JPH11177358A - Agc circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively expand a linear area of ΔΣAD converter and to improve bit error rate when a receiving input signal level fluctuates due to fading, etc. SOLUTION: A ΔΣAD converter 21 and a band pass filter 8 digital1y output an input IF signal. An enclosure detecting means 22 seeks the enclosure, subtracting means 10 subtracts reference value, a positive negative deciding means 23 decides an input level to the converter 21 and an output switching means 24 automatically switches β and γ by which an output of the means 10 is multiplied in accordance with its increase and decrease. An adding means 14 adds an output of a multiplying means 12 and an output of a delaying means 13. When a result whose integrated value is undergone positive negative decision by a positive negative deciding means 25 is positive, an output switching means 26 selects an output of the means 14, when it is negative, it selects zero and only a signal that is equal to or more than zero to the means 13 and a D/A converting means 16. Only when the output level of the converter 21 is larger than reference value, this AGC circuit is operated and the linear area of the converter 21 is expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AGC (automatic gain control) circuit, and more particularly, to a control of a conversion gain of a band-pass .DELTA..SIGMA. To an AGC circuit.

[0002]

2. Description of the Related Art When a bandpass type ΔΣ AD converter is used in a receiver for digital mobile communication or the like, an interference wave larger than a desired signal reception level is desired in order to remove the interference wave by baseband signal processing. It is necessary to have linearity that can be processed even if it exists simultaneously with the waves. In order to ensure linearity with respect to an assumed received signal level, in addition to the linearity of the AD converter, when the input level to the AD converter exceeds a predetermined reference signal level (reference value). , The sensitivity of the AD converter is automatically reduced and the signal level is
A function of adjusting the converter to the full scale value is required. That is, an automatic gain control (AGC) function is required.

As an example of controlling the output level according to the change in the input level in the conventional ΔΣ AD converter, there is “ALC circuit of delta-sigma modulator” disclosed in Japanese Patent Application Laid-Open No. 8-139607. Examples of the AGC circuit include those disclosed in JP-A-8-51329 and JP-A-9-74323.

A conventional bandpass type Δ 型 AD converter and AGC circuit will be described below. FIG. 3 shows a bandpass type Δ
This is an example of an AD converter. The ΔΣ AD converter shown here is a secondary ΔΣ AD converter. Two-stage transconductors 1 and 2 and tank circuits 3 and 4 having band limiting characteristics
A delay circuit 6 for delaying a 1-bit digital output of the comparator 5; and a 1-bit D / A converter 7 for D / A-converting a signal fed back from the delay circuit 6.
The center frequency of the tank circuits 3, 4 is equal to the input IF frequency. The result obtained by subtracting the feedback signal obtained by D / A converting the output of the delay circuit 6 by the D / A converter 7 from the input IF signal is
The signal is input to the first transconductor 1 and band-limited by the tank circuit 3. The result obtained by subtracting the feedback signal obtained by D / A converting the output of the delay circuit 6 by the D / A converter 7 from the output signal of the first transconductor 1 is input to the second transconductor 2. Restrict.
When the output of the delay circuit 6 is input to the digital bandpass filter 8, digital data corresponding to the input analog signal is obtained. That is, the bandpass type ΔΣA
A D converter is realized. At this time, by controlling the amount of feedback fed back to the inputs of the first and second transconductors 1 and 2 according to the input signal level, the output level of the ΔΣ AD converter can be controlled.

FIG. 4 is a circuit diagram showing a case where the output level of a ΔΣ AD converter is controlled by a conventional AGC circuit.
FIG. 5 shows the input / output characteristics of the ΔΣ AD converter at that time. In FIG. 4, 9 is an absolute value detection circuit, 10 is a subtractor, and 11 is F
The IR low-pass filter 12 is a multiplier. Reference numeral 15 denotes an integrator including the adder 14 and the delay unit 13. 16 is D
A / A converter 17 is an AGC amplifier. FIG.
In (a), solid line 1a shows the characteristics when AGC operation is not performed,
Dotted lines 1a and 2a show characteristics during the AGC operation.

In FIG. 5A, when the input signal level fluctuates due to fading or the like, the maximum output level at which the output signal with respect to the input modulation signal is not distorted is set as a reference value.
When the input signal level is ΔΣA from the level R in FIG.
Consider a case where the level changes to a level G exceeding the saturation level of the D converter. The AGC circuit in FIG. 4 obtains an envelope by detecting the absolute value of the output of the digital bandpass filter 8 by the absolute value detection circuit 9 and removing the carrier frequency component by the FIR low-pass filter 11. From the signal level of this envelope, a reference value which is a predetermined level is subtracted.
The difference is subtracted by 10 and the error a is output. The multiplier 12
The signal is multiplied by an error a and a coefficient ε (0 <ε <1) that determines the band of the feedback loop of the AGC circuit, that is, the loop band, and is output. Here, if ε is increased (to a value close to 1), the error a is output from the multiplier 12 as it is, so that a quick response with feedback is possible. However, the operation becomes unstable. When ε is reduced, the response becomes slower, but the operation becomes stable.

[0007] The integrator 15 integrates the output of the multiplier 12.
Here, the error a multiplied by ε smaller than 1 to obtain a value smaller than the original error is gradually added. D
The / A converter 16 converts the output of the integrator 15 into a control voltage Vc for controlling the gain of the AGC amplifier 17. AGC
The amplifier 17 has a gain variable width of several tens [dB]. The AGC amplifier 17 increases the gain by increasing the control voltage Vc, and increases the amount of feedback to the transconductors 1 and 2 so that the output level converges from point g1 to point g2 in FIG.

Next, consider the case where the input level decreases from level G in FIG. ΔΣAD
The input sensitivity of the converter is reduced at that point (dotted line 1).
Since a), the input signal is input to the point h1. Since the envelope-detected signal is smaller than the reference value, the error a output from subtracting the reference value is a negative signal. At this time, the value that has been integrated by the integrator 15 is m
Then, the adder 14 adds the error a, which is a negative signal, so that m decreases. Therefore, the control voltage Vc decreases, the AGC amplifier 17 lowers the gain, and converges the output level from the point h1 to the point h2 in FIG.
帰 還 Reduce the amount of feedback to the transconductors 1 and 2 so as to increase the sensitivity of the AD converter from the dotted line 1a to the dotted line 2a.

When the number of output bits of the integrator 15 is i, the output of the integrator 15 operates within a range of ± 2 ^i-1 with 0 as the center. For example, the gain control width of the AGC amplifier 17 is set to K [dB], the reference value is set to the maximum level at which the input modulation signal is not distorted, and the output of the integrator 15 is set to 0 at the center value.
When the gain of the GC amplifier 17 is set to be K / 2 [dB], the input / output characteristics of the ΔΣ AD converter are as shown by a solid line 1b in FIG. At this time, the level of the input signal shown in FIG.
, The error a becomes a positive signal, and the value integrated by the integrator 15 also becomes a positive signal. The gain of the AGC amplifier 17 is increased so that the output level Ho converges to the reference value.
The sensitivity of the converter is reduced from solid line 1b to dotted line 2b.
When the input signal level changes from the level C to a level Li smaller than the reference value, the error a becomes a negative signal, and the gain of the AGC amplifier 17 is reduced so that the output level Lo converges to the reference value. From the solid line 1b to the dotted line 1b. Therefore, as shown in FIG. 5B, the gain control width of the AGC circuit 17 is equal to the reference value ± K / 2 [d
B].

[0010]

SUMMARY OF THE INVENTION In the conventional configuration,
The response speed of the AGC circuit is determined by a coefficient ε multiplied by the multiplier 12, and this ε is set to a value such that the BER (bit error rate) is less deteriorated by the modulation method. That is, as far as possible, the BER does not deteriorate by following the envelope of the input signal within the range that can follow the fading.
It is set so that the GC response speed becomes slow.

In FIG. 5A, when the input level fluctuates from G to H and a signal is input to the point h1, the point h1 is in the linear region of the ΔΣ AD converter. However, when the input level fluctuates from R to G and the signal is input to point g1, the ΔΣ AD converter is saturated, and the signal is distorted until the output level converges to point g2, and the BER increases significantly. The state is deteriorated.

That is, when the input level decreases, the signal is always input to the linear region of the ΔΣ AD converter, so that the signal does not become distorted. Conversely, if the input level increases, the signal will always be in a distorted state. Until the output level converges to the reference value, the BER is greatly deteriorated. Therefore, it is necessary to converge the output to the reference value as quickly as possible within a range where the BER deterioration can be tolerated. However, the AG determined by the conventional coefficient ε
There is a problem that the response speed of the C circuit cannot cope.

The gain control width of the above-mentioned conventional AGC circuit is K [dB], as shown in FIG. Since the gain of the AGC amplifier 17 is set to be K / 2 [dB] when the output of the integrator 15 is the center value of 0, the input saturation level of the ΔΣ AD converter is expanded by K / 2 [dB]. Will be. However, even when the ΔΣ AD converter is operating in a linear range (when the output signal level is equal to or less than the reference value),
Since the AGC circuit operates by K / 2 [dB], ΔΣAD
For the purpose of expanding the linear region of the converter, the gain control width of the AGC amplifier 17 is wasted by K / 2 [dB].

In the example of FIG. 5B, when the center value of the output of the integrator 15 is set to 0, the gain of the AGC amplifier 17 becomes K /
This is an example in which the setting is made to be 2 [dB]. However, even if this setting is changed, when the output signal level is below the reference value,
Since the integrator 15 integrates the error a, which is a negative signal, the AGC
The circuit operates even below the reference value. Therefore, ΔΣ
There is a problem that the linear region of the AD converter and the gain control width of the AGC amplifier 17 are wasted.

Therefore, according to the present invention, when the output level of the AD converter is higher than the reference value, the BER is converged to the reference value at high speed within an allowable range, and the output level of the AD converter decreases. In such a case, it is necessary to reduce the AGC response speed as much as possible so as not to follow the envelope of the input signal, thereby improving the BER degradation.
The purpose of.

Furthermore, in order to ensure sufficient linearity even when the interfering wave and the desired wave are present at the same time, in addition to the linear region of the ΔΣ AD converter, the gain control variable width of the AGC amplifier and the Δ 、 AD converter are changed. It is a second object of the present invention to realize an AGC circuit that can be efficiently used to the maximum extent in the linear region with a simple configuration without increasing the hardware scale as compared with the conventional example.

[0017]

In order to achieve the above object, according to the present invention, an AGC circuit of a ΔΣ AD converter includes a positive / negative judging means for an error which is a difference between an output signal level and a reference value,
Switching means for switching a coefficient for determining the time constant of the AGC circuit according to the sign of the error is provided. With this configuration, when the output signal level exceeds the reference value, the output signal level quickly converges to the reference value, and when the output signal level does not exceed the reference value, the output signal does not follow the envelope but fading. Can be made to converge to the reference value.

A positive / negative determination means for an integrated value obtained by multiplying an AGC circuit of the ΔΣ AD converter by multiplying an error which is a difference between an output signal level and a reference value by a coefficient for determining a time constant;
When the integrated value is negative, 0 is output to the AGC amplifier and the AGC
A switching means for stopping the operation of the circuit is provided.
With this configuration, the AGC circuit is operated only when the input signal level is large and the output signal level exceeds the reference value, and the linear region of the ΔΣ AD converter is reduced by making full use of the gain control width of the AGC circuit. Can be expanded.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION
Band-limiting the signal obtained by subtracting the feedback signal from the input signal 1
Stage or a plurality of stages of band limiting means, a comparator for comparing an output of the band limiting means with a predetermined level, a delay circuit for delaying an output signal of the comparator, and a feedback signal based on an output of the delay circuit. Means for generating
An A / D converter, envelope detection means for obtaining an envelope from an output of a digital filter connected to the output side of the ΔΣ A / D converter, and subtraction means for obtaining an error obtained by subtracting a predetermined reference value from the envelope. Multiplying means for multiplying the error by a coefficient defining a constant to output an error for integration; adding means for integrating the error for integration and outputting an integrated value; and D / A for converting the integrated value to an analog signal Converting means, means for controlling the magnitude of the feedback signal by the analog signal, first positive / negative determining means for determining whether the error is positive or negative and outputting a first determination signal, and Automatic gain control (AGC) provided with means for switching coefficients
If the output signal level exceeds the reference value,
This has the effect of rapidly converging to the reference value.

The second aspect of the present invention is the first aspect.
In the automatic gain control (AGC) circuit described above, second positive / negative determining means for determining whether the integrated value is positive or negative and outputting a second determination signal; and determining only the positive integrated value based on the second determination signal. Means for inputting to the D / A conversion means, and has the effect of expanding the linear region of the ΔΣ AD converter.

According to a third aspect of the present invention, a difference signal is generated by subtracting a feedback signal from an input signal, and the difference signal is band-limited to generate a band-limited difference signal. Is compared with a predetermined level to generate a comparison result signal obtained by ΔΣ AD converting the input signal, generate the feedback signal based on a signal obtained by delaying the comparison result signal, and convert the comparison result signal into a digital value. Obtaining an envelope signal from the digital value; obtaining an error obtained by subtracting a predetermined reference value from the envelope signal; multiplying the error by a correction coefficient for determining a time constant to output an integration error; The error is integrated to obtain an integrated value, the integrated value is converted to an analog signal, the magnitude of the feedback signal is controlled according to the analog signal, the error is determined to be positive or negative, and a first determination signal is output. And said This is an automatic gain control method for switching the correction coefficient based on a first determination signal, and has an effect that when an output signal level exceeds a reference value, the output signal level quickly converges to the reference value.

The invention according to claim 4 of the present invention is the invention according to claim 3.
In the automatic gain control (AGC) method described above, a positive / negative of the integrated value is determined, a second determination signal is output, and only the positive integrated value is converted into an analog signal based on the second determination signal. Yes, it has the effect of expanding the linear region of the ΔΣ AD converter.

According to a fifth aspect of the present invention, a receiving IF
In a digital portable telephone equipped with an automatic gain control circuit for controlling the conversion gain of a bandpass type ΔΣ AD converter for AD converting a signal, one or more stages of band limiting for limiting a signal obtained by subtracting a feedback signal from an input signal Means,
A comparator that compares an output of the band limiting unit with a predetermined level, a delay circuit that delays an output signal of the comparator,
A ΔΣ AD converter having means for generating the feedback signal based on an output of the delay circuit; an envelope detection means for obtaining an envelope from an output of a digital filter connected to an output side of the ΔΣ AD converter; Subtraction means for obtaining an error obtained by subtracting a predetermined reference value from the line; multiplication means for multiplying the error by a coefficient defining a time constant to output an error for integration; and integrating the error for integration to output an integrated value Adding means for converting the integrated value into an analog signal, means for controlling the magnitude of the feedback signal based on the analog signal, determining whether the error is positive or negative, and outputting a first determination signal. And a means for switching the coefficient based on the first determination signal, wherein the received signal level of the mobile phone changes due to fading or the like. When the output signal level of the A / D converter exceeds the reference value, it has the effect of quickly converging to the reference value.

The invention according to claim 6 of the present invention provides the method according to claim 5.
A second positive / negative determining means for determining whether the integrated value is positive or negative and outputting a second determination signal;
Means for inputting only the positive integrated value to the D / A conversion means based on the determination signal, and has an effect of expanding the linear region of the ΔΣ AD converter of the mobile phone.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG.

In the embodiment of the present invention, when the output level is higher than the reference value, the time constant of the AGC circuit is switched to a smaller value, and when the output level is smaller than the reference value, the time constant is switched to a larger value. This is an automatic gain control (AGC) circuit that determines whether the AGC circuit is positive or negative and does not operate the AGC circuit if it is negative.

FIG. 1 is a principle diagram of an AGC circuit according to an embodiment of the present invention. In FIG. 1, the ΔΣ AD converter 21 includes:
This corresponds to the ΔΣ AD converter including the AGC amplifier of FIG. The envelope detection means 22 corresponds to the absolute value detection circuit 9 and the FIR filter 11 shown in FIG. As shown in FIG. 1, whether the input signal to the multiplying means 12 is positive or negative is determined by the positive / negative determining means 23 to determine whether the input signal to the ΔΣ AD converter 21 has increased or decreased, and based on the determination result, the AGC circuit The coefficients β and γ (β> γ) for determining the time constant are switched by the output switching means 24. Also, the sign of the output of the adding means 14 is judged by the sign judgment means 25, and based on the judgment result, only the signal of the positive sign is inputted to the D / A conversion means 16 and the delay means 13 by the output switching means 26. When the signal level is equal to or lower than the reference value, the AGC circuit is not operated.

FIG. 2 is a block diagram of the AGC circuit according to the embodiment of the present invention. This is an example of controlling the output level of the ΔΣ AD converter. Compared with the conventional example shown in FIG. 4, the newly provided elements are selectors 18 and 19, and the parts corresponding to the respective parts of the conventional example are denoted by the same reference numerals.

Referring to FIG. 2 and FIG. 5, ΔＡＧ
The operation when controlling the output level of the AD converter will be described. As shown in FIG. 5A, the input signal level of the ΔΣ AD converter changes from level R to level G, and
When the saturation level of the AD converter is exceeded, the AGC circuit generates Δ は
The sensitivity of the AD converter is reduced, and the operation characteristic changes from the solid line 1a to the dotted line 1a in FIG. The operating point is g1 to g
It changes to two points and operates in a direction to make the output level converge to the reference value. That is, when the input signal level of the ΔΣ AD converter increases, the output signal envelope detected by the absolute value detection circuit 9 and the FIR low-pass filter 11 becomes larger than the reference value. The error a with respect to the reference value becomes a positive signal, and the value m which has been integrated by the integrator 15 is further increased. Therefore, the control voltage Vc increases, and the AGC amplifier 17
Is increased, and the feedback amount to the transconductors 1 and 2 is increased, thereby reducing the sensitivity of the ΔΣ AD converter.

Next, the input level to the ΔΣ AD converter is
Assuming that the level decreases from level G to level H, AGC
The circuit increases the sensitivity of the ΔΣ AD converter, changes the operation characteristic from the dotted line 1a to the dotted line 2a, changes the operating point from the point h1 to the point h2, and operates in a direction to converge the output level to the reference value. Since the output level at the point h1 is smaller than the reference value, the envelope-detected signal is smaller than the reference value.
The error a with respect to the reference value is a negative signal. At this time, the integrator
The value m, which has been integrated up to that time at 15, is reduced by the adder 14 because it is added to the error a, which is a negative signal. Therefore, the control voltage Vc decreases, the gain of the AGC amplifier 17 decreases, and the amount of feedback to the transconductors 1 and 2 decreases, thereby increasing the sensitivity of the ΔΣ AD converter.

As described above, when the input level to the ΔΣ AD converter increases, the input to the multiplier 12 always becomes a positive signal, and when the input level decreases, it always becomes a negative signal.
In order to change the time constant of the AGC circuit according to the increase and decrease of the input level, the selector 18 is switched by the sign bit (most significant bit (MSB)) of the input signal of the multiplier 12 so that the time constant of the AGC circuit is changed. Are switched between the coefficients β and γ that determine. When the input signal level to the ΔΣ AD converter increases, β is multiplied, and when the input signal level decreases, γ is multiplied.
At this time, if the coefficients β and γ satisfy β> γ, the AGC circuit operates at high speed when the level of the input signal to the ΔΣ AD converter increases, and when the level decreases, the AGC response speed can be reduced. .

Further, when the level of the input signal of the ΔΣ AD converter is lowered, the absolute value detection circuit 9 and the FIR filter
The signal subjected to the envelope detection by 11 becomes a signal equal to or smaller than the reference value, and the error a output by subtracting the reference value by the subtracter 10 becomes a negative signal. The signal u input to the integrator 15 is also a negative signal, and the adder 14 adds the negative signal u and the value m accumulated so far. According to the sign bit (most significant bit (MSB)) of the signal s added by the adder 14, when s is positive, the selector 19 outputs s as it is,
If 0 is output when s is negative, only a value of 0 or more is input to the delay unit 13 and the D / A converter 16. When the value m accumulated up to that time is positive, the input u to the adder 14 is negative, and m + u is positive, m ≦ n × (−u)
The output of the integrator 15 becomes 0 at the nth clock. Since the clock cycle is usually much smaller than the set time constant (several ms), the delay of n clocks does not affect the response speed of AGC. The integrated value m is positive and the adder
When the input u is negative and m + u is negative, the integrator 15 immediately outputs 0. When the integrated value m and the input u to the adder 14 are both positive, a normal integration operation is performed.

As described above, when the output level of the ΔΣ AD converter is lower than the reference value, the output of the integrator 15 is always 0, and the gain of the AGC amplifier 17 is minimized. That is, A
The GC circuit does not operate, and the sensitivity of the ΔΣ AD converter is fixed to the maximum. Only when a signal whose output level is equal to or higher than the reference value is input, the integrator 15 performs a normal integration operation.
The AGC circuit can be operated. When the gain of the AGC amplifier 17 is the minimum, the ΔΣ AD converter has the maximum sensitivity. Therefore, when the input signal level is low, the ΔΣ AD converter is operated at the maximum sensitivity, the input signal level increases, and the output signal level falls below the reference value. If the AGC circuit is set to operate from the level exceeding, the gain control width of the AGC amplifier can be used to the maximum extent to effectively expand the linear region of the ΔΣ AD converter.

Although the case where the integrated value becomes negative is the easiest to detect, the present embodiment has been described with an example in which 0 is the minimum value. Value is detected as the minimum value, and that value is detected by the AGC amplifier 17.
If the setting is made so as to correspond to the minimum gain, the same function as in the above example can be achieved.

As described above, in the embodiment of the present invention,
When the output level is larger than the reference value, the time constant of the AGC circuit is switched to a smaller value when the output level is larger than the reference value, and when the output level is smaller than the reference value, the time constant is switched to a larger value. Since it is determined that the AGC circuit is not operated when the value is negative, the AGC circuit operates at a high speed when the input signal level increases, and the linear region of the ΔΣ AD converter is expanded.

[0036]

As described above, according to the present invention, the time constant of the AGC circuit is switched to a smaller value when the output level is larger than the reference value, and the time constant is changed when the output level is smaller than the reference value. A means for switching to a large value is provided, and the input signal level fluctuates due to fading or the like,
When the output level is higher than the reference value, the AGC circuit is operated at a high speed.
Since the configuration is such that the GC response speed is slowed, the effect of improving the BER deterioration due to the fluctuation of the input signal level can be obtained.

Further, in the AGC circuit of the ΔΣ AD converter,
A means for outputting 0 when the integrated value is negative is provided so that the AGC circuit is not operated below a predetermined input signal level, so that the gain control width of the AGC amplifier is expanded in the linear region of the ΔΣ AD converter. And the linearity that can sufficiently cope with the desired wave and the interfering wave can be obtained.

[Brief description of the drawings]

FIG. 1 is a principle diagram of an AGC circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a configuration of an AGC circuit according to the embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a conventional ΔΣ AD converter;

FIG. 4 is a block diagram showing a configuration of a conventional AGC circuit;

FIG. 5 is a diagram of input / output characteristics of a ΔΣ AD converter for explaining an AGC operation;

[Explanation of symbols]

 1, 2 Transconductor 3, 4 Tank circuit 5 Comparator 6, 13 Delay means 7, 16 D / A conversion means 8 Bandpass filter 9 Absolute value detection circuit 10 Subtraction means 11 FIR filter 12 Multiplication means 14 Addition means 15 Integrator 21 ΔΣ AD converter 22 Envelope detection means 23, 25 Positive / negative judgment means 24, 26 Output switching means

Claims (6)

[Claims] 1. A single-stage or plural-stage band limiter for band-limiting a signal obtained by subtracting a feedback signal from an input signal; a comparator for comparing an output of the band-limiter with a predetermined level; A Δ 回路 AD converter having a delay circuit for delaying an output signal, and a means for generating the feedback signal based on the output of the delay circuit; and an envelope from the output of a digital filter connected to the output side of the ΔΣ AD converter. An envelope detection means for obtaining, an subtraction means for obtaining an error obtained by subtracting a predetermined reference value from the envelope, a multiplication means for multiplying the error by a coefficient defining a time constant to output an error for integration, Adding means for integrating the error and outputting an integrated value; D / A converting means for converting the integrated value into an analog signal; means for controlling the magnitude of the feedback signal by the analog signal; Automatic gain control circuit, wherein the first polarity determination means for outputting a first determination signal to determine the sign of the error, in that a means for switching the coefficients based on the first determination signal. 2. A second positive / negative determining means for determining whether the integrated value is positive or negative and outputting a second determination signal, and outputting only the positive integrated value to the D / A converting means based on the second determining signal. 2. An automatic gain control circuit according to claim 1, further comprising means for inputting. 3. A difference signal is generated by subtracting a feedback signal from an input signal, a band-limited difference signal is generated by band-limiting the difference signal, and the band-limited difference signal is compared with a predetermined level. Generating a comparison result signal obtained by performing ΔΣ AD conversion on the input signal; generating the feedback signal based on a signal obtained by delaying the comparison result signal; converting the comparison result signal into a digital value; Is obtained, an error obtained by subtracting a predetermined reference value from the envelope signal is obtained, the error is multiplied by a correction coefficient for determining a time constant, an error for integration is output, and the error for integration is integrated to obtain an integrated value. Converting the integrated value into an analog signal, controlling the magnitude of the feedback signal according to the analog signal, determining whether the error is positive or negative, and outputting a first determination signal, based on the first determination signal. Repair Automatic gain control method characterized by switching the coefficients. 4. The method according to claim 3, wherein a positive / negative value of the integrated value is determined, a second determination signal is output, and only the positive integrated value is converted into an analog signal based on the second determination signal. Automatic gain control method as described. 5. A digital portable telephone equipped with an automatic gain control circuit for controlling a conversion gain of a band-pass ΔΣ AD converter for AD-converting a received IF signal, wherein a signal obtained by subtracting a feedback signal from an input signal is band-limited. Stage or a plurality of stages of band limiting means, a comparator for comparing an output of the band limiting means with a predetermined level, a delay circuit for delaying an output signal of the comparator, and a feedback signal based on an output of the delay circuit. And an envelope detector for obtaining an envelope from an output of a digital filter connected to an output side of the ΔΣ AD converter, and an error obtained by subtracting a predetermined reference value from the envelope. Subtraction means, a multiplication means for multiplying the error by a coefficient defining a time constant to output an error for integration, and an addition for integrating the error for integration and outputting an integrated value Means, D / A conversion means for converting the integrated value into an analog signal, means for controlling the magnitude of the feedback signal based on the analog signal, and means for determining whether the error is positive or negative and outputting a first determination signal. 1. A mobile phone comprising: a positive / negative determination unit; and a unit for switching the coefficient based on the first determination signal. 6. A second positive / negative determining means for determining whether the integrated value is positive or negative and outputting a second determination signal, and outputting only the positive integrated value to the D / A converting means based on the second determining signal. 6. The mobile phone according to claim 5, further comprising means for inputting.