JP3289590B2 - Class D power amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a class D power amplifier for driving a load such as a speaker in audio equipment.

[0002]

2. Description of the Related Art A power amplifier in an audio device modulates a DC voltage supplied from a DC power supply based on an input signal.
Usually, a waveform similar to an input signal is supplied to a speaker as a load.

[0003] In such a power amplifier, power loss is reduced as much as possible and power conversion efficiency is improved, for example, as described in the IEEE Conference on July 6-8, 1994.
Publication No.393 "Linearization
Of Class D Output Stage For Four
High Performance Audio Power Amplifiers ”(IEE 6-8 July 1994 Conference Publica
tion No.393 "LINEARIZATION OF CLASS D OUTPUT STAGE
S FOR HIGH-PERFORMANCE AUDIO POWER AMPLIFIERS ").

Hereinafter, a conventional class D power amplifier will be described. FIG. 10 shows a configuration of a conventional class D power amplifier. 1001 is an input terminal for inputting a binary signal, 1
002, a delay line having a plurality of delay taps for delaying an input binary signal; 1003, a power switch for amplifying the output of the delay line 1002;
4 is a low-pass filter for smoothing the output of the power switch 1003, 1005 is an output terminal for supplying the output of the low-pass filter 1004 to the load, 1006 is an attenuator for attenuating the output amplitude of the power switch 1003, 1007 is an attenuator 1006 and a delay line An adder 1002 calculates a difference between the output of the intermediate delay tap 1002 and an adder 1008.
A low-pass filter for smoothing the output of 07, a selection circuit 1009 for selecting the delay tap of the delay line 1002 based on the output of the low-pass filter 1008, and a reference numeral 1010 for the delay line 100 based on the output of the selection circuit 1009
2 is a switch for switching between two delay taps.

[0005] The operation of the conventional class D power amplifier configured as described above will be described. A binary signal (for example, a signal obtained by converting an audio signal into a PWM signal) input from an input terminal 1001 is delayed by a delay line 1002. The power switch 1003 amplifies the power of this signal,
The low-pass filter 1004 smoothes (demodulates to the original audio signal) and supplies power to the load via the output terminal 1005. By the way, the output of the power switch 1003 generates waveform distortion due to factors such as overshoot and ringing due to ripple and switching of the supplied power, and as a result, waveform distortion occurs at the output terminal 1005.
Therefore, the attenuator 1006 attenuates the output of the power switch 1003 to a predetermined level (a level at which the operation can be performed by the adder 1007, that is, a level equivalent to the output of the delay line 1002). The difference from the output from the intermediate delay tap on line 1002 is calculated.

Here, the delay time of the minimum delay tap of the delay line 1002 is zero, the delay time of the intermediate delay tap is equal to the propagation delay time of the power switch 1003,
The input of the power switch 1003 is the delay line 100
Assuming that the power switch 1003 is currently connected to the second minimum delay tap, the output of the adder 1007 becomes zero if no waveform distortion occurs in the power switch 1003. Power switch 1
When the waveform distortion occurs in 003, the adder 1007
The waveform distortion of the power switch 1003 attenuated by the attenuator 1006 is output. That is, a signal proportional to the waveform distortion generated by the power switch 1003 is output to the adder 1007. Then, the low-pass filter 1008 smoothes this signal, and the selection circuit 1009 determines the delay time of the signal input to the power switch 1003 based on the output of the low-pass filter 1008 so that the output of the low-pass filter 1008 becomes zero. And the switch 10
Reference numeral 10 switches the delay tap of the delay line 1002 based on the output of the selection circuit 1009.

That is, by detecting the waveform distortion generated by the power switch 1003 and controlling the timing of the binary signal input to the power switch 1003 by the delay line 1002 in accordance with the amount of the waveform distortion, the conventional class D signal is obtained. The power amplifier is configured to cancel the waveform distortion generated by the power switch 1003.

[0008]

However, the above-mentioned conventional configuration has the following problems.

That is, in the above-described conventional configuration, the waveform distortion generated in the power switch is canceled by controlling the input timing of the binary signal to the power switch according to the amount. However, in order to sufficiently cancel the waveform distortion, it is necessary to improve the resolution of the delay line to increase the circuit scale, and the entire system has a configuration in which the delay is increased. Since the previous signal is held, the power switch amplifies a signal different from the originally input binary signal. Therefore, when the FFT analysis of the output signal supplied from the output terminal to the load is performed by the operation simulation, the noise floor is increased as compared with before the countermeasure against the waveform distortion, and the volume of the power amplifier cannot be controlled. Had problems.

The present invention solves the above-mentioned conventional problem. When converting an input signal into a binary signal, the reference level of a quantizer in a ΔΣ modulator is adjusted so that detected waveform distortion becomes zero. In addition, by adopting a configuration in which the reference level of the quantizer is changed so that the amplitude level difference between the reference signal and the output signal of the present power amplifier becomes zero, the circuit scale increases. It is an object of the present invention to provide a class D power amplifier capable of canceling waveform distortion and controlling the volume without increasing the noise floor.

[0011]

In order to achieve this object, a class D power amplifier according to the present invention comprises a ΔΣ modulator having a quantizer for converting an input signal into a binary signal, and an output of the ΔΣ modulator. A power switch for amplifying power, a first low-pass filter for smoothing the output of the power switch, a delay for delaying the output of the Δ と modulator, an attenuator for attenuating the output amplitude of the power switch, and an output and attenuator for the delay An adder for calculating a difference from the output of the adder, and a second for smoothing the output of the adder.
And a selection circuit for selecting the reference level of the quantizer based on the output of the second low-pass filter.

Thus, a class D power amplifier capable of canceling the waveform distortion generated by the power switch is obtained.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a ΔΣ modulator having a quantizer for converting an input signal into a binary signal, a power switch for amplifying the output of the ΔΣ modulator, and an output of the power switch. A first low-pass filter for smoothing, a delay for delaying the output of the ΔΣ modulator, an attenuator for attenuating the output amplitude of the power switch, and calculating a difference between the output of the delay and the output of the attenuator. An adder,
A class D power amplifier comprising: a second low-pass filter for smoothing the output of the adder; and a selection circuit for selecting a reference level of the quantizer based on the output of the second low-pass filter. This has the following effects. That is, the input signal is converted into a binary signal by a ΔΣ modulator having a quantizer. The binary signal is power-amplified by the power switch, smoothed by the first low-pass filter, and supplied to the load. On the other hand, the delay delays the output of the ΔΣ modulator, and the attenuator attenuates the output amplitude of the power switch to be equal to the output amplitude of the delay. Then, the adder calculates a difference between the output of the delay and the output of the attenuator, and smoothes the output with a second low-pass filter to detect a waveform distortion generated by the power switch. The selection circuit selects a reference level of the one-bit quantizer according to the waveform distortion amount. As a result, the ΔΣ modulator converts the input signal into a binary signal so as to cancel the waveform distortion. Thus, the waveform distortion is canceled.

The present invention also provides a ΔΣ modulator having a quantizer for converting an input signal into a binary signal, a power switch for amplifying the output of the ΔΣ modulator, and a power switch for smoothing the output of the power switch. 1 low-pass filter and the Δ
A delay that delays the output of the modulator, an attenuator that attenuates the output amplitude of the power switch, an adder that calculates the difference between the output of the delay and the output of the attenuator, and an output of the adder. A class D power amplifier comprising: a second low-pass filter for smoothing; and a selection circuit for selecting a reference level of the quantizer based on an amplitude of the input signal and an output of the second low-pass filter. This has the following effects. That is, the input signal is converted into a binary signal by a ΔΣ modulator having a quantizer. The binary signal is power-amplified by the power switch, smoothed by the first low-pass filter, and supplied to the load. On the other hand, the delay delays the output of the ΔΣ modulator, and the attenuator attenuates the output amplitude of the power switch to the same level as the output amplitude of the delay. Then, the adder calculates a difference between the output of the delay and the output of the attenuator, and smoothes the output with a second low-pass filter to detect a waveform distortion generated by the power switch.
Then, the selection circuit selects the reference level of the 1-bit quantizer according to the amplitude of the input signal and the amount of waveform distortion. as a result,
The ΔΣ modulator converts an input signal into a binary signal so as to cancel waveform distortion. Thus, the waveform distortion is canceled.

Further, the present invention provides a ΔΣ modulator having a quantizer for converting an input signal into a binary signal, a power switch for amplifying the power of the output of the ΔΣ modulator, and a power switch for smoothing the output of the power switch. 1 low-pass filter and the Δ
デ ィ レ イ A delay that delays the output of the modulator, an attenuator that attenuates the output amplitude of the power switch that can vary the amount of attenuation by an external control signal, and calculates a difference between the output of the delay and the output of the attenuator. Class D power amplifier, comprising: an adder for performing the above operation; a second low-pass filter for smoothing the output of the adder; and a selection circuit for selecting a reference level of the quantizer based on the output of the second low-pass filter. This has the following effects. That is, the input signal is converted into a binary signal by a ΔΣ modulator having a quantizer. The binary signal is power-amplified by the power switch, smoothed by the first low-pass filter, and supplied to the load. On the other hand, the delay delays the output of the ΔΣ modulator and the attenuation of the attenuator is variable, so that the output amplitude of the power switch is attenuated according to the given attenuation. Then, the adder calculates the difference between the output of the delay and the output of the attenuator, and smoothes the difference with a second low-pass filter to obtain the waveform distortion generated by the power switch and the amplitude of the output of the delay and the output of the attenuator. Detect level differences. The selection circuit selects a reference level of the 1-bit quantizer according to the waveform distortion amount and the amplitude level difference. As a result, the ΔΣ modulator cancels the waveform distortion by converting the input signal into a binary signal so that the detected waveform distortion becomes zero. Further, the volume of the power amplifier is controlled by converting the input signal into a binary signal so that the amplitude level difference between the reference signal and the output signal of the power amplifier becomes zero.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a class D power amplifier according to Embodiment 1 of the present invention. In FIG. 1, 1
01 is an input terminal, 102 is a ΔΣ modulator that converts an input signal from the input terminal 101 into a binary signal, 103 is a quantizer, 104 is an adder that calculates a quantization error generated by the quantizer 103. , 105 are loop filters for controlling the frequency characteristics of the quantization error, 106 is an adder for calculating the difference between the input signal and the output of the loop filter 105, and constitutes the ΔΣ modulator 102. 107 is a power switch that amplifies the output signal of the ΔΣ modulator 102, 108 is a low-pass filter that smoothes the output signal of the power switch 107,
An output terminal 109 supplies the output of the low-pass filter 108 to a load such as a speaker.
7, an attenuator for attenuating the output amplitude to a predetermined level; 111, a delay for delaying the output of the ΔΣ modulator 102 by the propagation delay time of the power switch 107;
An adder for calculating the difference between 0 and the delay 111; 113, a low-pass filter for smoothing the output of the adder 112;
Is the quantizer 10 based on the output of the low-pass filter 113.
3 is a selection circuit for selecting the third reference level.

FIG. 2 is an explanatory diagram of the operation of the class D power amplifier according to the present embodiment, and is an explanatory diagram relating to waveform distortion generated by the power switch 107. In FIG. 2, a broken line shows an ideal waveform, and a solid line shows an actual waveform. FIG. 2A shows a case of waveform distortion due to power supply ripple, and FIG. 2B shows a case of waveform distortion due to switching overshoot or ringing. .

FIG. 3 is an explanatory diagram of the operation of the class D power amplifier according to the present embodiment, and shows an output waveform when the reference level of the quantizer 103 is changed. 3A shows a case where the reference level of the quantizer is zero, FIG. 3B shows a case where the reference level of the quantizer is positive, and FIG. 3C shows a case where the reference level of the quantizer is negative. .

FIG. 4 is an explanatory diagram of the operation of the class D power amplifier according to the present embodiment, showing the correspondence between the waveform distortion of the power switch 107 and the reference level of the quantizer 103. In FIG. 4, (a) shows waveform distortion of the power switch 107 (broken line is an ideal waveform, solid line is an actual waveform), (b) shows detected waveform distortion (output of the low-pass filter 113), and (c) shows a quantizer. 103 is a reference level (output of the selection circuit 114).

FIG. 5 is a block diagram showing an example of an actual configuration of the selection circuit 114 and the quantizer 103 in the class D power amplifier according to the present embodiment. 5A shows a case where the input signal from the input terminal 101 is an analog signal, and FIG. 5B shows a case where the input signal is a digital signal.

The operation of the class D power amplifier according to the present embodiment thus configured will be described below.

An input signal is input from an input terminal 101. Here, assuming a class D power amplifier for audio, the input signal is an audio signal, and the basic processing is the same whether the signal is an analog signal or a digital signal (PCM signal). The difference is that each of the blocks 103 to 106 constituting the ΔΣ modulator 102 has an analog configuration or a digital configuration. Less than,
The case where the output of the quantizer 103 is 1 bit (binary) will be described as an example. Even when the quantizer is multi-valued, a pulse width modulation (PWM) device is provided after the quantizer, Is converted into a binary signal, the same result is obtained.

The ΔΣ modulator 102 detects a quantization error generated in the quantizer 103 by the adder 104 calculating the difference between the input and output signals of the quantizer 103, and the loop filter 105 detects the quantization error. The frequency characteristics are processed and the adder 10
At 6, it is added to the input signal, and the quantizer 103 changes it to a binary signal. In this process, the frequency characteristic of the quantization error generated in the quantizer 103 when the input signal is converted into the binary signal is controlled to increase the SN ratio in the audible range.

Next, the power switch 107 power-amplifies the output signal of the ΔΣ modulator 102. Then, the low-pass filter 108 converts the power-amplified binary signal to an analog signal, and supplies power to the load via the output terminal 109. In this way, the class-D power amplifier once converts the input signal into a binary signal and amplifies the power, so that the power device that amplifies the power operates in saturation and no loss occurs. Therefore, a power amplifier with high power efficiency can be configured.

On the other hand, when the power switch 107 power-amplifies the binary signal, as shown in FIG. 2, waveform distortion due to power supply ripple and overshoot generated due to switching,
Waveform distortion such as ringing occurs. Therefore, in order to detect this waveform distortion, the attenuator 110 is connected to the power switch 10.
7 is attenuated to a level equivalent to the amplitude level of the output signal of the delay 111. The delay 111 is the propagation delay time of the power switch 107,
Is delayed. Then, the adder 112 calculates the difference between the output signals of the attenuator 110 and the delay 111.
Then, the low-pass filter 113 smoothes the output signal of the adder 112 and detects waveform distortion. The selection circuit 114
Power switch 1 output from low-pass filter 113
07, the quantizer 10 according to the magnitude of the waveform distortion generated.
Select a reference level of 3.

If the quantizer 103 is a one-bit quantizer, the reference level for quantizing the input signal is usually zero. In this case, -1 is output and the input signal is amplitude ± 1.
Into a pulse train. This is amplified by the power switch 107 and smoothed by the low-pass filter 108, so that the average value of the pulse train is output, and a desired power-amplified analog audio signal is obtained. That is, the average value of the pulse train becomes the output audio signal waveform. Therefore, FIG.
As shown in (1), when the reference level of the quantizer 103 is changed from zero to positive, the average value of the pulse train increases in the negative direction, and when the reference level is changed from zero to negative, the average value of the pulse train increases in the positive direction. Therefore, as shown in FIG. 4, in accordance with the magnitude of the detected waveform distortion, the reference level is changed from zero to a positive direction if the amplitude of the waveform distortion is canceled. (In the negative direction) to the quantizer 10
3 is changed to remove the waveform distortion from the output of the low-pass filter 108. That is, the input signal is converted into a binary signal so as to cancel the detected waveform distortion.

Further, the selection circuit 114 and the quantizer 103
Will be described with reference to FIG. When the input signal is analog, the quantizer 103 can be realized by a comparator. Therefore, as shown in FIG.
Reference numeral 4 may control the reference level of the comparator according to the output of the low-pass filter 113.

When the input signal is digital, FIG.
As shown in (b), the selection circuit 114 converts the output of the low-pass filter 113 into a digital signal with an A / D converter, decodes the digital signal with a decoder based on the digital signal, and determines the reference level of the quantizer 103. I do. here,
Since the level of the waveform distortion is smaller than the output level of the power switch 103, the resolution of the A / D converter may be several bits.

As described above, in the present embodiment, the waveform distortion generated by the power switch 107 is detected, and the reference level of the quantizer 103 is controlled according to the level of the waveform distortion.
The modulator 102 removes the waveform distortion with a simple configuration that binarizes the input signal so as to cancel the waveform distortion. As a result, a class D power amplifier having a low distortion factor and low power loss is configured.

(Embodiment 2) FIG. 6 shows a block diagram of a class D power amplifier according to Embodiment 2 of the present invention.
6, reference numeral 601 denotes an input terminal, and 602 denotes an input terminal 6.
Reference numeral 603 denotes a quantizer, 604 denotes an adder that calculates a quantization error generated by the quantizer 603, and 605 denotes a frequency characteristic of the quantization error. 606 is an adder for calculating the difference between the input signal and the output of the loop filter 605, and constitutes the ΔΣ modulator 602. 607, a power switch for amplifying the output signal of the ΔΣ modulator 602;
608, a low-pass filter for smoothing the output signal of the power switch 607; 609, an output terminal for supplying the output of the low-pass filter 608 to the load; 610, an attenuator for attenuating the output amplitude of the power switch 607 to a predetermined level;
1 is a delay for delaying the output of the ΔΣ modulator 602 by the propagation delay time of the power switch 607, 612 is an adder for calculating the difference between the attenuator 610 and the delay 611, 613
Is a low-pass filter for smoothing the output of the adder 612;
A selection circuit 14 selects the reference level of the quantizer 603 based on the input signal and the output of the low-pass filter 613.

FIG. 7 is a block diagram showing a configuration example of the selection circuit 614 in the class D power amplifier according to the present embodiment. In FIG. 7, (a) shows a case where the input signal is analog,
(B) shows a case where the input signal is digital. FIG.
7A, reference numeral 701 denotes a delay for delaying an input signal from the input terminal 601 by a propagation delay time of the ΔΣ modulator 602 and the power switch 607, and 702 denotes a level for determining whether the level of the input signal is equal to or higher than a predetermined level. A decision unit 703 is a variable gain amplifier whose gain is determined by the output of the level decision unit 702 and amplifies the output of the low-pass filter 613.

In FIG. 7B, reference numeral 704 denotes ΔΣ
A delay for delaying an input signal from the input terminal 601 by a propagation delay time of the modulator 602 and the power switch 607, a level determination unit 705 for determining whether the level of the input signal is equal to or higher than a predetermined level, and a reference numeral 706 for a low-pass filter 613. A / D converter (hereinafter simply referred to as A / D in the figure) for converting the output of the A / D into a digital signal, and 707 is an A / D converter 7
06 and the output of the level determiner 705
03 is a decoder for determining the reference level.

The operation of the class D power amplifier according to the present embodiment thus configured will be described below.

In FIG. 6, components other than the selection circuit 614 perform the same operations as in the first embodiment shown in FIG. Therefore, only for operations different from those in FIG.
Give an explanation. The selection circuit 614 includes the low-pass filter 61
3 and a reference level of the quantizer 603 based on the input signal from the input terminal 601. Specifically, the selection circuit 614 can be configured by a configuration block as shown in FIG.

First, the case where the input signal is an analog signal will be described. As shown in FIG. 7A, an input signal is supplied to a delay 701 by a ΔΣ modulator 602 and a power switch 60.
7 is delayed by a time corresponding to the sum of the propagation delay times. Then, the level determiner 702 determines whether the level of the input signal is equal to or higher than a predetermined level. On the other hand, the variable gain amplifier 7
Numeral 03 can change the gain by an external gain control signal. Here, the output of the level determiner 702 controls the gain of the variable gain amplifier 703. Then, the output of the low-pass filter 613 is amplified, and the reference level of the quantizer 603 is determined as shown in FIG. here,
The variable gain amplifier 703 has a configuration in which the gain is reduced when the level of the input signal is equal to or higher than a predetermined level, and the gain is increased when the level is lower than the predetermined level.

The distortion output to the output terminal 609 due to the waveform distortion generated in the power switch 607 has a large effect on the SN ratio when the input signal level is low. Conversely, if the input signal level is large,
The effect of this distortion on the SN ratio is small. Therefore, when the input signal level is small, the gain of the variable gain amplifier 703 is increased to amplify the error signal (waveform distortion) and cancel the waveform distortion generated in the power switch 607.

Next, the case where the input signal is a digital signal will be described. As shown in FIG. 7B, the input signal is supplied to a delay 704 by a ΔΣ modulator 602 and a power switch 6.
07, which is a time delay corresponding to the sum of the propagation delay times. Then, the level determiner 705 determines whether the level of the input signal is equal to or higher than a predetermined level. The A / D converter 70
6 converts the output of the low-pass filter 613 into a digital signal. Output of A / D Converter 706 and Level Judgment Unit 7
The decoder 707 decodes the reference level of the quantizer 603 based on the output of the decoder 05. Here, as in FIG. 7A, when the input signal level is low, the reference level of the quantizer 603 is decoded in a direction to strongly cancel the waveform distortion generated by the power switch.

As described above, in the present embodiment, the waveform distortion generated by the power switch 607 is detected, and the reference level of the quantizer 603 is controlled in accordance with the level of the waveform distortion and the input signal level, and the ΔΣ modulation is performed. The waveform distortion is removed by a simple configuration for converting the input signal into a binary signal so that the waveform distortion is canceled by the detector 602. As a result, a class D power amplifier having a low distortion rate and a small power loss even at the time of a small signal is configured.

(Embodiment 3) FIG. 8 is a block diagram showing a class D power amplifier according to Embodiment 3 of the present invention.

In FIG. 8, reference numeral 801 denotes an input terminal;
Is a ΔΣ modulator for converting an input signal from the input terminal 801 into a binary signal, 803 is a quantizer, 804 is an adder for calculating a quantization error generated by the quantizer 803,
Reference numeral 5 denotes a loop filter for controlling the frequency characteristic of the quantization error. Reference numeral 806 denotes an adder for calculating a difference between the input signal and the output of the loop filter 805. The adder 5 constitutes a ΔΣ modulator 802.
Reference numeral 807 denotes a power switch that amplifies the output signal of the ΔΣ modulator 802, 808 denotes a low-pass filter that smoothes the output signal of the power switch 807, 809 denotes an output terminal that supplies the output of the low-pass filter 808 to a load, and 810 denotes a power switch 807. An attenuator for attenuating the output amplitude of the power switch to a predetermined level; 811 a delay for delaying the output of the ΔΣ modulator 802 by the propagation delay time of the power switch 807;
812, an adder that calculates the difference between the attenuator 810 and the delay 811; 813, a low-pass filter that smoothes the output of the adder 812; 814, a selection circuit that selects the reference level of the quantizer 803 based on the output of the low-pass filter 813 , 815 are input terminals for inputting a control signal for controlling the amount of attenuation of the attenuator 810.

FIG. 9 is a diagram for explaining the operation of the class D power amplifier according to the present embodiment. FIG. 9A shows the case where the signal amplitude levels of the output of the attenuator 810 and the output of the delay 811 are equal.
(B) shows a case where the output of the attenuator 810 has a higher signal amplitude level than the output of the delay 811.

The operation of the class D power amplifier of this embodiment having the above-described configuration will be described below.

In FIG. 8, components other than the attenuator 810 perform the same operations as those in the first embodiment shown in FIG. Therefore, only operations different from those in FIG. 1 will be described. The amount of attenuation of the attenuator 810 is determined by the signal from the input terminal 815, and the output signal of the power switch 807 is attenuated. Adder 812 calculates the difference between the output of attenuator 810 and the output of delay 811, and the output is smoothed by low-pass filter 813. The amplitude value of the smoothed signal is determined by the difference between the output amplitude levels of the delay 811 and the attenuator 810, and a waveform similar to the signal output from the output terminal 809 is added with the waveform distortion generated by the power switch 807. It is a thing. The selection circuit 814 determines the reference level of the quantizer 803 according to the signal level. Therefore, the ΔΣ modulator 802 has the low-pass filter 8
The input signal is converted into a binary signal so that the output of the signal 13 becomes zero.

That is, when the amount of attenuation of the attenuator 810 is set so that the output amplitude level of the attenuator 810 and the output amplitude level of the delay 811 become equal, the output of the low-pass filter 813 becomes power as shown in FIG. The waveform distortion is generated by the switch 807, and the ΔΣ modulator 802 converts the input signal into a binary signal so as to cancel the waveform distortion. Therefore, no waveform distortion occurs at the output terminal 809.

When the amount of attenuation of the attenuator 810 is set so that the output amplitude level of the attenuator 810 is larger than the output amplitude level of the delay 811, the output of the low-pass filter 813 becomes as shown in FIG. , Attenuator 810
And a signal having an amplitude corresponding to the level difference between the output of the delay 811 and the signal similar to the signal output from the output terminal 809 and the waveform distortion generated by the power switch 807 are added, and this signal is canceled. Modulator 802 converts the input signal into a binary signal. Therefore, the waveform distortion generated by the power switch 807 is canceled, and no waveform distortion occurs at the output terminal 809.
In addition, since a signal similar to the output signal of the class D power amplifier according to the present embodiment is fed back and operates so as to cancel this signal, the operation of attenuating the output signal level of the class D power amplifier according to the present embodiment is performed. Do. Therefore, the output amplitude level of the class D power amplifier according to the third embodiment can be controlled by controlling the amount of attenuation of the attenuator 810.

Also, the output level of the attenuator 810 is lower than the output level of the delay 811.
Here, the attenuation amount of 10 does not exist here.

As described above, in the third embodiment, the waveform distortion generated by the power switch 807 is detected,
The reference level 3 is controlled, and the ΔΣ modulator 802 converts the input signal into a binary signal so as to cancel the waveform distortion, thereby removing the waveform distortion. Further, by controlling the reference level of the quantizer 803 with a signal similar to the output signal of the class D power amplifier, the amplitude level of the output signal of the class D power amplifier is controlled, that is, volume control is performed. As a result, a class D power amplifier with low distortion, volume controllable, and low power loss is configured.

[0048]

As described above, according to the present invention, the waveform distortion generated by the power switch is detected, and according to the level of the waveform distortion, .DELTA.
By controlling the reference level of the quantizer in the Σ modulator and converting the input signal into a binary signal by the ΔΣ modulator so as to cancel the waveform distortion, the waveform distortion can be canceled with a simple configuration. . For this reason, an effect of enabling a low distortion factor of the class D power amplifier can be obtained.

Further, by controlling the reference level of the quantizer in the ΔΣ modulator according to the detected waveform distortion level and the input signal level, the waveform distortion can be canceled even when the signal is small. For this reason, an effect of enabling a low distortion factor at the time of a small signal of the class D power amplifier is obtained.

Further, by controlling the reference level of the quantizer,
Although it has a configuration to cancel the waveform distortion, since the quantizer is in the loop of the ΔΣ modulator, controlling the reference level of the quantizer does not change the SN ratio of the ΔΣ modulator. Therefore, the effect of enabling the class D power amplifier to have a high SN ratio can be obtained.

Further, by controlling the reference level of the quantizer with a signal similar to the output signal of the class D power amplifier, the amplitude level of the output signal of the class D power amplifier can be controlled, that is, volume control can be performed. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a class D power amplifier according to a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram illustrating the operation of the class D power amplifier.

FIG. 3 is an operation explanatory diagram illustrating the operation of the class D power amplifier.

FIG. 4 is an operation explanatory diagram illustrating the operation of the class D power amplifier.

FIG. 5 is a block diagram showing a configuration example of a selection circuit and a quantizer of the class D power amplifier.

FIG. 6 is a block diagram showing a configuration of a class D power amplifier according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration example of a selection circuit of the class D power amplifier.

FIG. 8 is a block diagram showing a configuration of a class D power amplifier according to a third embodiment of the present invention.

FIG. 9 is an operation explanatory diagram illustrating the operation of the class D power amplifier.

FIG. 10 is a block diagram showing a configuration of a conventional class D power amplifier.

[Explanation of symbols]

 101 input terminal 102 ΔΣ modulator 103 quantizer 104, 106, 112 adder 105 loop filter 107 power switch 108, 113 low-pass filter 109 output terminal 110 attenuator 111 delay 114 selection circuit

Claims (3)

(57) [Claims] 1. A ΔΣ modulator having a quantizer for converting an input signal into a binary signal, a power switch for amplifying an output of the ΔΣ modulator, and a first low-pass for smoothing an output of the power switch A filter, a delay for delaying an output of the ΔΣ modulator, an attenuator for attenuating an output amplitude of the power switch, an adder for calculating a difference between an output of the delay and an output of the attenuator, and the addition. A class D power amplifier comprising: a second low-pass filter for smoothing an output of a quantizer; and a selection circuit for selecting a reference level of the quantizer based on an output of the second low-pass filter. 2. A ΔΣ modulator having a quantizer for converting an input signal into a binary signal, a power switch for amplifying power of an output of the Δ 電力 modulator, and a first low-pass for smoothing an output of the power switch. A filter, a delay for delaying an output of the ΔΣ modulator, an attenuator for attenuating an output amplitude of the power switch, an adder for calculating a difference between an output of the delay and an output of the attenuator, and the addition. Class D power amplifier comprising: a second low-pass filter for smoothing an output of a quantizer; and a selection circuit for selecting a reference level of the quantizer based on an amplitude of the input signal and an output of the second low-pass filter. . 3. A ΔΣ modulator having a quantizer for converting an input signal into a binary signal, a power switch for amplifying an output of the ΔΣ modulator, and a first low-pass for smoothing an output of the power switch A filter, a delay for delaying an output of the ΔΣ modulator, an attenuator for attenuating an output amplitude of the power switch capable of varying an amount of attenuation by an external control signal, and an output of the delay and an output of the attenuator. An adder for calculating a difference between the two, a second low-pass filter for smoothing the output of the adder, and a selection circuit for selecting a reference level of the quantizer based on the output of the second low-pass filter. Class D power amplifier.