JP2009176907A - Wiring substrate and its manufacturing method - Google Patents

Wiring substrate and its manufacturing method Download PDF

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JP2009176907A
JP2009176907A JP2008013283A JP2008013283A JP2009176907A JP 2009176907 A JP2009176907 A JP 2009176907A JP 2008013283 A JP2008013283 A JP 2008013283A JP 2008013283 A JP2008013283 A JP 2008013283A JP 2009176907 A JP2009176907 A JP 2009176907A
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hole
conductor
ceramic
layer
wiring board
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JP5166890B2 (en
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Muneyuki Iwata
宗之 岩田
Satoshi Hirano
聡 平野
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring substrate that allows planarization of the surface/rear-face of a ceramic layer of the outermost layer, where the end face of a via conductor is exposed, even if the via conductor continuously penetrates through a plurality of ceramic layers while allowing highly-accurate mounting or the like of each electronic component on the surface/rear-face, and its manufacturing method. <P>SOLUTION: The wiring substrate 1a includes a substrate body 2, which includes the surface 3 and the rear face 4 and is formed by laminating a plurality of ceramic layers S1-S4 including ceramic layers respectively formed with a through-hole h, a via hole 10, which is opened in the surface 3 of the substrate body 2 and in which a plurality of the through-holes h are continuous along in the thickness direction of the substrate body 2, a via conductor V, which is filled in the through-hole, being one of the plurality of through-holes h constituting the via hole 10, in the ceramic layer S1 of the outermost layer forming the surface 3 of the substrate body 2, and a through-hole conductor T that is formed along the inner-wall face of the through-hole, being one of the plurality of through-holes h forming the via hole 10, in the ceramic layer S2 other than the ceramic layer S1 of the outermost layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、積層した複数のセラミック層をビア導体が連続して貫通し、該ビア導体の端面が露出する最外層のセラミック層の表・裏面が平坦で電子部品などの実装が精度良く行える配線基板およびその製造方法に関する。   In the present invention, a via conductor continuously penetrates a plurality of laminated ceramic layers, and the front and back surfaces of the outermost ceramic layer where the end face of the via conductor is exposed are flat and wiring with which an electronic component or the like can be mounted with high accuracy is provided. The present invention relates to a substrate and a manufacturing method thereof.

複数のセラミック層とそれらの間ごとに配置した導体層とを積層してなる多層セラミック配線基板の製造過程において、上記セラミック層となるグリーンシートの搬送を容易にするため、その一面にキャリアシートを貼り付けた状態で、ビアホールとなる貫通孔が穿孔され、更に該貫通孔に導電性インクを充填する場合がある。上記グリーンシートを積層して多層セラミック配線基板を製造すると、上記キャリアシートの厚み相当分や、ビアホール内への導電性インクなどの過剰な充填に起因して、ビア導体が軸方向に延出し、最外層のセラミック層からその表面を外向きに突き上げてしまう場合がある。   In the manufacturing process of a multilayer ceramic wiring board formed by laminating a plurality of ceramic layers and conductor layers arranged between them, in order to facilitate the conveyance of the green sheet serving as the ceramic layer, a carrier sheet is provided on one surface thereof. In the pasted state, a through hole that becomes a via hole may be drilled, and the through hole may be filled with conductive ink. When a multilayer ceramic wiring board is manufactured by laminating the green sheets, the via conductor extends in the axial direction due to the thickness equivalent to the carrier sheet or excessive filling of the conductive ink into the via hole, In some cases, the surface of the outermost ceramic layer is pushed outward.

例えば、セラミックからなる複数の絶縁層と、それらの間ごとに配置した導体層とを有し、これらの厚み方向に沿って貫通するビアホール内に形成したビア導体が、導電性インクなどの過剰な充填により軸方向に延びる突き上げを生じ、最外層の絶縁層とこれに隣接する絶縁層との間に形成された面導体が外向きの凸形状に変形する場合がある。かかる凸形部の影響を避けてコンデンサを基板内に内設するため、該凸形部の真上に位置し、且つ最外層の絶縁層の表面に配置された電極導体の内部に、導体不在部の抜き孔を形成した多層基板が提案されている(例えば、特許文献1参照)。上記面導体、最外層の絶縁層、および電極導体は、上記多層基板内においてコンデンサを構成している。
特開2005−347567号公報(第1〜13頁、図1)
For example, a via conductor formed in a via hole having a plurality of insulating layers made of ceramic and a conductor layer disposed between each of them and passing through in the thickness direction of the conductive layer is excessive. In some cases, the filling causes a push-up extending in the axial direction, and the surface conductor formed between the outermost insulating layer and the insulating layer adjacent to the outermost insulating layer is deformed into an outwardly convex shape. In order to avoid the influence of the convex portion and to place the capacitor in the substrate, there is no conductor inside the electrode conductor located immediately above the convex portion and disposed on the surface of the outermost insulating layer. There has been proposed a multilayer substrate in which a part of the hole is formed (for example, see Patent Document 1). The surface conductor, the outermost insulating layer, and the electrode conductor constitute a capacitor in the multilayer substrate.
JP-A-2005-347567 (pages 1 to 13, FIG. 1)

ところで、前記のように、複数のセラミック層をそれらの厚み方向に沿って貫通するビア導体による突き上げが生じると、最外層のセラミック層の表面が平坦にならないだけでなく、かかる表面に露出するビア導体の端面上に形成された外部接続用のパッドを介して、半導体チップなどの電子部品を実装するに際し、パッド自体も平坦にならない。その結果、かかる電子部品と上記パッドとの導通が不安定になり、引いては、実装した電子部品の動作が不十分になるなどのおそれがあった。
あるいは、上記突き上げを伴うビア導体が、最外層のセラミック層の裏面に露出すると、該ビア導体の端面上に形成されたパッドなどを介して、接続すべき導体ピンを所要の位置および姿勢でハンダ付けできなくなる場合もあった。
By the way, as described above, when a push-up by a via conductor penetrating a plurality of ceramic layers along their thickness direction occurs, not only the surface of the outermost ceramic layer does not become flat, but also a via exposed on the surface. When an electronic component such as a semiconductor chip is mounted via an external connection pad formed on the end face of the conductor, the pad itself does not become flat. As a result, the electrical connection between the electronic component and the pad becomes unstable, and the operation of the mounted electronic component may be insufficient.
Alternatively, when the via conductor accompanied by the push-up is exposed on the back surface of the outermost ceramic layer, the conductor pin to be connected is soldered at a required position and posture via a pad formed on the end surface of the via conductor. In some cases, it could not be attached.

本発明は、背景技術において説明した問題点を解決し、複数のセラミック層をビア導体が軸方向に連続して貫通しても、該ビア導体の端面が露出する最外層のセラミック層の表・裏面を平坦にでき、かかる表・裏面上に電子部品などを精度良く実装などできる配線基板およびその製造方法を提供する、ことを課題とする。   The present invention solves the problems described in the background art, and even if the via conductor continuously penetrates the plurality of ceramic layers in the axial direction, the end surface of the via conductor is exposed. It is an object of the present invention to provide a wiring board capable of flattening the back surface and mounting electronic components and the like on the front and back surfaces with high accuracy and a method for manufacturing the same.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

本発明は、前記課題を解決するため、複数のセラミック層を厚み方向に沿って貫通する複数の貫通孔からなるビアホール内にビア導体を形成するに際し、最外層となるセラミック層を除いた一部のセラミック層の貫通孔の中心部に、空間を備えたスルーホール導体を形成する、ことに着想して成されたものである。
即ち、本発明の配線基板(請求項1)は、貫通孔が形成されたセラミック層を含む複数のセラミック層を積層してなり、且つ表面および裏面を有する基板本体と、かかる基板本体の表面または裏面の少なくとも一方に開口し、且つ該基板本体の厚み方向に沿って複数の上記貫通孔が連続したビアホールと、かかるビアホールを構成する複数の貫通孔のうち、上記基板本体の表面および裏面を形成する最外層のセラミック層の少なくとも一方の貫通孔に充填されたビア導体と、上記ビアホールを形成する複数の貫通孔のうち、上記最外層のセラミック層以外のセラミック層の貫通孔の内壁面に沿って形成されたスルーホール導体と、を備える、ことを特徴とする。
In order to solve the above-mentioned problem, the present invention provides a part excluding the ceramic layer which is the outermost layer when forming a via conductor in a via hole including a plurality of through holes penetrating a plurality of ceramic layers along the thickness direction. The idea is to form a through-hole conductor having a space at the center of the through hole of the ceramic layer.
That is, the wiring board of the present invention (Claim 1) is formed by laminating a plurality of ceramic layers including a ceramic layer in which a through hole is formed, and has a substrate body having a front surface and a back surface, and a surface of the substrate body or A via hole that opens in at least one of the back surfaces and has a plurality of through holes continuous along the thickness direction of the substrate body, and of the plurality of through holes that form the via holes, forms the front and back surfaces of the substrate body. A via conductor filled in at least one through-hole of the outermost ceramic layer and a plurality of through-holes forming the via hole along an inner wall surface of the through-hole of the ceramic layer other than the outermost ceramic layer And a through-hole conductor formed.

これによれば、複数のセラミック層ごとに形成された貫通孔が連続するビアホール内において、最外層を除いた何れかのセラミック層の貫通孔にスルーホール導体が形成されているので、かかるスルーホール導体が、製造時の複数のグリーンシートの積層・圧着工程において、隣接するビア導体の前記突き上げによる膨張を予め吸収をしている。このため、最外層のセラミック層の表面および裏面の少なくとも一方に露出するビア導体の端面が、かかる表・裏面と面一ないしほぼ面一となる。従って、基板本体の表面や裏面に露出する上記ビア導体の端面や、該ビア導体と接続して上記表面や裏面に形成されるパッドなどを介して、電子部品を精度良く実装したり、外部接続用の導体ピンを所定の位置および姿勢にしてハンダ付けなどにて固着することができる。   According to this, since the through hole conductor is formed in the through hole of any ceramic layer except the outermost layer in the via hole in which the through holes formed for each of the plurality of ceramic layers are continuous, the through hole The conductor absorbs in advance the expansion of the adjacent via conductor due to the push-up in the step of laminating and crimping a plurality of green sheets at the time of manufacture. For this reason, the end surface of the via conductor exposed on at least one of the front surface and the back surface of the outermost ceramic layer is flush with or substantially flush with the front and back surfaces. Therefore, it is possible to mount electronic components with high precision through the end face of the via conductor exposed on the front and back surfaces of the substrate body and the pads formed on the front and back surfaces by connecting to the via conductor and external connection. The conductor pins for use can be fixed in a predetermined position and posture by soldering or the like.

尚、前記セラミック層のセラミックには、アルミナなどの高温焼成セラミック、あるいは、ガラス成分を約50wt%程度含む低温焼成セラミックが含まれる。
また、前記ビア導体やスルーホール導体を含む導体には、前記セラミック層のセラミックが高温焼成セラミックからなる場合には、WやMoなどが用いられ、低温焼成セラミックの場合には、AgやCuなどが用いられる。
更に、前記ビアホールは、基板本体の表面側または裏面側のセラミック層の貫通孔から、中層のセラミック層の貫通孔まで連続する形態のほか、基板本体の表面と裏面との間の全てのセラミック層の貫通孔が連続した形態としても良い。
また、貫通孔にスルーホール導体が形成されるセラミック層は、最外層のセラミック層を除いたセラミック層のうちの何れかである。例えば、貫通孔にビア導体が充填された最外層のセラミック層の内側に隣接するセラミック層や、かかるセラミック層よりも更に内側に位置するセラミック層でも良い。かかるスルーホール導体の軸方向における両端面の少なくとも一方には、前記ビア導体が接続され、他方には該ビア導体または基板内部の配線層が接続される。
更に、前記スルーホール導体は、後述する製造工程で、かかるスルーホール導体が形成されたセラミック層を含む複数のセラミック層を積層・圧着する際の圧力によって、中心部に当初位置していたほぼ円柱形の空間が、ほぼ鼓形などの異形を呈するものとなっていても良い。
加えて、前記スルーホール導体は、貫通孔の内壁面に沿った外周部を有し、かかる外周部付近の表層を主に電流が流れるため、ビア導体に比べても、電気抵抗を殆んど増加させない。
The ceramic of the ceramic layer includes a high-temperature fired ceramic such as alumina, or a low-temperature fired ceramic containing about 50 wt% of a glass component.
For the conductor including the via conductor and the through-hole conductor, W or Mo is used when the ceramic of the ceramic layer is made of high-temperature fired ceramic, and Ag or Cu is used when the ceramic is low-temperature fired ceramic. Is used.
Further, the via hole has a continuous form from the through hole of the ceramic layer on the front surface side or the back surface side of the substrate body to the through hole of the ceramic layer of the middle layer, and all the ceramic layers between the front surface and the back surface of the substrate body. The through holes may be continuous.
Further, the ceramic layer in which the through-hole conductor is formed in the through hole is any one of the ceramic layers excluding the outermost ceramic layer. For example, a ceramic layer adjacent to the inside of the outermost ceramic layer in which the via conductor is filled in the through hole, or a ceramic layer positioned further inside than the ceramic layer may be used. The via conductor is connected to at least one of both end faces in the axial direction of the through-hole conductor, and the via conductor or a wiring layer inside the substrate is connected to the other.
Further, the through-hole conductor is substantially a cylinder that was originally located in the center due to the pressure when laminating and crimping a plurality of ceramic layers including the ceramic layer in which the through-hole conductor is formed in the manufacturing process described later. The space of the shape may have an irregular shape such as a drum shape.
In addition, the through-hole conductor has an outer peripheral portion along the inner wall surface of the through-hole, and a current mainly flows through the surface layer near the outer peripheral portion. Therefore, the electric resistance is almost smaller than that of the via conductor. Do not increase.

また、本発明には、前記スルーホール導体は、焼成後の厚みが100μm以上の前記セラミック層を貫通する貫通孔の内壁面に沿って形成されている、配線基板(請求項2)も含まれる。
これによれば、焼成後の厚みが100μm以上となる比較的厚いセラミック層を貫通する貫通孔の内壁面に沿って、スルーホール導体を形成しているので、製造時に前記貫通孔における一方の開口部を負圧とした状態で、他方の開口部から導電性インクなどを吸引させつつ容易に塗布・形成することができる。しかも、比較的厚いセラミック層の貫通孔には、導電性インクなどを吸引・塗布して、スルーホール導体を形成できるため、かかる製造工程も容易となる。
更に、本発明には、前記スルーホール導体の軸方向における少なくとも一方の開口部に、前記ビア導体の一部が進入している、配線基板(請求項3)も含まれる。
これによれば、スルーホール導体の軸方向における一方または双方の開口部に、隣接するビア導体の一部が進入しているため、該スルーホール導体とビア導体との電気的接続を安定させることが可能となる。
The present invention also includes a wiring board (Claim 2) in which the through-hole conductor is formed along an inner wall surface of a through hole that penetrates the ceramic layer having a thickness of 100 μm or more after firing. .
According to this, since the through-hole conductor is formed along the inner wall surface of the through-hole penetrating the relatively thick ceramic layer having a thickness of 100 μm or more after firing, one opening in the through-hole at the time of manufacturing is formed. It can be easily applied and formed while a conductive ink or the like is sucked from the other opening in a state where the portion is at a negative pressure. Moreover, since the through-hole conductor can be formed by sucking and applying conductive ink or the like in the through-hole of the relatively thick ceramic layer, such a manufacturing process is facilitated.
Furthermore, the present invention includes a wiring board (Claim 3) in which a part of the via conductor enters at least one opening in the axial direction of the through-hole conductor.
According to this, since a part of the adjacent via conductor enters one or both openings in the axial direction of the through-hole conductor, the electrical connection between the through-hole conductor and the via conductor can be stabilized. Is possible.

一方、本発明による配線基板の製造方法(請求項4)は、焼成後の厚みが100μm以上または100μm未満となる複数のグリーンシートに貫通孔を形成する工程と、上記グリーンシートのうち、少なくとも積層工程で最外層となるグリーンシートに形成した上記貫通孔に導電性ペーストを充填してビア導体を形成する工程と、上記最外層となるグリーンシート以外のグリーンシートに形成した上記貫通孔の内壁面に沿って、導電性ペーストを円環状に配設してスルーホール導体を形成する工程と、少なくとも上記ビア導体およびスルーホール導体が形成された複数のグリーンシートを、該ビア導体とスルーホール導体とが軸方向に沿って連続するように積層する工程と、を含む、ことを特徴とする。   On the other hand, the method for manufacturing a wiring board according to the present invention (Claim 4) includes a step of forming through holes in a plurality of green sheets having a thickness after firing of 100 μm or more or less than 100 μm, and at least a lamination of the green sheets. A step of filling the through hole formed in the outermost green sheet in the process with a conductive paste to form a via conductor, and an inner wall surface of the through hole formed in the green sheet other than the outermost green sheet And forming a through-hole conductor by disposing a conductive paste in an annular shape, and a plurality of green sheets on which at least the via conductor and the through-hole conductor are formed, the via conductor and the through-hole conductor And laminating so as to be continuous along the axial direction.

これによれば、積層工程で最外層となるグリーンシートの貫通孔にビア導体を形成し、最外層以外のグリーンシートの何れかのグリーンシートの貫通孔にスルーホール導体に形成し、これらの貫通孔が連続するビアホールを形成するように、複数の上記グリーンシートを積層・圧着している。その結果、基板本体を構成する複数のセラミック層の厚み方向に沿って貫通するビアホール内に、最外層のセラミック層を除いたセラミック層の何れかの貫通孔にスルーホール導体が、これ以外のセラミック層の貫通孔にビア導体が、互いにほぼ同軸で形成される。従って、かかるビア導体およびスルーホール導体の電気的接続が十分可能であり、基板本体の表面および裏面の少なくとも一方に露出するビア導体の端面が、前記表面や裏面とほぼ面一の平坦である配線基板を確実に製造することができる。
尚、焼成後の厚みが100μm以上あるいは100μm未満の前記グリーンシートは、これらを相対的な厚みで区切ったものである。
また、複数のグリーンシートごとに形成する前記貫通孔は、積層工程で同心となれば、互いの内径が異なるものを含んでいても良い。
更に、最外層以外のグリーンシートの何れかには、その貫通孔にビア導体が形成されるものも含まれる。
加えて、前記スルーホール導体には、中心部に当初位置していたほぼ円柱形の空間が、ほぼ鼓形などの異形を呈する形態のほか、かかる空間が極く小さな隙間に縮小している形態も含む。
According to this, a via conductor is formed in the through hole of the green sheet which is the outermost layer in the lamination process, and a through hole conductor is formed in the through hole of any green sheet of the green sheet other than the outermost layer. A plurality of the green sheets are laminated and pressure-bonded so as to form a via hole having continuous holes. As a result, a through-hole conductor is inserted into any through-hole of the ceramic layer except the outermost ceramic layer in the via hole penetrating along the thickness direction of the plurality of ceramic layers constituting the substrate body, and the other ceramics. Via conductors are formed substantially coaxial with each other in the through-holes of the layers. Accordingly, the via conductor and the through-hole conductor can be sufficiently electrically connected, and the end surface of the via conductor exposed on at least one of the front and back surfaces of the substrate body is substantially flush with the front and back surfaces. The substrate can be reliably manufactured.
In addition, the said green sheet whose thickness after baking is 100 micrometers or more or less than 100 micrometers is what divided | segmented these by relative thickness.
In addition, the through holes formed for each of the plurality of green sheets may include those having different inner diameters as long as they are concentric in the stacking step.
Further, any of the green sheets other than the outermost layer includes one in which a via conductor is formed in the through hole.
In addition, in the through-hole conductor, the substantially cylindrical space originally located in the center portion has an irregular shape such as a drum shape, and the space is reduced to a very small gap. Including.

また、本発明には、前記スルーホール導体が形成されるグリーンシートの焼成後の厚みは、100μm以上である、配線基板の製造方法(請求項5)も含まれる。
これによれば、焼成後のセラミック層の厚みが100μm以上の比較的厚いグリーンシートを貫通する貫通孔の内壁面に沿って、かかる貫通孔における一方の開口部を負圧とした状態で、他方の開口部から導電性インクなどを吸引しつつ塗布・形成することで、スルーホール導体を容易に形成できる。しかも、比較的厚いグリーンシートの貫通孔には、導電性インクなどを吸引・塗布して、スルーホール導体を形成できるため、かかる製造工程も容易となる。
The present invention also includes a method for manufacturing a wiring board (Claim 5), wherein the green sheet on which the through-hole conductor is formed has a thickness after firing of 100 μm or more.
According to this, along the inner wall surface of the through hole that penetrates a relatively thick green sheet having a thickness of 100 μm or more after firing, the other opening in the through hole has a negative pressure. A through-hole conductor can be easily formed by applying and forming conductive ink or the like from the opening of the substrate. Moreover, since the through-hole conductor can be formed by sucking and applying conductive ink or the like in the through-hole of the relatively thick green sheet, such a manufacturing process is facilitated.

更に、本発明には、一面に添着したキャリアシートを含んで前記貫通孔が貫通する前記グリーンシートは、前記導電性ペーストを充填してビア導体が形成された後、上記キャリアシートが剥離される、配線基板の製造方法(請求項6)も含まれる。
これによれば、グリーンシートの一面に添着したキャリアシートを含んで、貫通孔が形成され、かかる貫通孔にビア導体を形成した後、上記キャリアシートを剥離するので、該キャリアシートの厚み相当分だけビア導体の一部が、当該グリーンシートの一面に突出する。このため、次述するように、該ビア導体の凸部を、隣接するスルーホール導体の軸方向における一方の開口部に押し付けつつ、複数のセラミック層を積層することで、スルーホール導体における一方の開口部にビア導体の一部が進入した状態で、両導体を確実に接続することが可能となる。
尚、前記複数のグリーンシートのうち何れかには、その一面にキャリアシートが付着され、該キャリアシートにも前記貫通孔が同軸で形成される。
また、前記キャリアシートには、ポリエチレンテレフタレート(以下、PETと称する)などの樹脂フィルムが用いられる。
更に、前記キャリアシートは、少なくとも100μm未満のグリーンシートの一面に添着させることが望ましい。
Further, according to the present invention, the green sheet including the carrier sheet attached to one surface and through which the through hole penetrates is filled with the conductive paste to form a via conductor, and then the carrier sheet is peeled off. Also included is a method for manufacturing a wiring board (claim 6).
According to this, since the through hole is formed including the carrier sheet attached to one surface of the green sheet, and the via conductor is formed in the through hole, the carrier sheet is peeled off. Only a part of the via conductor protrudes on one surface of the green sheet. For this reason, as will be described below, by laminating a plurality of ceramic layers while pressing the convex portion of the via conductor against one opening in the axial direction of the adjacent through-hole conductor, Both conductors can be reliably connected in a state where a part of the via conductor enters the opening.
In addition, a carrier sheet is attached to one surface of any of the plurality of green sheets, and the through holes are formed coaxially in the carrier sheet.
Further, a resin film such as polyethylene terephthalate (hereinafter referred to as PET) is used for the carrier sheet.
Furthermore, it is desirable that the carrier sheet is attached to one side of a green sheet having a size of at least less than 100 μm.

加えて、本発明には、前記キャリアシートが剥離された前記グリーンシートは、その一面側に突出する上記ビア導体の凸部を、前記積層工程において、該グリーンシートに隣接して積層され且つ前記スルーホール導体が形成されたグリーンシートの該スルーホール導体の軸方向における一方の開口部に進入するようにして積層される、配線基板の製造方法(請求項7)も含まれる。
これによれば、ビア導体の凸部を、隣接するスルーホール導体の軸方向における一方の開口部に向かって押し込むように、複数のセラミック層を積層することで、スルーホール導体における一方の開口部にビア導体の一部が進入している状態で、両導体を物理的および電気的に確実に接続することが可能となる。
In addition, according to the present invention, the green sheet from which the carrier sheet has been peeled is formed by laminating the protruding portion of the via conductor protruding on one side of the green sheet adjacent to the green sheet in the stacking step, and A method for manufacturing a wiring board is also included in which the green sheet on which the through-hole conductor is formed is laminated so as to enter one opening in the axial direction of the through-hole conductor.
According to this, by laminating a plurality of ceramic layers so as to push the convex portion of the via conductor toward one opening in the axial direction of the adjacent through-hole conductor, one opening in the through-hole conductor In a state in which a part of the via conductor has entered, both conductors can be securely and physically connected.

以下において、本発明を実施するための最良の形態について説明する。
図1は、本発明による一形態の配線基板1aの要部を示す断面図である。
配線基板1aは、図1に示すように、複数のセラミック層S1〜S4からなり、表面3および裏面4を有する基板本体2と、セラミック層S1〜S3ごとの同じ位置に形成された貫通孔hが基板本体2の厚み方向に沿って連続し、一端が表面3に開口するビアホール10と、該ビアホール10を形成する複数の貫通孔hのうち、最上層(最外層)のセラミックS1および中層のセラミックS3の貫通孔hに充填されたビア導体Vと、これらに挟まれた中層のセラミックS2の貫通孔hの内壁面に沿って形成されたスルーホール導体Tと、を備えている。
前記セラミック層S1〜S4は、例えば、アルミナを主成分とし、最外層のセラミックS1,S4および中層のセラミックS3は、厚みが約50μm(100μm未満)と比較的薄く、中層のセラミックS2は、厚みが約110μm(100μm以上)と比較的厚い。
In the following, the best mode for carrying out the present invention will be described.
FIG. 1 is a cross-sectional view showing a main part of a wiring board 1a according to an embodiment of the present invention.
As shown in FIG. 1, the wiring board 1 a includes a plurality of ceramic layers S1 to S4, a substrate body 2 having a front surface 3 and a back surface 4, and through holes h formed at the same position for each of the ceramic layers S1 to S3. Are continuous along the thickness direction of the substrate body 2, and one end of the via hole 10 that opens to the surface 3, and among the plurality of through holes h forming the via hole 10, the uppermost layer (outermost layer) ceramic S 1 and the middle layer A via conductor V filled in the through-hole h of the ceramic S3 and a through-hole conductor T formed along the inner wall surface of the through-hole h of the middle-layer ceramic S2 sandwiched therebetween.
The ceramic layers S1 to S4 are mainly composed of alumina, for example, and the outermost ceramics S1 and S4 and the middle ceramic S3 are relatively thin with a thickness of about 50 μm (less than 100 μm), and the middle ceramic S2 is thick. Is relatively thick at about 110 μm (100 μm or more).

図1に示すように、スルーホール導体Tは、貫通孔hの内壁面に沿ったほぼ円筒形の胴部12と、その軸方向の両端に位置し且つほぼ半球形状の曲面部13と、これらに囲まれ且つほぼ鼓形を呈する空間sと、を有している。
また、セラミック層S1〜S4間には、所定パターンの配線層5,6,7が形成され、基板本体2の表面3には、最上層のセラミック層S1の貫通孔h内に位置するビア導体Vと接続するパッド8が形成されている。かかるパッド8には、表面3の上方に実装される半導体チップなどの電子部品がハンダ(何れも図示せず)を介して接続される。上記配線層5,6と、ビア導体Vあるいはスルーホール導体Tとの間には、前者に設けた円環状の透孔11が位置している。
As shown in FIG. 1, the through-hole conductor T includes a substantially cylindrical body portion 12 along the inner wall surface of the through-hole h, a substantially hemispherical curved surface portion 13 positioned at both ends in the axial direction, And a space s that is substantially in the shape of a drum.
Further, wiring layers 5, 6, and 7 having a predetermined pattern are formed between the ceramic layers S1 to S4, and a via conductor located in the through hole h of the uppermost ceramic layer S1 is formed on the surface 3 of the substrate body 2. A pad 8 connected to V is formed. An electronic component such as a semiconductor chip mounted above the surface 3 is connected to the pad 8 via solder (none of which is shown). Between the wiring layers 5 and 6 and the via conductor V or the through-hole conductor T, an annular through hole 11 provided in the former is located.

更に、図1に示すように、最下層(最外層)のセラミックS4には、平面視で前記ビアホール10とは異なる位置に貫通孔hおよびビア導体Vが形成され、かかるビア導体Vと接続するパッド9が基板本体2の裏面4に形成されている。該パッド9には、図示しないハンダを介して導体ピンPの頭部14が、裏面4と軸方向を直交させた姿勢で接合される。前記配線層7は、ビアホール10で最下層のビア導体Vと、セラミック層S4を貫通するビア導体Vとの間を接続している。
尚、前記ビア導体V、スルーホール導体T、配線層5〜7、およびパッド8,9は、WまたはMoなどからなり、前記導体ピンPは、例えば、Fe−42wt%Ni(42アロイ)またはCu−Fe−P合金(194合金)などからなる。
Further, as shown in FIG. 1, a through hole h and a via conductor V are formed in a position different from the via hole 10 in a plan view in the lowermost layer (outermost layer) ceramic S4 and connected to the via conductor V. Pads 9 are formed on the back surface 4 of the substrate body 2. The head 14 of the conductor pin P is joined to the pad 9 in a posture in which the axial direction is orthogonal to the back surface 4 via solder (not shown). The wiring layer 7 connects the lowermost via conductor V via the via hole 10 and the via conductor V penetrating the ceramic layer S4.
The via conductor V, the through-hole conductor T, the wiring layers 5 to 7 and the pads 8 and 9 are made of W or Mo, and the conductor pin P is made of, for example, Fe-42 wt% Ni (42 alloy) or It consists of Cu-Fe-P alloy (194 alloy) etc.

図2は、異なる形態の配線基板1bの要部を示す断面図である。
配線基板1bは、図2に示すように、複数のセラミック層S1〜S4からなる前記同様の基板本体2、前記同様のビアホール10と、該ビアホール10を形成する複数の貫通孔hのうち、最上層(最外層)のセラミックS1および中層のセラミックS2の貫通孔hに充填されたビア導体Vと、中層のセラミックS3の貫通孔hの内壁面に沿って形成されたスルーホール導体Tと、を備えている。
前記セラミック層S1〜S4は、前記同様のセラミックからなり、最外層のセラミックS1,S4および中層のセラミックS2の厚みは、約60μm(100μm未満)、中層のセラミックS2の厚みは、約120μm(100μm以上)である。
FIG. 2 is a cross-sectional view showing a main part of a wiring board 1b having a different form.
As shown in FIG. 2, the wiring substrate 1 b includes the same substrate body 2 composed of a plurality of ceramic layers S 1 to S 4, the same via hole 10, and the plurality of through holes h forming the via hole 10. Via conductor V filled in through hole h of upper layer (outermost layer) ceramic S1 and middle layer ceramic S2, and through hole conductor T formed along the inner wall surface of through hole h of middle layer ceramic S3, I have.
The ceramic layers S1 to S4 are made of the same ceramic as described above, and the outermost layer ceramics S1 and S4 and the middle layer ceramic S2 have a thickness of about 60 μm (less than 100 μm), and the middle layer ceramic S2 has a thickness of about 120 μm (100 μm). Above).

図2に示すように、スルーホール導体Tは、貫通孔hの内壁面に沿ったほぼ円筒形の胴部12と、その軸方向の上端に位置し且つほぼ半球形状の曲面部13と、これらおよび胴部12の下端に接続する配線層7に囲まれ且つほぼ鼓形を呈する空間sと、を有している。
また、セラミック層S1〜S4間には、前記同様の配線層5,6,7が形成され、基板本体2の表面3には、前記同様のパッド8が形成されている。上記配線層5,6とビア導体Vまたはスルーホール導体Tとの間には、前記同様の透孔11が位置している。
更に、図2に示すように、最下層のセラミックS4には、前記同様の貫通孔hおよびビア導体Vが形成され、該ビア導体Vと接続するパッド9が基板本体2の裏面4に形成されている。前記配線層7は、ビアホール10で最下層のスルーホール導体Tと、セラミック層s4を貫通するビア導体Vとの間を接続している。
As shown in FIG. 2, the through-hole conductor T includes a substantially cylindrical body portion 12 along the inner wall surface of the through hole h, a curved surface portion 13 that is located at the upper end in the axial direction and has a substantially hemispherical shape, And a space s surrounded by the wiring layer 7 connected to the lower end of the body portion 12 and having a substantially drum shape.
Further, the same wiring layers 5, 6, and 7 are formed between the ceramic layers S1 to S4, and the same pad 8 is formed on the surface 3 of the substrate body 2. Between the wiring layers 5 and 6 and the via conductor V or the through-hole conductor T, the same through hole 11 is located.
Further, as shown in FIG. 2, the lowermost ceramic S4 is provided with the same through hole h and via conductor V, and a pad 9 connected to the via conductor V is formed on the back surface 4 of the substrate body 2. ing. The wiring layer 7 connects the lowermost through-hole conductor T in the via hole 10 and the via conductor V penetrating the ceramic layer s4.

図3は、更に異なる形態の配線基板1cの要部を示す断面図である。
配線基板1cは、図3に示すように、複数のセラミック層S1〜S4からなる前記同様の基板本体2、セラミック層S1に形成した大径の貫通孔hと、セラミック層S2〜S4の同じ位置に形成された小径の貫通孔hとが基板本体2の厚み方向に沿って同心で連続し、両端が表面3および裏面4に開口するビアホール10と、該ビアホール10を形成する複数の貫通孔hのうち、最外層のセラミックS1,S4および中層のセラミックS2の貫通孔hに充填されたビア導体Vと、残る中層のセラミックS3の貫通孔hの内壁面に沿って形成された比較的短軸のスルーホール導体Tと、を備えている。
前記セラミック層S1〜S4は、前記同様のセラミックからなり、最外層のセラミックS1,S4および中層のセラミックS3の厚みは、約80μm(100μm未満)、中層のセラミックS2の厚みは、約150μm(100μm以上)である。
FIG. 3 is a cross-sectional view showing the main part of a further different form of the wiring board 1c.
As shown in FIG. 3, the wiring board 1c has the same substrate body 2 composed of a plurality of ceramic layers S1 to S4, a large-diameter through hole h formed in the ceramic layer S1, and the same positions of the ceramic layers S2 to S4. And a plurality of through-holes h forming the via holes 10, which are concentrically continuous with each other along the thickness direction of the substrate body 2, have both ends opened to the front surface 3 and the back surface 4. Among them, the via conductor V filled in the through holes h of the outermost layer ceramics S1 and S4 and the middle layer ceramic S2, and the relatively short axis formed along the inner wall surface of the remaining through holes h of the middle layer ceramic S3. Through-hole conductor T.
The ceramic layers S1 to S4 are made of the same ceramic as described above, and the outermost layer ceramics S1 and S4 and the middle layer ceramic S3 have a thickness of about 80 μm (less than 100 μm), and the middle layer ceramic S2 has a thickness of about 150 μm (100 μm). Above).

図3に示すように、スルーホール導体Tは、貫通孔hの内壁面に沿ったほぼ円筒形で短い胴部12と、その軸方向の両端に位置し且つほぼ半球形状の曲面部13と、これらに囲まれ且つほぼ鼓形を呈する比較的小さな空間sと、を有している。
また、セラミック層S1〜S4間には、前記同様の配線層5,6,7が形成され、基板本体2の表面3には、前記大径のビア導体Vの上端面が露出し、該ビア導体Vの上端面に電子部品が直に実装される。上記配線層5,6,7とビア導体Vまたはスルーホール導体Tとの間には、前記同様の透孔11が位置している。
更に、図3に示すように、基板本体2の裏面4には、最下層のセラミックS4に形成されたビア導体Vと接続する前記同様のパッド9が形成されている。
As shown in FIG. 3, the through-hole conductor T includes a substantially cylindrical short body portion 12 along the inner wall surface of the through hole h, a substantially hemispherical curved surface portion 13 positioned at both ends in the axial direction, A relatively small space s surrounded by these and having a substantially hourglass shape.
Further, the same wiring layers 5, 6, and 7 are formed between the ceramic layers S1 to S4, and the upper end surface of the large-diameter via conductor V is exposed on the surface 3 of the substrate body 2, and the via An electronic component is mounted directly on the upper end surface of the conductor V. Between the wiring layers 5, 6 and 7 and the via conductor V or the through-hole conductor T, the same through hole 11 is located.
Further, as shown in FIG. 3, the same pad 9 as that connected to the via conductor V formed in the lowermost ceramic S <b> 4 is formed on the back surface 4 of the substrate body 2.

図4は、前記配線基板1aの応用形態である配線基板1dの要部を示す断面図である。
配線基板1dは、図4に示すように、複数のセラミック層S1〜S4からなる前記同様の基板本体2、セラミック層S2〜S4ごとの同じ位置に形成された貫通孔hが基板本体2の厚み方向に沿って連続し、一端が裏面4に開口するビアホール10と、該ビアホール10を形成する複数の貫通孔hのうち、最下層(最外層)のセラミックS4および中層のセラミックS2の貫通孔hに充填されたビア導体Vと、これらに挟まれた中層のセラミックS3の貫通孔hの内壁面に沿って形成されたスルーホール導体Tと、を備えている。
前記セラミック層S1〜S4は、前記同様のセラミックからなり、最外層のセラミックS1,S4および中層のセラミックS2の厚みは、約70μm(100μm未満)、中層のセラミックS3の厚みは、約140μm(100μm以上)である。
FIG. 4 is a cross-sectional view showing a main part of a wiring board 1d which is an applied form of the wiring board 1a.
As shown in FIG. 4, the wiring board 1 d has a through hole h formed in the same position for each of the ceramic body S <b> 2 and the ceramic layers S <b> 2 to S <b> 4 having a plurality of ceramic layers S <b> 1 to S <b> 4. A via hole 10 that is continuous along the direction and has one end opened on the back surface 4, and among the plurality of through holes h that form the via hole 10, the lower layer (outermost layer) ceramic S4 and the middle layer ceramic S2 have a through hole h. And a through-hole conductor T formed along the inner wall surface of the through hole h of the middle-layer ceramic S3 sandwiched between them.
The ceramic layers S1 to S4 are made of the same ceramic as described above, and the outermost layer ceramics S1 and S4 and the middle layer ceramic S2 have a thickness of about 70 μm (less than 100 μm), and the middle layer ceramic S3 has a thickness of about 140 μm (100 μm). Above).

図4に示すように、スルーホール導体Tは、前記同様の長軸の胴部12、上下一対の曲面部13と、および空間sと、を有している。
また、セラミック層S1〜S4間には、前記同様の配線層5,6,7が形成され、基板本体2の表面3には、前記同様のパッド8が形成されている。上記配線層6,7とビア導体Vまたはスルーホール導体Tとの間には、前記同様の透孔11が位置している。
更に、図4に示すように、最上層のセラミックS1には、ビアホール10と異なる位置に貫通孔hおよびビア導体Vが形成され、該ビア導体Vと接続するパッド8が基板本体2の表面3に形成されている。前記配線層5は、ビアホール10で最上層のビア導体Vと、セラミック層S1を貫通するビア導体Vとの間を接続している。
As shown in FIG. 4, the through-hole conductor T has a long-axis body 12 similar to the above, a pair of upper and lower curved surfaces 13, and a space s.
Further, the same wiring layers 5, 6, and 7 are formed between the ceramic layers S1 to S4, and the same pad 8 is formed on the surface 3 of the substrate body 2. Between the wiring layers 6 and 7 and the via conductor V or the through-hole conductor T, the same through hole 11 is located.
Further, as shown in FIG. 4, a through hole h and a via conductor V are formed in a different position from the via hole 10 in the uppermost ceramic S <b> 1, and a pad 8 connected to the via conductor V is a surface 3 of the substrate body 2. Is formed. The wiring layer 5 connects the uppermost via conductor V in the via hole 10 and the via conductor V penetrating the ceramic layer S1.

以上のような配線基板1a〜1dによれば、前記セラミック層S1〜S4のうち、少なくとも一方の最外層を含むセラミック層S1,S4に形成された貫通孔hが連続するビアホール10内において、最外層を除いたセラミック層S2,S3の何れか一方の貫通孔hにスルーホール導体Tが形成されているので、該スルーホール導体Tが、製造時の複数のグリーンシートの積層・圧着工程にて、隣接するビア導体Vの前記突き上げによる膨張を予め吸収している。このため、最外層のセラミック層S1,S4の表面3および裏面4の少なくとも一方に露出するビア導体Vの端面が、かかる表・裏面3,4と面一ないしほぼ面一となる。従って、基板本体2の表面3や裏面4に露出する上記ビア導体Vの端面や、該ビア導体Vと接続して形成されるパッド8,9を介して、電子部品を精度良く実装したり、導体ピンPを所定の位置および姿勢にしてハンダ付けなどで接合可能となる。
更に、前記配線基板1a,1c,1dでは、それらのスルーホール導体Tが、その軸方向の両端の開口部に隣接する上層および下層のビア導体Vの一部進入して、上下一対の曲面部13が形成されているので、かかるスルーホール導体Tと隣接するビア導体Vとの電気的な接続を安定したものにできる。
しかも、配線基板1a,1b,1dでは、スルーホール導体Tが、厚みが100μm以上のセラミック層S2,S3の貫通孔hの内壁面に沿って形成されているため、製造時に導電性インクなどを容易に塗布して形成することができる。
According to the wiring boards 1a to 1d as described above, in the via hole 10 in which the through holes h formed in the ceramic layers S1 and S4 including at least one outermost layer among the ceramic layers S1 to S4 are continuous, Since the through-hole conductor T is formed in one of the through holes h of the ceramic layers S2 and S3 excluding the outer layer, the through-hole conductor T is formed in a process of laminating and pressing a plurality of green sheets at the time of manufacture. The expansion due to the push-up of the adjacent via conductor V is absorbed in advance. For this reason, the end face of the via conductor V exposed to at least one of the front surface 3 and the back surface 4 of the outermost ceramic layers S1 and S4 is flush with or substantially flush with the front and back surfaces 3 and 4. Therefore, the electronic component can be mounted with high accuracy through the end surface of the via conductor V exposed on the front surface 3 and the back surface 4 of the substrate body 2 and the pads 8 and 9 formed in connection with the via conductor V. The conductor pins P can be joined by soldering or the like with the predetermined positions and postures.
Furthermore, in the wiring boards 1a, 1c, and 1d, the through-hole conductors T partially enter the upper and lower via conductors V adjacent to the openings at both ends in the axial direction, and a pair of upper and lower curved surface portions. 13 is formed, the electrical connection between the through-hole conductor T and the adjacent via conductor V can be stabilized.
Moreover, in the wiring boards 1a, 1b, and 1d, the through-hole conductor T is formed along the inner wall surface of the through hole h of the ceramic layers S2 and S3 having a thickness of 100 μm or more. It can be easily applied and formed.

以下において、前記配線基板1aの製造方法について説明する。
予め、アルミナ粉末、所要の有機バインダ、および溶剤などを、所要量ずつ瓶量・混合してセラミックスラリを製作し、これをドクターブレード法によって、シート状を呈する複数のグリーンシートs1〜s4に成形した。このうち、グリーンシートs1,s3,s4は、焼成後の厚みが約50μm(100μm未満)となり、グリーンシートs2は、焼成後の厚みが約100μm(100μm以上)となるものである。比較的薄いグリーンシートs1,s3の一面には、厚みが約40μmのキャリアシートcsが全面に添着されている。尚、該キャリアシートcsは、例えば、PETからなるフィルムである。
次に、キャリアシートcsを含む上記グリーンシートs1〜s3の同じ位置ごとに、打ち抜き加工を施して、図5に示すように、複数の貫通孔hを同軸となるように穿孔した。一方、グリーンシートs4には、上記と異なる位置に貫通孔hを穿孔した。
Below, the manufacturing method of the said wiring board 1a is demonstrated.
A ceramic slurry is prepared by mixing and mixing required amounts of alumina powder, required organic binder, and solvent in advance, and this is formed into a plurality of green sheets s1 to s4 that have a sheet shape by the doctor blade method. did. Among these, the green sheets s1, s3, and s4 have a thickness after firing of about 50 μm (less than 100 μm), and the green sheet s2 has a thickness after firing of about 100 μm (100 μm or more). A carrier sheet cs having a thickness of about 40 μm is attached to one surface of the relatively thin green sheets s1 and s3. The carrier sheet cs is a film made of PET, for example.
Next, the green sheets s1 to s3 including the carrier sheet cs were punched at the same positions, and a plurality of through holes h were formed so as to be coaxial, as shown in FIG. On the other hand, a through hole h was drilled in the green sheet s4 at a position different from the above.

次いで、追って最外層となる前記グリーンシートs1,s4と中層となるグリーンシートs3との貫通孔hに、W粉末またはMo粉末を含む導電性ペースト(導電性インク)を、図示しないメタルマスクおよびスキージを用いて充填し、図6に示すように、ほぼ円柱形を呈する未焼成のビア導体vを形成した。
一方、追って中層となる比較的厚いグリーンシートs2の貫通孔hに対し、一方の開口部からエアを吸引して内部を負圧状態とし、他方の開口部から上記同様の導電性ペーストを吸引した。その結果、図6に示すように、該貫通孔hの内壁面に沿ってほぼ円筒形を呈し、中心部に通し孔uを有する未焼成のスルーホール導体tが形成された。
尚、上記ビア導体vやスルーホール導体tの端面が露出するグリーンシートs1〜s4の表・裏面には、図示しない前記導電性ペーストの一部が貫通孔hごとの周囲に、平面視が異形の環状を呈するように、薄膜状に張り出している。
Next, a conductive paste (conductive ink) containing W powder or Mo powder is applied to the through holes h of the green sheets s1, s4, which will be outermost layers, and the green sheet s3, which will be the middle layer, and a metal mask and squeegee (not shown). As shown in FIG. 6, an unfired via conductor v having a substantially cylindrical shape was formed.
On the other hand, air is sucked from one opening to make a negative pressure inside the through-hole h of the relatively thick green sheet s2, which will be an intermediate layer, and the same conductive paste is sucked from the other opening. . As a result, as shown in FIG. 6, an unfired through-hole conductor t having a substantially cylindrical shape along the inner wall surface of the through hole h and having a through hole u at the center was formed.
In addition, on the front and back surfaces of the green sheets s1 to s4 where the end surfaces of the via conductors v and the through-hole conductors t are exposed, a part of the conductive paste (not shown) is around each through hole h, and the plan view is irregular. It protrudes in the form of a thin film so as to exhibit an annular shape.

更に、前記グリーンシートs1,s2,s4の表面および裏面の少なくとも一方に、前記同様の導電性ペーストをスクリーン印刷にて所定パターンで形成した。
その結果、図7に示すように、最上層となるグリーンシートs1の表面には、ビア導体vと接続した未焼成のパッド8が形成され、中層となるグリーンシートs2の表面および裏面には、所定パターンの配線層5,6がスルーホール導体tと離れて形成された。更に、最下層となるグリーンシートs4の表面および裏面には、所定パターンの配線層7と未焼成のパッド9とが、該グリーンシートs4を貫通するビア導体vと接続して形成された。
次に、図8に示すように、前記グリーンシートs1,s3から、その一面に添着されていた前記キャリアシートcsを剥離した。その結果、グリーンシートs1,s3の裏面または表面には、これを貫通するビア導体vのうち、キャリアシートcsの厚み分にほぼ相当する高さの凸部pが個別に突出した。
Further, the same conductive paste as described above was formed in a predetermined pattern by screen printing on at least one of the front and back surfaces of the green sheets s1, s2, and s4.
As a result, as shown in FIG. 7, unfired pads 8 connected to the via conductors v are formed on the surface of the green sheet s1 as the uppermost layer, and on the front and back surfaces of the green sheet s2 as the middle layer, The wiring layers 5 and 6 having a predetermined pattern were formed apart from the through-hole conductor t. Further, a wiring layer 7 having a predetermined pattern and an unfired pad 9 were formed on the front and back surfaces of the green sheet s4 serving as the lowermost layer, connected to the via conductors v penetrating the green sheet s4.
Next, as shown in FIG. 8, the carrier sheet cs attached to one surface of the green sheets s1 and s3 was peeled off. As a result, protrusions p having a height substantially corresponding to the thickness of the carrier sheet cs out of the via conductors v penetrating the green sheets s1 and s3 individually protruded from the back surface or the front surface of the green sheets s1 and s3.

次いで、図8中の矢印で示すように、前記グリーンシートs1〜s4を、これらの厚み方向に沿って積層し、且つ圧着した。この際、グリーンシートs1〜s3ごとの貫通孔hがほぼ同軸で連続し、これらに形成されたビア導体vおよびスルーホール導体tが接続されるようにして積層した。
その結果、図9に示すように、グリーンシートs1〜s4が積層され、表面3および裏面4を有する未焼成の基板本体2が形成されると共に、グリーンシートs1〜s3ごとの貫通孔hが連続したビアホール10が形成された。
この際、比較的厚い中層のグリーンシートs2内の前記スルーホール導体tには、隣接して積層されたグリーンシートs1,s3の各ビア導体vの凸部(一部)pが、その軸方向における前記通し孔uの両端の開口部に押し込まれつつ進入していた。
Next, as indicated by the arrows in FIG. 8, the green sheets s1 to s4 were laminated along the thickness direction and pressure-bonded. At this time, the through holes h for each of the green sheets s1 to s3 were substantially coaxially continuous, and the via conductors v and the through-hole conductors t formed thereon were connected to be laminated.
As a result, as shown in FIG. 9, the green sheets s1 to s4 are laminated to form the unfired substrate body 2 having the front surface 3 and the back surface 4, and the through holes h for each of the green sheets s1 to s3 are continuous. The via hole 10 was formed.
At this time, the through-hole conductor t in the relatively thick middle-layer green sheet s2 is provided with convex portions (parts) p of the via conductors v of the green sheets s1 and s3 stacked adjacent to each other. It was approaching while being pushed into the openings at both ends of the through hole u.

その結果、前記スルーホール導体tは、図9に示すように、貫通孔hの内壁面に沿い且つ軸方向のほぼ中間部分が厚肉の円筒部12と、上記通し孔uの上下両端に上記凸部pが進入して形成された一対の曲面部13と、これらに囲まれ且つほぼ鼓形を呈する空間sとを有する未焼成のスルーホール導体Tとなった。
また、前記配線層5,6は、ビアホール10内のビア導体vやスルーホール導体tと透孔11を置いて、グリーンシートs1〜s3間に形成された。
更に、前記配線層7とグリーンシートs3,s4を貫通する各ビア導体vとが接続されると共に、これらとビアホール10内の前記スルーホール導体tやビア導体vとを介して、表面3側のパッド8と裏面4側のパッド9とが、相互に導通可能となった。
As a result, as shown in FIG. 9, the through-hole conductor t is formed along the inner wall surface of the through-hole h and the cylindrical portion 12 having a thick middle portion in the axial direction, and the upper and lower ends of the through-hole u. An unfired through-hole conductor T having a pair of curved surface portions 13 formed by the protrusions p and a space s surrounded by these and having a substantially drum shape was obtained.
The wiring layers 5 and 6 are formed between the green sheets s1 to s3 with the via conductors v and through-hole conductors t in the via holes 10 and the through holes 11 being placed.
Further, the wiring layer 7 and each via conductor v penetrating the green sheets s3 and s4 are connected, and the through-hole conductor t and the via conductor v in the via hole 10 are connected to the surface layer 3 side. The pad 8 and the pad 9 on the back surface 4 side can conduct each other.

尚、前記グリーンシートs1〜s4間ごとにおけるビアホール10と交差する位置の付近には、前記導電性ペーストの一部が平面視が異形の環状を呈するように、薄膜状に張り出していた。
そして、以上のような未焼成の基板本体2を、所定の温度帯で焼成した。その結果、前記図1に示した配線基板1aが得られた。
尚、前記製造方法において、前記グリーンシートs2とグリーンシートs3との位置を入れ替え、且つグリーンシートs1,s4と共に前記同様に積層・圧着し、更に焼成することで、前記配線基板1bを製造することができる。
また、前記製造方法において、前記グリーンシートs1〜s4の積層すべき位置を適宜入れ替えて、これらを積層・圧着し、更に焼成することで、前記配線基板1dを製造することができる。
In addition, in the vicinity of the position intersecting with the via hole 10 between the green sheets s1 to s4, a part of the conductive paste protrudes in a thin film shape so as to exhibit a ring shape having an irregular shape in plan view.
Then, the unfired substrate body 2 as described above was fired at a predetermined temperature zone. As a result, the wiring board 1a shown in FIG. 1 was obtained.
In the manufacturing method, the wiring board 1b is manufactured by switching the positions of the green sheet s2 and the green sheet s3, laminating and press-bonding the green sheets s1 and s4 in the same manner as described above, and further firing them. Can do.
Moreover, in the said manufacturing method, the said wiring board 1d can be manufactured by changing suitably the position which the said green sheets s1-s4 should laminate | stack, laminating | stacking and crimping | bonding these, and also baking.

次に、前記配線基板1cの製造方法の概略について説明する。
図10の左側に示すように、焼成後の厚みが150μmとなる前記同様のグリーンシートs2と、焼成後の厚みが80μmとなる前記同様のグリーンシートs3,s4とを用意した。グリーンシートs2,s4の裏面または表面には、前記同様のキャリアシートcsが全面に添着されている。かかるキャリアシートcsを含むグリーンシートs2〜s4の同じ位置に打ち抜き加工を施して、それぞれに貫通孔hを形成した。尚、図示しない最上層となるグリーンシートs1の同じ位置には、上記貫通孔hよりも大径の貫通孔hを形成した。
次いで、図10の右側に示すように、グリーンシートs2,s4と図示しないグリーンシートs1との貫通孔hごとに、前記同様の導電性ペーストを充填して、未焼成のビア導体vを形成した。一方、グリーンシートs3の貫通孔hには、前記同様の方法によって、その内壁面に沿い且つ中心部に通し孔uを有する短軸で未焼成のスルーホール導体tを形成した。
Next, an outline of a method for manufacturing the wiring board 1c will be described.
As shown on the left side of FIG. 10, the same green sheet s2 having a thickness after firing of 150 μm and the same green sheets s3 and s4 having a thickness of 80 μm after firing were prepared. The same carrier sheet cs as described above is attached to the entire back surface or front surface of the green sheets s2 and s4. The green sheets s2 to s4 including the carrier sheet cs were punched at the same positions to form through holes h in each. A through hole h having a diameter larger than that of the through hole h was formed at the same position of the green sheet s1 as the uppermost layer (not shown).
Next, as shown on the right side of FIG. 10, each of the through holes h of the green sheets s2 and s4 and the green sheet s1 (not shown) is filled with the same conductive paste as described above to form an unfired via conductor v. . On the other hand, in the through hole h of the green sheet s3, an unfired through-hole conductor t with a short axis having a through hole u along the inner wall surface and in the center portion was formed by the same method as described above.

更に、グリーンシートs2,s4から前記キャリアシートcsを剥離して、図11の左側に示すように、グリーンシートs2,s4の裏面または表面に、キャリアシートcsの厚み相当分の高さであるビア導体vの凸部pを突出させた。
次いで、グリーンシートs2〜s4の表面に、前記ビア導体vやスルーホール導体tと間隔を置いて、前記同様にして、配線層5〜7を印刷・形成した。
次に、グリーンシートs2〜s4と図示しないグリーンシートs1とを、それらの貫通孔hが連通するように、図11の左側の矢印に沿って積層・圧着した。
その結果、図11の右側に示すように、グリーンシートs2〜s4と図示しないグリーンシートs1との貫通孔hが同心で連続したビアホール10が形成されると共に、前記短軸のスルーホール導体tが、上下の各凸部pに軸方向から押されつつ変形して、ほぼ円筒形の胴部12、上下一対の曲面部13、およびこれらに囲まれ且つほぼ鼓形を呈する空間sを有する未焼成のスルーホール導体T、およびこれを含む未焼成の基板本体2が形成された。
そして、かかる基板本体2を前記同様に焼成した結果、前記図3に示した配線基板1cが得られた。以上の製造方法には、前記積層工程において、スルーホール導体tの空間sが消失して、ほぼビア導体vとなる形態も含まれる。
Further, the carrier sheet cs is peeled from the green sheets s2 and s4, and vias having a height corresponding to the thickness of the carrier sheet cs are formed on the back surface or front surface of the green sheets s2 and s4 as shown on the left side of FIG. The convex part p of the conductor v was protruded.
Next, wiring layers 5 to 7 were printed and formed on the surfaces of the green sheets s2 to s4 at intervals from the via conductors v and the through-hole conductors t.
Next, the green sheets s <b> 2 to s <b> 4 and the green sheet s <b> 1 (not shown) were laminated and pressure-bonded along the arrow on the left side of FIG. 11 so that the through holes h communicate with each other.
As a result, as shown on the right side of FIG. 11, via holes 10 in which through holes h of green sheets s2 to s4 and green sheet s1 (not shown) are concentric and continuous are formed, and the short-axis through-hole conductor t is The upper and lower convex portions p are deformed while being pushed from the axial direction, and have a substantially cylindrical body portion 12, a pair of upper and lower curved surface portions 13, and a space s surrounded by these and having a substantially drum shape. Through-hole conductors T and an unfired substrate body 2 including the conductors were formed.
As a result of firing the substrate body 2 in the same manner as described above, the wiring substrate 1c shown in FIG. 3 was obtained. The above manufacturing method includes a form in which the space s of the through-hole conductor t disappears and becomes a via conductor v in the laminating step.

図12は、前記配線基板1cの変形形態である配線基板1eの要部を示す断面図である。配線基板1eは、図12に示すように、前記同様の基板本体2、セラミック層S1に形成した大径の貫通孔hと、小径のセラミック層S2〜S4の同じ位置に形成された小径の貫通孔hとが、基板本体2の厚み方向に沿って同心で連続し、両端が表面3および裏面4に開口するビアホール10と、該ビアホール10を形成する複数の貫通孔hのうち、最外層のセラミックS1,S4および中層のセラミックS3の貫通孔hに充填されたビア導体Vと、残る中層のセラミックS2の貫通孔hの内壁面に沿って形成された比較的長軸のスルーホール導体Tと、を備えている。
図12に示すように、スルーホール導体Tは、前記同様の胴部12、上下一対の曲面部13、および空間sと、を有している。また、セラミック層S1〜S4間には、前記同様の配線層5,6,7が形成され、基板本体2の表面3には、前記大径のビア導体Vの端面が露出し、実装される電子部品との接続に使用される。更に、基板本板2の裏面4には、前記同様のパッド9が形成されている。
FIG. 12 is a cross-sectional view showing a main part of a wiring board 1e which is a modification of the wiring board 1c. As shown in FIG. 12, the wiring board 1e has a small-diameter penetration formed in the same position of the large-diameter through hole h formed in the substrate body 2 and the ceramic layer S1 and the small-diameter ceramic layers S2 to S4. The hole h is concentrically continuous along the thickness direction of the substrate body 2, and the outermost layer among the via hole 10 having both ends opened on the front surface 3 and the back surface 4 and the plurality of through holes h forming the via hole 10. Via conductors V filled in the through holes h of the ceramics S1 and S4 and the intermediate ceramic S3, and a relatively long-axis through hole conductor T formed along the inner wall surface of the through holes h of the remaining intermediate ceramic S2. It is equipped with.
As shown in FIG. 12, the through-hole conductor T has the same body portion 12, a pair of upper and lower curved surface portions 13, and a space s as described above. The same wiring layers 5, 6, and 7 are formed between the ceramic layers S1 to S4, and the end surface of the large-diameter via conductor V is exposed and mounted on the surface 3 of the substrate body 2. Used for connection to electronic components. Further, the same pad 9 as described above is formed on the back surface 4 of the substrate main plate 2.

図13は、前記配線基板1eの製造方法を示す。図示のように、最上層となるグリーンシートs1の貫通孔hには、前記同様の凸部pを有する大径のビア導体vを形成し、中層のグリーンシートs2の貫通孔hには、前記同様のスルーホール導体tを形成し、他の中層のグリーンシートs3の貫通孔hには、前記同様の凸部pを有するビア導体vを形成し、最下層となるグリーンシートs4の貫通孔hには、ビア導体vを形成した。また、グリーンシートs2〜s4の表面には、前記同様の配線層5〜7を印刷・形成すると共に、グリーンシートs4の裏面には、パッド9を形成した。
そして、図13中の矢印で示すように、グリーンシートs1〜s4を圧着・積層した際に、グリーンシートs1,s3の各凸部pが、グリーンシートs2のスルーホール導体tの通し孔uに進入して、前記スルーホール導体Tが形成され、これらを焼成することで、前記配線基板1eが得られた。
FIG. 13 shows a manufacturing method of the wiring board 1e. As shown in the drawing, a large-diameter via conductor v having the same convex portion p is formed in the through hole h of the green sheet s1 as the uppermost layer, and the through hole h of the green sheet s2 in the middle layer is formed in the through hole h. The same through-hole conductor t is formed, and the via conductor v having the same convex portion p is formed in the through hole h of the other middle-layer green sheet s3, and the through-hole h of the green sheet s4 serving as the lowermost layer is formed. A via conductor v was formed. In addition, the same wiring layers 5 to 7 were printed and formed on the front surfaces of the green sheets s2 to s4, and the pads 9 were formed on the back surface of the green sheets s4.
Then, as indicated by the arrows in FIG. 13, when the green sheets s1 to s4 are pressure-bonded and laminated, the convex portions p of the green sheets s1 and s3 are inserted into the through holes u of the through-hole conductors t of the green sheet s2. The through-hole conductor T was formed by entering, and these were baked to obtain the wiring board 1e.

以上のような配線基板1a〜1eの製造方法によれば、積層工程で最外層となるグリーンシートs1,s4の貫通孔hにビア導体vを形成し、最外層以外のグリーンシートs2,s3の何れか一方の貫通孔hにスルーホール導体tに形成し、これらの貫通孔hが連続するビアホール10を形成するように、グリーンシート1a〜1dを積層・圧着している。その結果、基板本体2を構成する複数のセラミック層S1〜S3またはセラミック層S2〜S4の厚み方向に沿って貫通するビアホール10内に、最外層のセラミック層S1,S4を除いたセラミック層S2,S3の何れかの貫通孔hにスルーホール導体Tが、これ以外のセラミック層S2,S3の貫通孔hにビア導体Vがほぼ同軸で形成される。   According to the method of manufacturing the wiring boards 1a to 1e as described above, the via conductors v are formed in the through holes h of the green sheets s1 and s4 that are the outermost layers in the stacking process, and the green sheets s2 and s3 other than the outermost layers are formed. The green sheets 1a to 1d are laminated and pressure-bonded so that the through-hole conductor t is formed in any one of the through-holes h, and the via-hole 10 in which the through-holes h are continuous is formed. As a result, the ceramic layers S2 excluding the outermost ceramic layers S1 and S4 are inserted into the via holes 10 penetrating along the thickness direction of the plurality of ceramic layers S1 to S3 or the ceramic layers S2 to S4 constituting the substrate body 2. A through-hole conductor T is formed in one of the through holes h of S3, and a via conductor V is formed substantially coaxially in the through-holes h of the other ceramic layers S2 and S3.

従って、かかるビア導体Vおよびスルーホール導体Tの電気的接続が十分可能であり、基板本体2の表面3および裏面4に露出するビア導体Vの端面が平坦とされた配線基板1a〜1eを確実に製造することができる。
更に、前記配線基板1a,1c,1d,1eでは、これらのスルーホール導体Tは、その軸方向の両端の開口部に隣接する上層および下層のビア導体Vの一部が進入して、上下一対の曲面部13が形成されるので、かかるスルーホール導体Tと隣接するビア導体Vとの電気的な接続を安定させられる。
しかも、配線基板1a,1b,1d,1eでは、そのスルーホール導体Tが、厚みが100μm以上のセラミック層s2,s3の貫通孔hの内壁面に沿って形成されているため、製造工程で導電性ペーストなどを容易に塗布して形成できる。
Therefore, the electrical connection between the via conductor V and the through-hole conductor T is sufficiently possible, and the wiring substrates 1a to 1e in which the end surfaces of the via conductor V exposed on the front surface 3 and the back surface 4 of the substrate body 2 are flat are reliably provided. Can be manufactured.
Further, in the wiring boards 1a, 1c, 1d, and 1e, the through-hole conductors T have a pair of upper and lower via conductors V that are adjacent to the openings at both ends in the axial direction, and a pair of upper and lower via conductors V enter. Therefore, the electrical connection between the through-hole conductor T and the adjacent via conductor V can be stabilized.
In addition, in the wiring boards 1a, 1b, 1d, and 1e, the through-hole conductor T is formed along the inner wall surface of the through hole h of the ceramic layers s2 and s3 having a thickness of 100 μm or more. It can be formed by easily applying a functional paste or the like.

本発明は、以上において説明した各形態や各製造方法に限定されない。
例えば、本発明の配線基板には、焼成後の厚みが全て100μm未満である複数のセラミック層を積層した基板本体を有し、何れかの中層のセラミック層に前記スルーホール導体が形成され、該スルーホール導体と連続し且つ基板本体の表面および裏面の少なくとも一方に露出するビア導体を有する形態も含まれる。
あるいは、本発明には、焼成後の厚みが全て100μm以上である複数のセラミック層を積層した基板本体を有し、何れかの中層のセラミック層に前記スルーホール導体が形成され、該スルーホール導体と連続し且つ基板本体の表面および裏面の少なくとも一方に露出するビア導体を有する形態の配線基板も含まれる。
また、前記セラミック層やグリーンシートのセラミックは、前記アルミナに限らず、ムライトや窒化アルミニウムなどとしたり、ガラス成分を約50wt%含む低温焼成セラミックとしても良い。
The present invention is not limited to each form and each manufacturing method described above.
For example, the wiring board of the present invention has a substrate body in which a plurality of ceramic layers each having a thickness after firing of less than 100 μm are laminated, and the through-hole conductor is formed on any middle ceramic layer, A form having a via conductor that is continuous with the through-hole conductor and exposed on at least one of the front surface and the back surface of the substrate body is also included.
Alternatively, the present invention includes a substrate body in which a plurality of ceramic layers each having a thickness after firing of 100 μm or more are laminated, and the through-hole conductor is formed on any middle ceramic layer, and the through-hole conductor And a wiring board having a via conductor exposed to at least one of the front surface and the back surface of the substrate body.
Further, the ceramic of the ceramic layer or the green sheet is not limited to alumina, but may be mullite, aluminum nitride, or the like, or a low-temperature fired ceramic containing about 50 wt% of a glass component.

更に、前記セラミック層やグリーンシートは、5層以上としても良く、前記基板本体も5層以上のセラミック層を有する形態としても良い。
また、前記ビアホール、ビア導体、およびスルーホール導体からなる組は、基板本体の厚み方向に沿って、複数組が任意の位置に形成されていても良い。
更に、前記ビアホール内に形成されるビア導体やスルーホール導体の間に、前記セラミック層間に形成される配線層が挟まれて接続される形態としても良い。
また、前記配線基板の製造方法は、一面にキャリアシートが添着されていない複数のグリーンシートを用いて行うことも可能であり、特にスルーホール導体を焼成後の厚みが100μm未満の比較的薄いグリーンシートの貫通孔に形成する場合には、適している。
加えて、前記配線基板の製造方法は、大版のグリーンシートを用いる多数個取りの方法として行っても良い。
Furthermore, the ceramic layer and the green sheet may have five or more layers, and the substrate main body may have five or more ceramic layers.
A plurality of sets of the via holes, via conductors, and through-hole conductors may be formed at arbitrary positions along the thickness direction of the substrate body.
Furthermore, a wiring layer formed between the ceramic layers may be sandwiched and connected between via conductors and through-hole conductors formed in the via holes.
In addition, the method of manufacturing the wiring board can be performed using a plurality of green sheets having no carrier sheet attached to one side, and in particular, a relatively thin green having a thickness of less than 100 μm after firing the through-hole conductor. It is suitable when it is formed in the through hole of the sheet.
In addition, the method of manufacturing the wiring board may be performed as a multi-cavity method using a large green sheet.

本発明による一形態の配線基板の要部を示す断面図。Sectional drawing which shows the principal part of the wiring board of one form by this invention. 異なる形態の配線基板の要部を示す断面図。Sectional drawing which shows the principal part of the wiring board of a different form. 更に異なる形態の配線基板の要部を示す断面図。Furthermore, sectional drawing which shows the principal part of the wiring board of a different form. 図1の配線基板の応用形態である配線基板の要部を示す断面図。Sectional drawing which shows the principal part of the wiring board which is an application form of the wiring board of FIG. 図1の配線基板を得るための一製造工程を示す概略図。Schematic which shows one manufacturing process for obtaining the wiring board of FIG. 図5に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図6に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図7に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図8に続く製造工程を示す概略図。Schematic which shows the manufacturing process following FIG. 図3の配線基板を得るための製造工程を示す部分概略図。FIG. 4 is a partial schematic view showing a manufacturing process for obtaining the wiring board of FIG. 3. 図10に続く製造工程を示す部分概略図。FIG. 11 is a partial schematic diagram illustrating a manufacturing process subsequent to FIG. 10. 図3の配線基板の変形形態の配線基板の要部を示す断面図。Sectional drawing which shows the principal part of the wiring board of the deformation | transformation form of the wiring board of FIG. 図12の配線基板を得るための一製造工程を示す概略図。Schematic which shows one manufacturing process for obtaining the wiring board of FIG.

符号の説明Explanation of symbols

1a〜1e…配線基板
2……………基板本体
3……………表面
4……………裏面
10…………ビアホール
S1〜S4…セラミック層
s1〜s4…グリーンシート
h……………貫通孔
V,v………ビア導体
T,t………スルーホール導体
cs…………キャリアシート
1a to 1e ... wiring board 2 ..... substrate body 3 ..... front surface 4 ........... back surface 10 ..... via hole S1-S4 ... ceramic layer s1-s4 ... green sheet h .... …… Through hole V, v ……… via conductor T, t ……… through hole conductor cs ………… carrier sheet

Claims (7)

貫通孔が形成されたセラミック層を含む複数のセラミック層を積層してなり、且つ表面および裏面を有する基板本体と、
上記基板本体の表面または裏面の少なくとも一方に開口し、且つ該基板本体の厚み方向に沿って複数の上記貫通孔が連続したビアホールと、
上記ビアホールを構成する複数の貫通孔のうち、上記基板本体の表面および裏面を形成する最外層のセラミック層の少なくとも一方の貫通孔に充填されたビア導体と、
上記ビアホールを形成する複数の貫通孔のうち、上記最外層のセラミック層以外のセラミック層の貫通孔の内壁面に沿って形成されたスルーホール導体と、を備える、
ことを特徴とする配線基板。
A plurality of ceramic layers including a ceramic layer having through holes formed thereon, and a substrate body having a front surface and a back surface;
A via hole that is opened in at least one of the front surface and the back surface of the substrate body, and the plurality of through holes are continuous along the thickness direction of the substrate body;
Among the plurality of through holes constituting the via hole, via conductors filled in at least one through hole of the outermost ceramic layer forming the front surface and the back surface of the substrate body,
A through-hole conductor formed along the inner wall surface of the through hole of the ceramic layer other than the ceramic layer of the outermost layer among the plurality of through holes forming the via hole,
A wiring board characterized by that.
前記スルーホール導体は、焼成後の厚みが100μm以上の前記セラミック層を貫通する貫通孔の内壁面に沿って形成されている、
ことを特徴とする請求項1に記載の配線基板。
The through-hole conductor is formed along the inner wall surface of the through hole that penetrates the ceramic layer having a thickness of 100 μm or more after firing.
The wiring board according to claim 1.
前記スルーホール導体の軸方向における少なくとも一方の開口部に、前記ビア導体の一部が進入している、
ことを特徴とする請求項1または2に記載の配線基板。
A part of the via conductor enters at least one opening in the axial direction of the through-hole conductor,
The wiring board according to claim 1 or 2, wherein
焼成後の厚みが100μm以上または100μm未満となる複数のグリーンシートに貫通孔を形成する工程と、
上記グリーンシートのうち、少なくとも積層工程で最外層となるグリーンシートに形成した上記貫通孔に導電性ペーストを充填してビア導体を形成する工程と、
上記最外層となるグリーンシート以外のグリーンシートに形成した上記貫通孔の内壁面に沿って、導電性ペーストを円環状に配設してスルーホール導体を形成する工程と、
少なくとも上記ビア導体およびスルーホール導体が形成された複数のグリーンシートを、該ビア導体とスルーホール導体とが軸方向に沿って連続するように積層する工程と、を含む、
ことを特徴とする配線基板の製造方法。
Forming through holes in a plurality of green sheets having a thickness after firing of 100 μm or more or less than 100 μm;
Among the green sheets, at least a step of forming a via conductor by filling a conductive paste into the through-hole formed in the green sheet that is the outermost layer in the lamination step;
A step of forming a through-hole conductor by arranging a conductive paste in an annular shape along the inner wall surface of the through hole formed in a green sheet other than the green sheet as the outermost layer;
Laminating a plurality of green sheets formed with at least the via conductor and the through-hole conductor such that the via conductor and the through-hole conductor are continuous along the axial direction.
A method of manufacturing a wiring board.
前記スルーホール導体が形成されるグリーンシートの焼成後の厚みは、100μm以上である、
ことを特徴とする請求項4に記載の配線基板の製造方法。
The thickness after firing of the green sheet on which the through-hole conductor is formed is 100 μm or more.
The method for manufacturing a wiring board according to claim 4.
一面に添着したキャリアシートを含んで前記貫通孔が貫通する前記グリーンシートは、前記導電性ペーストを充填してビア導体が形成された後、上記キャリアシートが剥離される、
ことを特徴とする請求項4または5に記載の配線基板の製造方法。
The green sheet including the carrier sheet attached to one surface and penetrating the through hole is filled with the conductive paste to form a via conductor, and then the carrier sheet is peeled off.
The method for manufacturing a wiring board according to claim 4 or 5, wherein:
前記キャリアシートが剥離された前記グリーンシートは、その一面側に突出する上記ビア導体の凸部を、前記積層工程において、該グリーンシートに隣接して積層され且つ前記スルーホール導体が形成されたグリーンシートの該スルーホール導体の軸方向における一方の開口部に進入するようにして積層される、
ことを特徴とする請求項6に記載の配線基板の製造方法。
The green sheet from which the carrier sheet has been peeled is formed by forming the via conductor protrusion protruding on one side of the green sheet adjacent to the green sheet and forming the through-hole conductor in the stacking step. Laminated so as to enter one opening in the axial direction of the through-hole conductor of the sheet,
The method for manufacturing a wiring board according to claim 6.
JP2008013283A 2008-01-24 2008-01-24 Wiring board and manufacturing method thereof Expired - Fee Related JP5166890B2 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03240289A (en) * 1990-02-19 1991-10-25 Fujitsu Ltd Manufacture of aluminum nitride substrate
JPH0629666A (en) * 1992-05-12 1994-02-04 Oki Electric Ind Co Ltd Via forming method in ceramic multilayered substrate
JPH0645758A (en) * 1992-07-24 1994-02-18 Matsushita Electric Ind Co Ltd Multilayer ceramic board and manufacture thereof
JP2005129884A (en) * 2003-10-20 2005-05-19 Samsung Electro Mech Co Ltd Multi-layer printed circuit board improved in inter-layer electrical connection and method for manufacturing the same
JP2006165242A (en) * 2004-12-07 2006-06-22 Matsushita Electric Ind Co Ltd Printed-wiring board and its manufacturing method
JP2007142399A (en) * 2005-11-16 2007-06-07 Samsung Electro-Mechanics Co Ltd Printed circuit board using paste bump and method of manufacturing same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03240289A (en) * 1990-02-19 1991-10-25 Fujitsu Ltd Manufacture of aluminum nitride substrate
JPH0629666A (en) * 1992-05-12 1994-02-04 Oki Electric Ind Co Ltd Via forming method in ceramic multilayered substrate
JPH0645758A (en) * 1992-07-24 1994-02-18 Matsushita Electric Ind Co Ltd Multilayer ceramic board and manufacture thereof
JP2005129884A (en) * 2003-10-20 2005-05-19 Samsung Electro Mech Co Ltd Multi-layer printed circuit board improved in inter-layer electrical connection and method for manufacturing the same
JP2006165242A (en) * 2004-12-07 2006-06-22 Matsushita Electric Ind Co Ltd Printed-wiring board and its manufacturing method
JP2007142399A (en) * 2005-11-16 2007-06-07 Samsung Electro-Mechanics Co Ltd Printed circuit board using paste bump and method of manufacturing same

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