JP2009124109A5 - - Google Patents

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Publication number
JP2009124109A5
JP2009124109A5 JP2008240357A JP2008240357A JP2009124109A5 JP 2009124109 A5 JP2009124109 A5 JP 2009124109A5 JP 2008240357 A JP2008240357 A JP 2008240357A JP 2008240357 A JP2008240357 A JP 2008240357A JP 2009124109 A5 JP2009124109 A5 JP 2009124109A5
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JP
Japan
Prior art keywords
bias power
power level
substrate
polymer film
flow rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008240357A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009124109A (ja
JP5553496B2 (ja
Filing date
Publication date
Priority claimed from US11/861,032 external-priority patent/US7846846B2/en
Application filed filed Critical
Publication of JP2009124109A publication Critical patent/JP2009124109A/ja
Publication of JP2009124109A5 publication Critical patent/JP2009124109A5/ja
Application granted granted Critical
Publication of JP5553496B2 publication Critical patent/JP5553496B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2008240357A 2007-09-25 2008-09-19 開口部側壁に形成した高分子の処理により高アスペクト比の開口部におけるエッチプロファイルの屈曲と湾曲を防止する方法 Expired - Fee Related JP5553496B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/861,032 US7846846B2 (en) 2007-09-25 2007-09-25 Method of preventing etch profile bending and bowing in high aspect ratio openings by treating a polymer formed on the opening sidewalls
US11/861,032 2007-09-25

Publications (3)

Publication Number Publication Date
JP2009124109A JP2009124109A (ja) 2009-06-04
JP2009124109A5 true JP2009124109A5 (enExample) 2012-12-20
JP5553496B2 JP5553496B2 (ja) 2014-07-16

Family

ID=39952217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008240357A Expired - Fee Related JP5553496B2 (ja) 2007-09-25 2008-09-19 開口部側壁に形成した高分子の処理により高アスペクト比の開口部におけるエッチプロファイルの屈曲と湾曲を防止する方法

Country Status (6)

Country Link
US (1) US7846846B2 (enExample)
EP (1) EP2043139A2 (enExample)
JP (1) JP5553496B2 (enExample)
KR (1) KR101019930B1 (enExample)
CN (1) CN101447425B (enExample)
TW (1) TWI367527B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100330805A1 (en) * 2007-11-02 2010-12-30 Kenny Linh Doan Methods for forming high aspect ratio features on a substrate
KR101575190B1 (ko) * 2010-02-12 2015-12-08 삼성전자주식회사 윗면과 바닥면의 시디차가 없는 깊은 트렌치를 갖는 반도체 및 제조방법
CN101866848B (zh) * 2010-04-29 2012-05-30 中微半导体设备(上海)有限公司 一种刻蚀有机物层的等离子刻蚀方法
US9165785B2 (en) 2013-03-29 2015-10-20 Tokyo Electron Limited Reducing bowing bias in etching an oxide layer
US9275869B2 (en) * 2013-08-02 2016-03-01 Lam Research Corporation Fast-gas switching for etching
KR102203460B1 (ko) 2014-07-11 2021-01-18 삼성전자주식회사 나노구조 반도체 발광소자의 제조방법
KR20160119329A (ko) 2015-04-02 2016-10-13 삼성전자주식회사 반도체 소자의 미세패턴 형성방법
KR102345979B1 (ko) 2015-04-30 2021-12-31 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN111063655A (zh) * 2018-10-17 2020-04-24 无锡华润上华科技有限公司 一种半导体器件的制造方法
CN111785604B (zh) * 2019-04-04 2025-04-08 中微半导体设备(上海)股份有限公司 气体喷淋头、制作方法及包括气体喷淋头的等离子体装置
US12479004B2 (en) 2019-10-18 2025-11-25 Lam Research Corporation Selective attachment to enhance SiO2:SiNx etch selectivity
US11437230B2 (en) 2020-04-06 2022-09-06 Applied Materials, Inc. Amorphous carbon multilayer coating with directional protection
US12106971B2 (en) 2020-12-28 2024-10-01 American Air Liquide, Inc. High conductive passivation layers and method of forming the same during high aspect ratio plasma etching
KR20230050130A (ko) * 2021-10-07 2023-04-14 삼성전자주식회사 식각 공정을 이용하는 집적회로 소자의 제조 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9616225D0 (en) * 1996-08-01 1996-09-11 Surface Tech Sys Ltd Method of surface treatment of semiconductor substrates
US6187685B1 (en) * 1997-08-01 2001-02-13 Surface Technology Systems Limited Method and apparatus for etching a substrate
US6228775B1 (en) 1998-02-24 2001-05-08 Micron Technology, Inc. Plasma etching method using low ionization potential gas
JP4153606B2 (ja) * 1998-10-22 2008-09-24 東京エレクトロン株式会社 プラズマエッチング方法およびプラズマエッチング装置
DE69942034D1 (de) * 1998-11-04 2010-04-01 Surface Technology Systems Plc Verfahren zur ätzung eines substrats
JP2002110647A (ja) 2000-09-29 2002-04-12 Hitachi Ltd 半導体集積回路装置の製造方法
JP5174319B2 (ja) * 2005-11-11 2013-04-03 株式会社日立ハイテクノロジーズ エッチング処理装置およびエッチング処理方法
US7713430B2 (en) * 2006-02-23 2010-05-11 Micron Technology, Inc. Using positive DC offset of bias RF to neutralize charge build-up of etch features
KR100763514B1 (ko) 2006-06-30 2007-10-04 삼성전자주식회사 반도체 장치의 개구 형성 방법 및 이를 이용한 반도체 장치제조 방법
US7682986B2 (en) * 2007-02-05 2010-03-23 Lam Research Corporation Ultra-high aspect ratio dielectric etch
US20080203056A1 (en) * 2007-02-26 2008-08-28 Judy Wang Methods for etching high aspect ratio features

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