JP2009094191A - Manufacturing method of multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a multilayer wiring board in which an external-layer wiring pattern can be accurately formed without making manufacturing processes complicated. <P>SOLUTION: After an external wiring layer 30 is laminated on an internal-layer circuit board 10 or an intermediate external-layer circuit board laminated on the internal-layer circuit board, a hole for a via 47 is formed in the external-layer insulating layer and a hole for an external-layer alignment mark 57 is formed based upon an alignment mark 22 formed on the internal-layer circuit board or intermediate external-layer circuit board, so that the external wiring pattern is formed based upon an external-layer alignment mark consisting of the holes. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a multilayer wiring board formed by laminating one or more outer layer circuit boards on an inner layer circuit board by a build-up method.

  In recent years, electrical devices have been reduced in size and weight, and the wiring boards used therefor are also required to be reduced in size and mounted in high density. As a conventional wiring board of this type, for example, a build-up method for manufacturing a multilayer wiring board by alternately stacking insulating layers and conductor layers (wiring layers) is known.

  A general build-up method will be described. An outer layer insulating layer and a conductor layer are sequentially stacked on an inner layer circuit board formed by forming a wiring pattern on an inner layer insulating substrate, and the wiring pattern is formed on the outer layer insulating layer and the conductor layer. A via that communicates with is formed. Then, the inner circumference of the via is made conductive by means such as electroless plating, and electrolytic plating is performed while energizing the conductor layer and the inner circumference of the via by the power feeding means. By removing unnecessary portions of the electrolytic plating layer thus obtained by etching or the like, a predetermined conductor pattern is formed, and a multilayer wiring board is manufactured.

  By the way, in such a build-up multilayer wiring board manufacturing method, the position of the via formed in the outer insulating layer and the position of the outer wiring pattern formed by photo-etching the electrolytic plating layer of the outer insulating layer are the inner circuit board. It is required to accurately align with the inner layer wiring pattern. For this reason, in the formation of vias in the outer insulating layer and the photoetching of the electrolytic plating layer, the processing position is set based on the alignment mark formed on the inner circuit board or the outer insulating layer.

  For example, in Patent Document 1 below, an insulating layer and a conductor layer are stacked on a core substrate on which a wiring pattern provided with an alignment mark including a through hole is formed in advance, and a wiring pattern and a via hole are formed using the alignment mark as a reference. In a method for manufacturing a multilayer printed wiring board in which insulating layers and wiring patterns are alternately laminated, a wavelength of 600 nm or more is used as a confirmation light for a through-hole used as an alignment mark formed in advance on the substrate at the time of alignment A method for manufacturing a printed wiring board is disclosed, which uses the transmitted light. In this method, vias and wiring patterns of the outer insulating layer are formed with reference to the alignment mark formed at the end of the inner circuit board.

Further, in Patent Document 2 below, an insulating core and a conductor layer are laminated as outer layers on an inner core substrate having copper foil on both sides of an insulating base material, and a wiring pattern is formed on the conductor layer with reference to an alignment mark. In the method of manufacturing a multilayer printed wiring board, the step of forming an alignment mark on the copper foil, the step of covering the alignment mark with a masking material in advance before laminating the insulating layer, and after laminating the conductor layer A multilayer printed wiring board comprising: a step of forming a cut groove penetrating from the conductor layer to the masking material; and a step of removing the outer layer together with the masking material at a position coinciding with the alignment mark. A manufacturing method is disclosed.
JP 2006-100525 A JP 2006-237088 A

  However, in the above conventional method, the vias and the wiring pattern of the outer insulating layer are formed on the basis of the alignment marks formed at the end of the inner layer circuit board. Sometimes, the expansion / contraction of the base material in the processing step or storage environment differs between a portion where the outer insulating layer is laminated and a portion where the outer insulating layer is not laminated, which causes a positional shift. In particular, the thermal process and mechanical process after the via formation of the outer insulating layer, the range where the outer insulating layer is laminated by the temperature and humidity in the storage state, and the range where the outer insulating layer is not laminated (the inner alignment mark exists) A difference occurs in the expansion and contraction of the substrate. For this reason, when the outer layer wiring pattern is formed on the basis of the inner layer alignment mark, a positional deviation occurs between the outer layer via. Therefore, if the via land which is a part of the outer layer pattern is formed small, the outer layer via is detached from the land and causes a defect. In order to avoid this, the high density is obstructed by increasing the land diameter.

  Further, in the above conventional method, it is necessary to cover the alignment mark with a masking material in advance before laminating the insulating layer and to form a cut groove penetrating from the conductor layer to the masking material after laminating the conductor layer. As a result, the manufacturing process becomes complicated and the manufacturing workability is poor.

    Accordingly, an object of the present invention is to provide a multilayer wiring board that enables high-density wiring without the need to unnecessarily widen via lands by improving the positional accuracy of outer layer wiring patterns and outer layer vias without complicating the manufacturing process. It is in providing the manufacturing method of.

  In order to achieve the above object, a method for manufacturing a multilayer wiring board according to the present invention provides an inner layer circuit board in which an inner layer wiring pattern is formed on at least one surface of an inner layer insulating board, and an outer layer insulating layer with respect to the inner layer insulating board. An outer layer circuit board having an outer layer wiring pattern formed on an outer surface, and a multilayer wiring board in which one or more outer layer circuit boards are laminated on at least one side of the inner layer circuit board by a build-up method In this method, after the outer insulating layer is laminated on the inner circuit board or the intermediate outer circuit board laminated on the inner circuit board, the alignment mark formed on the inner circuit board or the intermediate outer circuit board is used as a reference. Forming a hole for a via in the outer insulating layer and a hole for an outer alignment mark, and forming an outer alignment mark formed of the hole. Based on the, and forming an outer layer wiring pattern on the outer insulating layer.

  According to the present invention, a hole for a via is formed in the outer insulating layer on the basis of the alignment mark formed on the inner layer circuit board or the intermediate outer layer circuit board laminated on the inner layer circuit board, and the outer layer alignment mark is formed. Forming an outer layer wiring pattern on the basis of the outer layer alignment mark made of this hole, the positional accuracy between the outer layer alignment mark and the outer layer wiring pattern is maintained, and the outer layer wiring pattern is accurately Can be formed at any position. That is, the positions of the inner layer wiring pattern, the intermediate outer layer wiring pattern, and the outer layer via are formed by forming a via hole in the outer layer insulating substrate with reference to the alignment mark formed on the inner layer circuit board or the intermediate outer layer circuit board. The accuracy can be determined accurately, and the holes for the outer layer alignment marks formed at the same time have the same positional accuracy as the inner layer wiring pattern and the intermediate outer layer wiring pattern. Also, in the positional accuracy of the outer layer pattern and the outer layer via, since the outer layer alignment mark and the outer layer via are formed in the same process, it can be kept particularly good by forming the outer layer pattern based on the outer layer alignment mark. Is possible. Especially after formation of outer layer via and outer layer alignment mark, expansion and contraction of the substrate due to various processes and storage environment (mechanical polishing process, thermal process, internal stress by plating process, moisture absorption by wet process, etc. (It can be considered as a process that easily expands and contracts), so that the outer layer alignment mark and the outer layer via exist on the same layer structure, so there is no so-called “displacement” due to the difference in expansion and contraction, and the influence is minimized. Even if expansion or contraction occurs, the position is almost uniform, and the position can be easily matched by correcting the magnification at the time of exposure. As a result, the product defect rate due to pattern deviation can be reduced, and it is not necessary to unnecessarily widen the land diameter to absorb the deviation between the via and the pattern, making it possible to cope with higher density wiring patterns. Become. In addition, when forming the via hole in the outer insulating layer, the outer alignment mark hole is formed together so that the manufacturing process is not complicated.

  In the present invention, the alignment mark formed on the inner circuit board or the intermediate outer circuit board is an alignment mark used as a reference when forming the wiring pattern of the circuit board, or the wiring pattern of the circuit board is formed. It is preferable that the alignment mark is formed at the same time as the reference alignment mark, or the alignment mark is formed at the same time as the wiring pattern of the circuit board. These alignment marks are in a positional relationship defined with respect to the inner layer wiring pattern or the intermediate outer layer wiring pattern, and by forming holes for outer layer vias and outer layer alignment marks based on these alignment marks. The holes for the outer layer via and the outer layer alignment mark can be accurately positioned with respect to the inner layer wiring pattern or the intermediate outer layer wiring pattern.

  In particular, in a method of manufacturing a multilayer wiring board in which a plurality of outer layer circuit boards are laminated by a build-up method, after laminating the outer insulating layer on an intermediate outer layer circuit board laminated on the inner layer circuit board, With reference to an intermediate outer layer alignment mark formed on the intermediate outer layer circuit board, a hole for a via is formed in the outer insulating layer and a hole for the outer layer alignment mark is formed, and the outer layer alignment mark including the hole is used as a reference. Thus, it is preferable to form an outer layer wiring pattern. In this case, the intermediate outer layer alignment mark is an alignment mark used as a reference when forming the intermediate outer layer wiring pattern, an alignment mark formed simultaneously with the alignment mark used as the reference when forming the intermediate outer layer wiring pattern, or The alignment mark is preferably formed simultaneously with the intermediate outer layer wiring pattern. According to this, the positional relationship with the pattern of the adjacent layer can be formed accurately, which is advantageous in the formation of a circuit board in which the positional relationship with the lower layer pattern such as a high frequency circuit is important.

  In the present invention, the alignment mark formed on the inner layer circuit board or the intermediate outer layer circuit board is formed on a portion of the circuit board that extends outward from the edge of the outer layer insulating layer. It is preferable. According to this aspect, even if the outer insulating layer is laminated, the alignment mark is not hidden, so that it can be clearly recognized without a troublesome process such as partial removal of the outer insulating layer. . Furthermore, in the case of stacking a plurality of layers, the outer layer alignment mark may be formed with reference to the common inner layer alignment mark, but the intermediate outer layer alignment mark is formed at a portion extending outward from the edge of the outer insulating layer. However, the outer layer alignment mark may be formed on the basis of this, and in particular, the wiring pattern and outer layer via of the immediately lower layer are determined by using the alignment mark of the immediately lower layer sequentially formed with reference to the inner layer formed first. Can be positioned more accurately. Since which interlayer accuracy is important depends on the design, any one may be used as long as it is properly used depending on the accuracy required in each layer.

  In the present invention, it is preferable that after forming the via hole and the outer layer alignment hole, the inner wall of each hole is cleaned by physical cleaning. According to this aspect, the shape of the hole for the outer layer alignment can be increased without increasing the number of processes by physically cleaning the inner periphery of the hole for the outer layer simultaneously with the physical cleaning of the inner periphery of the hole for the via. Can be formed accurately, and the accuracy of alignment can be improved.

  Further, in the present invention, the formation of the outer layer wiring pattern based on the outer layer alignment mark is performed by exposing and developing using a photomask aligned with the outer layer alignment mark as a reference when patterning with a photoresist. Thus, it is preferable to perform this by forming a predetermined resist pattern.

  Hereinafter, with reference to FIGS. 1-8, one embodiment of the manufacturing method of the multilayer wiring board by this invention is demonstrated. However, this invention is not restrict | limited by the following embodiment.

  FIG. 1 shows a schematic cross-sectional view of a multilayer wiring board 1 manufactured by the method for manufacturing a multilayer wiring board of the present invention. In this embodiment, the multilayer wiring board 1 includes an inner layer circuit board 10 in which inner layer wiring patterns 15 and 15 are formed on both front and back surfaces of an inner layer insulating substrate 11, and an adhesive layer 25 provided on both front and back surfaces of the inner layer circuit board 10. , 25, outer layer insulating layers 30, 30 laminated on the front and back sides of the inner layer circuit board 10 via the adhesive layers 25, 25, and outer layers formed on the surfaces of the outer layer insulating layers 30, 30, respectively. The wiring patterns 40 and 40 are included.

  Next, the configuration of each layer of the multilayer wiring board 1 will be described in more detail. First, the inner layer circuit board 10 will be described. Conductor wirings 13 and 13 are respectively formed on the front and back surfaces of the inner layer insulating substrate 11, and a predetermined inner layer wiring pattern 15 is provided thereby. Further, a round hole-shaped via 17 (see FIG. 6) is formed through a predetermined portion of the inner layer insulating substrate 11, and the inner layer insulating substrate 11 is connected via a connection portion 18 provided in the via 17. Inner layer wiring patterns 15, 15 formed on both front and back surfaces are electrically connected.

  The inner layer circuit board 10 is typically a copper-clad laminate, a so-called CCL (copper), in which a conductor material such as a copper foil is laminated on an inner layer insulating substrate 11 made of an insulating material such as a resin film described later. Clad laminate) is used as a core substrate, and an unnecessary portion of a conductive material such as copper foil is etched by a subtractive method or the like to leave a necessary conductive wiring 13 and form a predetermined inner wiring pattern 15 The shape is made. As described above, the inner layer circuit board 10 is typically formed by a subtractive method using an etching process, but may be formed by a semi-additive method using electrolytic plating, and the like. Is not to be done. The inner layer circuit board 10 may be formed with an inner layer wiring pattern 15 composed of a plurality of conductor wirings 13 only on one side of the inner layer insulating substrate 11, but on both front and back surfaces of the inner layer insulating substrate 11 as in this embodiment. It is particularly advantageous from the viewpoint of increasing the density that a plurality of conductor wirings 13 are provided and are electrically connected via the connecting portions 18 in the vias 17. The inner diameter of the round hole-shaped via 17 is appropriately set according to the purpose, but it is preferably 10 to 100 μm from the viewpoint of increasing the density, and 20 to 100 μm from the viewpoint of stable via connection. More preferred. In addition, a round hole shape is desirable from the viewpoint of stress dispersion, but a shape other than a round shape such as a square hole may be used depending on the design.

  The material of the inner layer insulating substrate 11 is not particularly limited, but the inner layer insulating substrate 11 is formed of a component containing a synthetic resin, and the plurality of conductor wirings 13 constituting the inner layer wiring pattern 15 formed on the front and back surfaces thereof are as follows. Generally, it is made of a metal material. As the inner layer insulating substrate 11, for example, a polyimide film, a polyamide film, a liquid crystal film, an aramid, a glass epoxy material or the like can be used. Particularly, those using a polyimide film for the insulating layer are excellent in heat resistance and dimensional stability, Not only is it thin and strong and suitable for high density, but also has flexibility, it is suitable for a wide range of applications. Moreover, as CCL which used the polyimide for the inner-layer insulation board | substrate 11, what heat-pressed the copper foil to the polyimide film through the meltable polyimide layer, the thing which cast and heated the polyimide precursor to copper foil, a polyimide Examples of the film include surface treatment of the film, sputtering a seed layer such as nichrome as a seed layer, sputtering copper, and electrolytic copper plating thereon to form a copper foil layer.

  On the other hand, the conductor material of the conductor wiring 13 that forms the inner layer wiring pattern 15 includes a metal foil such as copper, aluminum, gold, silver, nickel, and stainless steel, a metal plating layer (preferably a deposited metal underlayer-metal plating layer or Many known techniques such as a chemical metal plating layer can be applied), and the like is laminated on the inner insulating substrate 11 in the form of a foil, or the surface of the inner insulating substrate 11 is sputtered. In this case, a metal mainly composed of copper is most commonly used. In addition, when the said conductor material laminated | stacked on the inner-layer insulation board | substrate 11 is 5-35 micrometers in comparatively thick foil, it is used for a subtractive method, and the same conductor material is 0.5-5 micrometers ultra-thin foil. In this case, it is suitable for the semi-additive method or the case where electrolytic metal plating is stacked and used, such as when the conductor wirings 13 and 13 on both sides are connected via the via 17. In addition, it is also possible to use an ultrathin copper foil having a removable carrier layer that is thermocompression bonded to a polyimide film via a fusion layer, particularly in the case of an ultrathin copper foil of 0.5 to 3 μm. Since the total thickness of the conductor can be suppressed even when the electrolytic copper plating is stacked, it is suitable for forming fine wiring with a pitch of 40 μm or less.

  The inner layer insulating substrate 11 or the inner layer circuit substrate 10 on which a conductor layer or a wiring pattern is formed can be used in any form as long as it can be used without any problem in this manufacturing method. It is preferable to use a tape shape, a film shape, a sheet shape or the like. In particular, a long substrate that can be wound around rolls 101 and 107 (see FIG. 9) having a diameter of about 250 mm, which will be described later, is preferably employed. More specifically, the thickness of the inner insulating substrate 11 constituting the inner layer circuit board 10 is 5 to 150 μm, and the thickness of the outer insulating layer 30 described later is 5 to 50 μm. It is preferable to perform continuous treatment by the roll-to-roll method shown in 9 in order to increase productivity.

  As shown in FIG. 1, outer insulating layers 30, 30 are connected to both front and back surfaces of the inner circuit board 10 through adhesive layers 25, 25. The adhesive layer 25 is formed by applying a liquid adhesive resin on the inner layer circuit board 10 by a method such as coating, printing, or coating, or by laminating or pressing a bonding sheet in which the adhesive resin is previously formed into a film. Etc., and may be formed on the inner layer circuit board 10 without any particular limitation. In this embodiment, the adhesive layer 25 is bonded as a bonding sheet on the back surface side of the so-called single-sided CCL, in which the conductor layer 45 is bonded to the front surface side of the outer insulating layer 30 (FIG. 2B). reference). In addition, as the adhesive resin, epoxy, acrylic, urethane, siloxane, or the like is used, and those that are filled and bonded by thermoplasticity or those that use both thermoplasticity and thermosetting properties are employed. Here, the term “thermosetting” does not necessarily include a thermal cross-linking component or the like, but includes a substance that substantially loses thermoplasticity due to gelation or natural cross-linking by heating and has the same effect. A combination of thermoplasticity and thermosetting is a press machine that uses thermoplasticity to heat and press in vacuum for a short time to ensure filling between the inner layer wiring and then heat and cure in an oven for a specified time. It is advantageous to obtain a sufficient adhesion strength with a short occupation time. Further, the thickness of the adhesive layer 25 may be any thickness as long as the inner circuit board 10 and the outer insulating layer 30 described later can be bonded together. Preferably used.

  Next, the outer layer insulating layers 30 and 30 are formed on the front and rear surfaces of the inner layer circuit board 10 through the adhesive layers 25 and 25, and the outer layer wiring pattern formed by being laminated on the surface of the outer layer insulating layers 30 and 30, respectively. 40 will be described. As the outer insulating layer 30, for example, a polyimide film, a polyamide film, a liquid crystal film, an aramid, a glass epoxy material, or the like is used similarly to the inner insulating substrate 11 constituting the inner circuit board 10 described above. As described above, the thickness of the outer insulating layer 30 is preferably 5 to 50 μm from the viewpoint of employing the roll-to-roll method shown in FIG.

  On the other hand, in this embodiment, the outer layer wiring pattern 40 formed on each outer layer insulating layer 30, 30 has conductor layers 45, 45 respectively formed in a predetermined pattern on the surface of the outer layer insulating layer 30, 30. The conductor layers 45 are formed of plated conductor layers 50 and 50 formed on the conductor layers 45 and 45. In addition, a round hole-shaped via 47 is provided at a predetermined position of each outer insulating layer 30, and the via 47 further penetrates the adhesive layers 25, 25 to form an inner circuit board. The inner layer wiring patterns 15 and 15 provided on the front and back surfaces of the inner layer 10 are formed at a depth reaching each. A conductive layer 52 is formed on the inner periphery of the via 47, and a plated conductor layer 50 is formed in the via 47 from the conductor layer 45. One end of the plated conductor layer 50 is formed on the inner layer wiring pattern 15. The outer layer wiring pattern 40 and the inner layer wiring pattern 15 are electrically connected to each other. The inner diameter of the round hole-shaped via 47 is appropriately set, and is preferably 10 to 100 μm from the viewpoint of increasing the density, and more preferably 20 to 100 μm from the viewpoint of stable via connection. In addition, a round hole shape is desirable from the viewpoint of stress dispersion, but a shape other than a round shape such as a square hole may be used depending on the design. In this embodiment, only one via 47 is shown for convenience for each outer layer insulating layer 30, but in reality, a plurality of vias 47 are formed for higher density, and the outer layer wiring pattern 40 is formed by the inner layer circuit. The inner layer wiring pattern 15 of the substrate 10 is electrically connected at a plurality of locations. In addition, the interlayer connection may be achieved independently by filling a conductive material such as a conductive paste. In this case, the outer layer wiring pattern 40 may be composed of only the conductor layer 45 if the electrical and mechanical characteristics are sufficient. The plated conductor layer 50 is not always necessary.

  Each conductor layer 45 is made of, for example, a metal foil such as copper, aluminum, gold, silver, nickel, stainless steel or the like, preferably 0.5 to 35 μm, like the conductive material of the conductor wiring 13 of the inner layer circuit board 10. A thickness of 3 to 35 μm is preferable from the viewpoint of ensuring electrical and mechanical characteristics, because a high wiring density can be easily formed together with the thickness of the plated conductor layer 50 described later. In this embodiment, as shown in FIG. 2B, a so-called single-sided CCL formed by attaching a conductor layer 45 to the surface side of the outer insulating layer 30 is used. Further, as described above, the adhesive layer 25 is bonded to the back surface side of the outer insulating layer 30 as a bonding sheet.

  Here, the method of separately preparing the outer insulating layers 30 and 30 and the adhesive layers 25 and 25 has been described. However, the adhesive layer 25 can be maintained if necessary characteristics in the design of the substrate can be maintained in a state of being laminated on the inner substrate. May also serve as the outer insulating layer 30. It is also possible to use a so-called copper foil with resin (RCC) in which an adhesive resin layer is formed on a copper foil.

  Further, the plating conductor layer 50 laminated on the surface of the conductor layer 45 is subjected to various platings such as gold, silver, copper, nickel, etc. In this embodiment, the copper plating is applied. Yes. The plated conductor layer 50 made of copper plating is applied to a thickness of 1 to 25 μm, and is applied so as to be approximately 3 to 35 μm together with the thickness of the conductor layer 45 described above.

  Next, a process for manufacturing the multilayer wiring board 1 having the above-described configuration by the method for manufacturing a multilayer wiring board of the present invention will be described. 2 to 5 are schematic configuration sectional views showing an embodiment of the manufacturing method of the present invention in the order of steps.

  As shown in FIG. 2A, the inner layer circuit board 10 has the inner layer wiring patterns 15 formed of a plurality of conductor wirings 13 formed on both the front and back surfaces of the inner layer insulating substrate 11, as described above. It is in the shape of being electrically connected via. In the present invention, as shown in FIG. 2B, the inner layer circuit board 10 is formed so as to be larger than a laminated body 55 formed by laminating the adhesive layer 25, the outer insulating layer 30, and the conductor layer 45. In other words, it is larger than the outer insulating layer 30 and the conductor layer 45, and has a shape protruding from the peripheral portions on the left and right sides of the outer insulating layer 30 and the outer wiring pattern 40 by a predetermined length. In the projecting state shown in FIG. 1, the exposed conductor portions 20 to be cut and removed are provided on the protruding portions at both the left and right positions of the inner insulating substrate 11 and on both the front and back surfaces. ing.

  FIG. 6 shows a plan view of the inner layer circuit board 10 during the manufacturing process. That is, the inner layer insulating substrate 11 forming the inner layer circuit board 10 is continuously supplied to the production line in the form of a roll-shaped sheet, and feed holes 14 (so-called sproget holes) are formed at predetermined intervals on both sides of the sheet. It is formed with. Further, an inner layer wiring pattern 15 made of a conductor wiring 13 and a via 17 are formed at the center of the sheet of the inner layer insulating substrate 11. The connection portion 18 described above is formed in the via 17.

  In the figure, reference numeral 22 denotes an inner layer alignment mark used as a reference when forming the inner layer wiring pattern 15 and the via 17. That is, when the via 17 is formed, the processing position is set with reference to the inner layer alignment mark 22. The inner layer wiring pattern 15 made of the conductor wiring 13 is patterned by photoetching, for example, a conductor layer (including an electrolytic plating layer formed as necessary) formed on the inner insulating substrate 11. In etching, a photomask is positioned with reference to the inner layer alignment mark 22, exposed, and developed to form a resist pattern.

  The inner layer alignment mark 22 can be formed, for example, as a through hole by machining or the like when forming a feed hole (sproget hole) 14 to the inner layer insulating substrate 11. Further, the sproget hole 14 may be used as an inner layer alignment mark, or for example, via hole processing may be performed on the basis of the sproget hole, and the inner layer alignment mark 22 may be formed together. Also, another alignment mark 26 can be formed when the inner layer alignment mark 22 is formed. Furthermore, when the inner wiring pattern 15 is formed, the conductor layer may be left or removed in the form of dots to form another alignment mark 27. The alignment mark 27 is formed not as a hole but as a conductor pattern.

  Next, as shown in FIG. 2B, the conductor layer 45 before the predetermined pattern is formed is laminated on the front surface side of the outer insulating layer 30, and the adhesive layer 25 is pasted as a bonding sheet on the back surface side. The laminated body 55 is disposed at predetermined positions on both the front and back sides of the inner layer circuit board 10. At this time, each laminated body 55 is disposed so as to cover at least a part of the inner layer wiring patterns 15, 15 without covering the inner layer alignment marks 22, 22 and the exposed conductors 20, 20 of the inner layer circuit board 10.

  In the above state, as shown in FIG. 2 (c), the inner layer circuit board 10 is sandwiched between the laminated bodies 55, 55, and the outer layer insulating layer 30 and the inner layer circuit board 10 are bonded to both front and back surfaces via the adhesive layers 25, 25. A conductor layer 45 is laminated. In FIG. 2C, the outer insulating layers 30 and 30 are stacked so as to cover all of the inner wiring patterns 15 and 15 on both surfaces of the inner circuit board 10, but a part of the inner wiring pattern 15 is covered. The outer insulating layer 30 may be laminated as described above, and one side of the inner layer circuit board 10 may cover a part of the inner layer wiring pattern 15 and the remaining one side of the inner layer circuit board 10 may be covered.

Further, as shown in FIGS. 2B and 2C, the laminated body 55 only needs to be composed of the adhesive layer 25, the outer insulating layer 30, and the conductor layer 45. For example,
1) a base material in which the adhesive layer 25, the outer insulating layer 30 and the conductor layer 45 are laminated in advance;
2) The adhesive layer 25 and the outer insulating layer 30 having the conductor layer 45 on one side are formed as separate films,
3) An adhesive layer 25 provided in advance on the inner circuit board 10 and an outer insulating layer 30 having a conductor layer 45 on one side laminated on the adhesive layer 25;
4) What formed the adhesive resin layer which served as the adhesive layer 25 and the outer-layer insulating layer 30 inside the conductor layer 45,
Etc. can be used.

  In this embodiment, a so-called single-sided CCL formed by attaching a conductor layer 45 to the surface side of the outer insulating layer 30 is used and is laminated on the inner circuit board 10 via the adhesive layer 25. It has become. Here, the lamination to the inner layer circuit board 10 may be carried out so that the adhesive layer 25, the outer layer insulating layer 30, and the conductor layer 45 are laminated in this order on at least one inner layer wiring pattern 15 forming surface of the inner layer circuit board 10. Although there is no limitation, for example, a liquid adhesive may be applied to the inner layer wiring pattern 15 forming surface of the inner layer circuit board 10 and the CCL may be stacked and press cured so that the outer insulating layer 30 side is in contact. Alternatively, a bonding sheet may be overlapped between the CCL outer layer insulating layer 30 and the inner layer insulating substrate 11 so as to cover a part or all of the inner layer wiring pattern 15 and heated and pressed in a vacuum. In particular, a bonding sheet is previously laminated on the outer insulating layer 30 side of the CCL, for example, with a roll laminator, and the outer shape processed as needed is temporarily attached to the inner circuit board 10 and heated in a vacuum. Then, it is possible to stack various stacked bodies 55 accurately and efficiently. Moreover, in the case of roll-to-roll conveyance, the inner layer circuit board 10 and the laminate 55 may be continuously laminated on the inner layer circuit board 10 with a roll laminator in a vacuum. Conversely, the bonding sheet laminated on the inner layer circuit board 10 in a vacuum with a roll laminator may be laminated with a roll laminator or a press device so that the outer insulating layer 30 side of the CCL is in contact with the bonding sheet. In addition, when laminating the stacked bodies 55, 55 on both the front and back surfaces of the inner layer circuit board 10, the above method may be repeated, and until the middle, for example, until temporary bonding or heating press in vacuum is performed individually on the front and back sides. Subsequent steps may be performed simultaneously. Further, in the case of roll-to-roll conveyance, both the inner layer circuit board 10 and the laminate 55 may be continuously laminated with a roll laminator in a vacuum at the same time. In addition, additional heat curing of the adhesive layer can be performed in an oven or the like as necessary.

  Next, when the laminated body 55 is laminated on the inner layer circuit board 10 by the above process, the inner layer alignment marks 22, 22 provided on the portions extending outward from the edge of the outer insulating layer on both the left and right sides of the inner layer circuit board 10. 3a, as shown in FIG. 3A, round hole-shaped vias 47 and 47 are formed at predetermined positions of the adhesive layers 25, the outer insulating layer 30, and the conductor layer 45 of the laminates 55 and 55, respectively. At the same time, an outer layer alignment mark 57 is formed. Thus, by forming the outer layer alignment mark 57 simultaneously with the formation of the via 47 and forming the outer layer wiring pattern 40 with reference to the outer layer alignment mark 57, the positional accuracy of the outer layer wiring pattern 40 can be improved.

  FIG. 7 is a plan view showing a state in which the stacked body 55 is stacked on the inner circuit board 10 and the vias 47 are formed. The via 47 can be formed in one or more places of the stacked body 55 with reference to the inner layer alignment mark 22 of the inner layer circuit board 10. Then, when forming the via 47, a hole for the outer layer alignment mark 57 is formed at the same time. The via 47 and the outer layer alignment mark 57 can be formed with reference to the inner layer alignment mark 22 that is used as a reference when the inner layer wiring pattern 15 is formed, but the inner layer alignment mark that is used as a reference when the inner layer wiring pattern 15 is formed. The alignment mark 26 formed at the same time as 22 and the alignment mark 27 formed at the same time as the inner wiring pattern 15 can be used as a reference. Further, the outer layer alignment mark 57 may be any hole as long as it can be recognized as an alignment reference, and may be a stop hole as shown by 57 in FIG. 3, or for optical alignment using high contrast transmitted light. It may be a through hole. When forming alignment marks from the front and back with through holes, the positions may be shifted so as not to overlap. Also, in the case of such a printed wiring board, for example, a semiconductor chip is mounted on one surface and a solder ball is formed on the other surface, and in many cases, particularly high density is required only on one surface. In this case, an alignment mark by a through hole may be formed simultaneously with the outer layer via on the surface requiring high density, and this through hole may also be used as an alignment mark on the opposite surface where the demand for high density is low.

  When the via 47 and the outer layer alignment mark 57 are formed, the conductor layer 45 may be formed in the first step, and then the outer layer insulating layer 30 and the adhesive layer 25 may be formed in two steps. One step of making a hole in the outer insulating layer 30 and the adhesive layer 25 at a time may be used.

  The vias 47 and the outer layer alignment marks 57 can be formed by a known method, and it is particularly preferable to process using laser light. The laser beam used here is typified by carbon dioxide laser (wavelength 9.3 to 10.6 μm), YAG laser (wavelength 1064 nm), and harmonics of YAG laser (third harmonic: wavelength 355 nm, fourth harmonic: wavelength 266 nm). In addition, an excimer laser (wavelength varies depending on the gas type) using various gases may be used.

  The carbon dioxide laser is easy to obtain a large power at present, but is a light different from the wavelength band absorbed by the metal. For this reason, surface treatment such as blackening is performed when the metal is directly processed. That is, the surface of the multilayer body 55 is blackened, and then the portion where the via 47 is formed is irradiated with a pulsed laser beam with a narrowed beam diameter to remove the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25. The vias 47 are sequentially formed. Alternatively, the portion where the via 47 is formed may be selectively blackened, and the laser light may be scanned to remove the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25. Here, the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25 may be removed at a time. However, when it is necessary to reduce the thermal damage of the inner layer, the conductor layer 45 is first removed, and then the conductor layer 45 is mainly removed. The outer insulating layer 30 and the adhesive layer 25 can be removed by lowering the power density of the laser beam. As another method, the conductive layer 45 in the portion where the via 47 is formed may be selectively removed by etching or the like, and the adhesive layer 25 and the outer insulating layer 30 may be removed by scanning with laser light.

  Ultraviolet laser light typified by the harmonics of the YAG laser belongs to a wavelength band that is absorbed by the metal, so that the metal can be directly processed. In addition, it is considered that the effect of directly cutting the molecular bonds of the outer insulating layer 30 and the adhesive layer 25 mainly made of an organic material contributes, and the processed shape is better than that of a carbon dioxide laser that is mainly removed thermally. In addition, solid excitation lasers represented by YAG have a good beam shape, and the harmonics are short in wavelength with ultraviolet light, so that the beam can be narrowed down and suitable for forming a small diameter via 47 having an inner diameter of 50 μm or less. Yes. As a method of forming the via 47, a portion of the multilayer body 55 where the via 47 is processed is irradiated with a laser beam pulse narrowed down to a small diameter so that the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25 are formed. And a via 47 is formed. At this time, the pulse may be irradiated by a plurality of shots, or in the case of a hole larger than the beam diameter, for example, scanning may be performed spirally for each shot. In addition, the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25 may be removed at a time, but when it is necessary to reduce the damage of the inner layer, the conductor layer 45 is first removed, and then the laser is removed. The adhesive layer 25 and the outer insulating layer 30 may be removed by lowering the light power density. The conductor remaining after the conductor layer 45 is removed is used as a mask to irradiate a laser beam out of focus, and the outer insulating layer 30. When the adhesive layer 25 is removed, a particularly good hole shape can be obtained. This operation is sequentially repeated by changing the position for each hole.

  The excimer laser is a gas laser, which emits deep ultraviolet light, although the oscillation wavelength varies depending on the gas type, and is irradiated with a mask to remove the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25, and to have a small diameter. Hole drilling is possible, but because of the high running cost, it is for expensive products.

  Further, when the stacked bodies 55 and 55 are formed on both the front and back surfaces of the inner layer circuit board 10, the hole processing of the via 47 may be repeated for each front and back.

  Furthermore, here, the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25 of the laminated body 55 are removed, and the processing up to the surface of the inner layer wiring pattern 15 of the inner layer circuit board 10, that is, the formation of a standard blind via is described. However, vias to the back surface side of the inner layer circuit board 10, or vias to the back surface of the laminated body 55 on the back surface side of the inner layer circuit board 10, and further through holes may be used, and are adjusted appropriately by the laser beam power and the number of shots. That's fine.

  Moreover, when the laminated body 55 is an ultra-thin metal foil with a carrier layer, the via 47 may be formed after the carrier layer is peeled off, or may be formed before peeling. In the former case, the metal foil can be processed with a relatively weak laser power, so it is easy to obtain a good hole shape. In the latter case, the laser power is required to remove the entire carrier, but the metal foil surface is protected. Therefore, contamination of the surface by laser processing can be prevented.

  When the outer layer alignment mark 57 is formed simultaneously with the formation of the via 47, it is difficult to process the laser at the same time because the laser is generally processed by narrowing the beam, but the via 47 and the outer layer alignment mark 57 are formed. If the positioning is performed by a series of operations using the same alignment mark as a reference, the effect is the same and can be regarded as substantially simultaneous.

  As described above, as shown in FIG. 3A, after the vias 47 are formed in the stacked body 55, the inside of each outer layer alignment mark 57 and the inside of each via 47 are made of a permanganate solution or the like. Clean by chemical cleaning or physical cleaning such as wet blasting. This is a so-called desmear process, and the adhesion between the plating conductor layer 50 and the conductive layer 52 for electrically connecting the inner layer wiring pattern 15 of the inner layer circuit board 10 and the conductor layer 45 of the multilayer body 55. In particular, the contamination in the via 47 caused by laser processing is removed. The contamination is mainly caused by adhesion of the resin component of the adhesive layer 25 melted by the laser, the resin component of the outer insulating layer 30 and their alterations, and the molten conductor layer 45, and the inner layer is formed particularly by the formation of the via 47. Contamination due to the resin component in the exposed part of the wiring pattern 15 lowers the adhesion of the conductive layer 52 and the plating conductor layer 50 and causes a poor electrical connection. Further, when the outer insulating layer 30 and the adhesive layer 25 have different components, if either one of them is excessively eroded in the chemical desmear process, it may cause poor conduction due to poor adhesion or residual bubbles in the subsequent process. Become. In order to prevent these problems, in this embodiment, cleaning of the hole in the via 47 is physically performed. Since there is no chemical action in physical cleaning, it is possible to prevent one from being excessively eroded. Of course, there is a slight difference due to differences in hardness, but there is virtually no problem because the physical removal amount is also small.

  Specific physical cleaning methods include irradiation with deep ultraviolet light of 250 nm or less typified by excimer light, plasma treatment, drive blast treatment, and wet blast treatment. In the plasma treatment, a resin is etched by plasma generated by discharging a gas under a low pressure, and a complicated vacuum process is required. Further, since the etching rate of the resin is slow, it cannot cope with severe contamination. Drive-last treatment is a method of polishing by blowing abrasive powder together with high-pressure air, and it is possible to treat even fine holes, but there is a stall after injection, the polishing force is somewhat weak, and a large amount of dust is generated. However, it is difficult to use in a clean room. Wet blasting is a method of spraying a slurry mixed with abrasive grains and water with high-pressure air. The fine holes are also treated, and abrasives with high hardness and high polishing power such as water-insoluble alumina particles and zirconia particles. It is sprayed with fine water droplets using grains and has little stall. Therefore, a sufficient polishing force can be generated, which is particularly desirable as a physical cleaning method.

  As the wet blasting apparatus, for example, a mounting portion formed of a magnet for mounting the object to be processed shown in FIG. 3A in which the via 47 and the outer layer alignment mark 57 are formed, and the object to be processed An apparatus including a mask that is placed on the body and has a window hole of a desired shape that allows a liquid mixed with abrasive grains to pass therethrough and that is formed of a material that is magnetized on the placement portion. It is done. In the wet blasting apparatus, as a mask, a rubber member such as urethane rubber that contacts the upper surface of the object to be processed is provided below the metal member magnetized by the magnet. What provided the mask in which the window hole of the desired shape which allows the liquid which mixed the said abrasive grain to pass through was formed is preferable. Such a wet blasting apparatus is described in, for example, Japanese Patent Laid-Open No. 9-295266.

  In the wet blasting method, it is preferable to simultaneously remove burrs generated by drilling and clean the vias 47 and the outer layer alignment marks 57. For example, a liquid containing abrasive grains (preferably 5 abrasive grains) is used. ~ 20% by volume), preferably using abrasive grains such as alumina particles and zirconia particles having a high hardness and a high polishing power and having a diameter of about 1 to 10 μm. The workpiece is processed by high-pressure jetting at a flow rate of about 10 m to about 300 m / sec, preferably about 20 to about 100 m / sec, and more preferably about 30 to about 70 m / sec, together with the processing air toward the holes. be able to. In addition, when the laminated bodies 55 and 55 are formed on both front and back surfaces of the inner layer circuit board 10, they may be carried in the air and subjected to the above physical cleaning at the same time or repeated on both sides.

  After cleaning the inside of the outer layer alignment mark 57 and the via 47 as described above, the continuity for conducting the conductor layer 45 and the inner layer wiring pattern 15 of the inner layer circuit board 10 prior to electroplating described later. Process. That is, as shown in FIG. 3 (b), at least the inner peripheral surface of each via 47, preferably the outer peripheral surfaces of the stacked bodies 55, 55 stacked on the front and back surfaces of the inner layer circuit board 10, By forming the conductive layer 52 by direct plating or the like, the conductor layer 45 and the inner layer wiring pattern 15 of the inner layer circuit board 10 are electrically connected, preferably the conductor layer 45 and the exposed conductor part 20 are electrically connected, which is preferable for electrolytic plating. A power supply path is formed. In FIG. 3B, the conductive layer 52 is formed only on the inner peripheral surface of each outer layer alignment mark 57, the outer peripheral surface of the stacked bodies 55 and 55, and the inner peripheral surface of each via 47. If there is no problem in the adhesion to the layer and the etching property during pattern formation, the conductive layer 45 may be provided.

  As described above, the conduction step is performed by a general electroless metal plating step or direct plating step, and these can be simultaneously processed on both sides.

  Various known processes such as nickel and copper can be applied to the electroless metal plating. However, since the adhesiveness with the electrolytic copper plating frequently used for thickening the conductor layer 45 is excellent, the via plating of the wiring board is mainly used. Suitable for electroless copper plating.

  Materials used for the direct plating method include graphite-based and palladium-based materials, which are particularly desirable processes because the process is short and chemical management is relatively easy. In particular, when polyimide is used for the outer insulating layer 30, a direct plating method that can obtain a palladium-tin film using a palladium-tin colloidal catalyst is preferable because of excellent adhesion and less adverse effects on the environment. It is.

  In the palladium-tin colloidal direct plating method, monoethanolamine, nonionic surfactant, cationic surfactant, etc. are used to degrease the metal and polyimide film and adhesive layer surface in the hole, and the surface state is colloidal. Is then adsorbed easily, and then soft-etched using sodium persulfate soda, and then pre-diped into sodium chloride, hydrochloric acid and the like. After these steps, a palladium-tin film is formed by an activating step of immersing in a palladium-tin colloid solution, and finally, in an alkali accelerator bath and an acidic accelerator bath containing sodium carbonate, potassium carbonate and copper ions. What is necessary is just to add a reducing agent to the alkaline accelerator bath used for activation at the time of activation. A conductive film mainly composed of palladium is formed by the above process. In addition, this process treats both surfaces simultaneously by processing a base material in a liquid.

  After the inner wiring pattern 15 and the conductor layer 45 are made conductive as described above, the conductor layer of the laminated bodies 55 and 55 laminated on both the front and back surfaces of the inner layer circuit board 10 where the conductor is exposed, and the conduction. Electroplating is performed on the layer forming portion.

  That is, as shown in FIG. 8, a power supply in which the exposed conductor portions 20 provided on the protruding portions on both sides of the inner circuit board 10 that protrude from the peripheral portions on the left and right sides of the multilayer bodies 55 and 55 are provided on the left and right in pairs. The power feeding rollers 105 are brought into contact with the exposed conductor portions 20 by being sandwiched by the rollers 105 and 105, respectively. Then, the exposed conductor portion 20 of the inner layer circuit board 10 is applied to the cathode side via the power supply roller 105 connected to the cathode electrode, and conduction between the outer peripheral surfaces of the stacked bodies 55 and 55 that are conducted to the exposed conductor portion 20 is achieved. The layer 52, the conductor layer 45 on the surface of the outer insulating layer 30 that conducts to the conduction layer 52, and the conduction layer 52 in the outer via 47 that conducts to the conductor layer are applied to the cathode side.

  In this state, the inner layer circuit board 10 and laminates 55 and 55 laminated on both sides thereof are placed in a plating bath shown by 103 in FIG. 9 in which the anode electrode is disposed and the ionized electrolytic copper plating solution is stored. When the sheet is introduced, copper ions adhere to the exposed portion of the inner circuit board 10 and the surface of the conductive layer 52 and the conductor layer 45 of the laminated body 55, which are applied to the cathode side by the power supply roller 105. Layer 50 is formed. As a result, the inner layer wiring pattern 15 is electrically connected to the plated conductor layer 50 formed on the conductor layer 45 of the outer insulating layer 30 through the plated conductor layer 50 formed on the inner peripheral surface of the via 47. Then, by patterning the plated conductor layer 50 and the underlying conductor layer 45, an outer layer wiring pattern 40 described later is formed.

  In this way, the inner layer circuit board 10 is formed larger than the outer layer insulating layer 30 and the conductor layer 45, and at least part of the inner layer circuit board 10 protrudes from the peripheral portions of the outer layer insulating layer 30 and the conductor layer 45, and the outer layer An exposed conductor portion 20 that is partly in contact with the outer peripheral surface of the multilayer body 55 that forms the structure is connected, and a power feeding means composed of a power feeding roller 105 is connected to the exposed conductor portion 20, and electricity is supplied from this to at least the outer layer. By electrically plating the outer peripheral surface of the laminate 55 to be formed, the outer surface of the conductor layer 45, and the inner peripheral surface of the via 47, the inner layer wiring pattern 15 and the wiring layer to be the outer layer wiring pattern 40 are electrically connected. (See FIG. 3 (c)). That is, the power supply roller 105 is not directly brought into contact with the conductor layer 45, but the power is supplied to the conductor layer 45 through the exposed conductor portion 20, so that the conductor layer 45 is damaged or contaminated. This can be prevented, and the inner layer wiring pattern 15 and the wiring layer to be the outer layer wiring pattern 40 can be electrically and reliably connected, and the occurrence of defects during pattern formation can be suppressed.

In the above electroplating step, the current density at the time of supplying power is set to 0.1 to 50 A / dm ² , and in particular, it is set to 0.5 to 10 A / dm ² to prevent so-called bumps and roughness. Good plating finish. At this time, as described above, if the total thickness of the conductor layer 45 and the plated conductor layer 50 is set to approximately 20 μm or less, the influence of side etching can be suppressed during the etching described later. It can be formed easily. In particular, when a total thickness of the conductor layer 45 and the plated conductor layer 50 is set to approximately 10 μm or less by using an ultrathin copper foil of 0.5 to 3 μm for the conductor layer 45, it is easy to form fine wiring with a pitch of 40 μm or less. In the electrolytic plating solution, anode balls made of phosphorous copper may be installed at opposite positions on both sides, and copper ions may be supplied together with the anode current. Also in this step, the laminated bodies 55 and 55 laminated on both the front and back surfaces of the inner layer circuit board 10 are processed at the same time (see FIG. 8).

  Next, as shown in FIG. 4A, the outer layer alignment is performed with respect to the outer surfaces of the plated conductor layers 50 and 50 formed by the electrolytic plating process of the laminates 55 and 55 on both the front and back surfaces of the inner circuit board 10. The resist layers 60 and 60 are laminated without covering the marks 57 and 57, respectively. The resist layer 60 is necessary for forming the outer layer wiring pattern 40, and generally a photoresist is used. Photoresist typically has a liquid coating and drying, and a dry film type may be laminated. In general, the former has many positive types and the latter has many negative types. The dry film type resist is particularly suitable because the formation process is easy and the protection of the via 47 is reliable. The dry film resist is generally wound in a roll shape with one surface covered with a protective film and the other surface covered with a carrier protective film. And while peeling off a protective film with the roll part of a roll laminator, the peeled side is piled up on the surface of each plating conductor layer 50 and 50, and it pastes applying appropriate temperature and pressure. Here, the inside of the via 47 is protected by so-called tenting covering the periphery of the via 47.

  After laminating the resist layer 60 as described above, the photomask on which the target conductor pattern is drawn is aligned with reference to the outer layer alignment marks 57 and 57 formed on the laminate 55 that forms the outer layer, For example, the conductor pattern is transferred to the resist layer 60 by exposure with a projection exposure machine or a contact exposure machine using a high-pressure mercury lamp as a light source. For example, when using a negative dry film resist, the photomask of the portion where the conductor pattern is formed is drawn so as to transmit light, and the conductor is applied to the resist layer 60 by irradiating an appropriate exposure amount. The pattern is exposed. Then, the protective carrier film of the photoresist is peeled off and, for example, a sodium carbonate aqueous solution is sprayed and developed to remove the unnecessary resist layer 60. As shown in FIG. Only the resist layer 60 having the conductor pattern to be left is left. In the case of a negative photoresist, the resist layer 60 is removed from the unexposed portion, that is, the portion where no pattern is formed, to obtain the target resist layer 60.

  At this time, exposure is not performed using a photomask with the inner layer alignment mark 22 provided on the inner circuit board 10 as a reference, but is developed with reference to the outer layer alignment mark 57 provided on the stacked body 55 forming the outer layer. Therefore, it is less likely to be affected by the difference in expansion and contraction of the base material between the portion where the outer layer laminate 55 is present and the portion where the outer layer laminate 55 is not present due to an intermediate process or storage environment, rather than using the inner layer alignment mark 22. Can be improved.

  After the resist layer 60 is formed into a target conductor pattern in the above process, as shown in FIG. 5A, the resist layer 60 is formed on the inner circuit board 10 and the laminated bodies 55 and 55 laminated on both the front and back surfaces. Etching is performed to remove the unnecessary plated conductor layer 50 and conductor layer 45. That is, the plated conductor layer 50 and the conductor layer 45 other than the plated conductor layer 50 and the conductor layer 45 covered with the resist layer 60 are removed. This etching is performed by, for example, spraying an etching solution typified by a ferric chloride solution or immersing it in the etching solution to remove unnecessary plating conductor layer 50 and conductor layer 45, As a result, as shown in FIG. 5A, outer layer wiring patterns 40 and 40 composed of the conductor layer 45 and the plated conductor layer 50 are formed.

  After forming the desired outer layer wiring pattern 40 in the above process, as shown in FIG. 5B, the resist layer 60 used as an etching mask is removed with a strong alkaline stripping solution such as a sodium hydroxide solution, for example. To do. This resist removal is performed by dipping in a stripping solution or spraying. Although it is possible to use an organic solvent system as the stripping solution, an inorganic alkaline aqueous solution is desirable because measures against vapor and environmental measures are required. In addition, when a positive resist is used, it can be reliably peeled off by irradiating with ultraviolet rays prior to the peeling treatment.

  As described above, in this embodiment, the outer layer wiring pattern 40 is formed by the subtractive method, but the outer layer wiring pattern 40 may be formed by semi-additive. That is, after the resist layer 60 is formed in a portion where the outer layer wiring pattern 40 is not desired to be formed, electrolytic plating is performed on the portion where the conductor pattern in which the resist layer 60 is not formed is formed, so that the plated conductor layer 50 is formed. In this method, a desired outer layer wiring pattern 40 is formed. In this case, after the conducting step described above, the resist layer formation, the exposure step, and the development step are performed in the same manner as the above steps. Thereafter, in the electrolytic plating step, the plating conductor layer 50 is formed, and the outer layer wiring pattern portion and the plating conductor layer 50 inside the via are formed at the same time, and the inner layer wiring pattern 15 of the inner layer circuit board 10 is formed via the via 47. The outer wiring pattern 40 is electrically connected. Of course, in the exposure process, alignment is performed with reference to the outer layer alignment mark. And after performing the said resist peeling process, the exposed unnecessary conductor layer 45 is removed by flash etching, and the outer layer wiring pattern 40 is formed. Here, flash etching can be performed by spraying or dipping a weak etching solution represented by, for example, sulfuric acid hydrogen peroxide solution, persulfate, or a thin aqueous ferric chloride solution, and these solutions are suitable additives. There are a number of products that are added to the market, and an appropriate solution may be selected and used.

  As described above, as shown in FIG. 5B, after removing the resist layer 60 from the target outer layer wiring pattern 40, the outer layer insulating layer 30 of the inner layer circuit board 10 and the peripheral portions of the conductor layer 45 protrude. A multilayer wiring board 1 having a four-layer structure shown in FIG. 1 can be manufactured by appropriately cutting and removing portions and parts unnecessary for products.

  In addition, as said process, you may punch to a product shape using a metal mold | die, and you may cut | disconnect by laser processing. Further, here, the outer shape processing is performed immediately after the formation of the four-layer structure, but it may be cut when actually used, after the pattern protective layer formation or after electrode plating such as nickel gold plating or tin plating, Furthermore, it may be cut after mounting the components, and may be cut at a time convenient for mounting. In particular, in roll-to-roll conveyance, after mounting a component such as an IC chip, it is also possible to mount a chip protection member and cut it into individual pieces that can be used as a component.

  After forming the outer layer circuit board on the inner layer circuit board 10 as described above, the outer layer insulating layer 30 is again laminated on the outer layer circuit board via the adhesive layer 25, and the same method as above is performed. By repeating, it is also possible to stack two or more outer circuit boards. Even when a plurality of outer layer circuit boards are formed as described above, the outer layer alignment mark 57 is formed when the via 47 is formed in the outer layer stacked body 55 with the inner layer alignment mark 22 as a reference, and the outer layer alignment mark 57 is used as a reference. Thus, by forming the outer layer wiring pattern 40, the pattern accuracy of the outer layer wiring pattern 40 of each outer layer circuit board can be improved.

  Alternatively, the outer layer circuit board and the outer layer alignment mark formed on the inner layer circuit board 10 are used as the intermediate outer layer circuit board and the intermediate outer layer alignment mark, and the outer layer insulating board is laminated in the same manner as described above, and then formed on the intermediate outer circuit board. Forming a hole for a via in the outer insulating substrate based on the intermediate outer layer alignment mark and forming a hole for the outer layer alignment mark, and forming an outer layer wiring pattern on the basis of the outer layer alignment mark composed of the hole. Can be formed. In particular, the intermediate outer layer alignment mark is a reference alignment mark when forming the intermediate outer layer wiring pattern, an alignment mark formed simultaneously with the reference alignment mark when forming the intermediate outer layer wiring pattern, or an intermediate mark If the alignment mark is formed at the same time as the outer layer wiring pattern, it is possible to accurately form the positional relationship with the pattern of the adjacent layer, and the lower layer pattern such as a high frequency wiring layer or a wiring layer that requires high density in particular. This is advantageous in the formation of circuit boards where positional relationships are important.

  10 to 14 show another embodiment of the method for manufacturing a multilayer wiring board according to the present invention. Note that substantially the same parts as those in the manufacturing method of the multilayer wiring board of the above-described embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 10, in the multilayer wiring board 1a manufactured according to this embodiment, the conductor layer 45 is not previously laminated on the surface of the outer insulating layer 30, and the outer layer is formed in the conductive process for via conduction. Unlike the multilayer wiring board 1 manufactured according to the above embodiment, the surface of the insulating layer 30 is also made conductive at the same time to form a conductor layer composed of the plated conductor layer 50, which forms the outer layer wiring pattern 40. Yes.

  FIGS. 11 to 14 show the manufacturing method in the order of steps, but the steps are almost the same as the manufacturing method described above. Explaining in the order of processes, first, as shown in FIG. 11A, the inner layer circuit board 10 in which inner layer wiring patterns 15 and 15 electrically connected via the vias 17 are formed on both the front and back surfaces of the inner layer insulating substrate 11. As shown in FIG. 11B, outer insulating layers 30 and 30 each having an adhesive layer 25 attached as a bonding sheet are disposed on the front and back surfaces of the sheet.

Examples of the adhesive layer 25 and the outer insulating layer 30 include, for example,
1) a base material in which an adhesive layer 25 and an outer insulating layer 30 are laminated in advance;
2) The adhesive layer 25 and the outer insulating layer 30 are formed as separate films,
3) The adhesive layer 25 is provided on the inner layer circuit board 10 in advance, and the outer insulating layer 30 is laminated on the adhesive layer 25;
4) It is possible to use an adhesive resin that serves as the adhesive layer 25 and the outer insulating layer 30 in the form of a sheet.

  In the above state, as shown in FIG. 11C, the inner layer circuit is formed by sandwiching the inner layer wiring patterns 15 and 15 of the inner layer circuit board 10 and sandwiching the outer layer insulating layers 30 and 30 and applying pressure. Outer insulating layers 30 and 30 are laminated on both the front and back surfaces of the substrate 10 via adhesive layers 25 and 25.

  After the above process, as shown in FIG. 12A, a via 47 for electrical connection is formed by a laser or the like using the inner layer alignment mark 22 as a reference. At this time, the outer layer alignment mark 57 is formed simultaneously with the formation of the via 47.

  Thereafter, at least the inside of the via 47 is cleaned chemically or physically preferably by physical cleaning. In this embodiment, since the conductor layer 45 is not formed in advance as compared with the previous embodiment, the via 47 can be formed with relatively weak energy, and in particular, in the outer insulating layer 30 and the adhesive layer 25. In the case where there is no reinforcement with an inorganic material such as glass fiber, processing can be performed with particularly weak energy. In this case, since the processing residue in the via 47 is small and the adhesiveness is weak, the surface of the outer insulating layer 30 is subjected to irradiation with deep ultraviolet light of 250 nm or less typified by excimer light or physical cleaning by a plasma processing method. It is preferably employed because it causes less damage. The inside of the outer layer alignment mark 57 does not necessarily need to be cleaned, but may be cleaned, and may be cleaned when it is particularly desired to reduce the influence of changes in shape due to deposits.

  After the via 47 is cleaned as described above, a conduction process according to the above-described invention is performed as a pre-process for performing electrolytic plating. That is, as shown in FIG. 12B, the conductive layer is formed on the surface of the outer insulating layer 30, the outer peripheral surface of the outer insulating layer 30 and the adhesive layer 25, and the inner peripheral surface of each via 47 by electroless metal plating or the like. 52 is generated, and each conductive layer 52 is connected to the exposed conductor portion 20 via the conductive layer 52 on the outer peripheral surface of the outer layer base material. Here, unlike the above-described invention, it is necessary to make the surface of the outer insulating layer 30 conductive. Therefore, a conductive treatment method capable of obtaining high conductivity such as electroless metal plating is desirable. Further, the inner peripheral surface of the alignment mark 57 and the inner peripheral surface of the inner layer alignment mark 22 may be formed with a conductive layer or not with any protective means.

  Various known processes such as nickel and copper can be applied to the above electroless metal plating. However, after electroless nickel plating or electroless metal oxide plating as a barrier layer or buffer layer is performed, no process is performed. It is preferable to perform electrolytic copper plating since the adhesion to the outer insulating layer 30 can be increased and the adhesion can be further maintained. Electroless copper plating includes a method of reducing and precipitating copper ions by adding a catalyst. When a metal such as nickel is used for the buffer layer, replacement copper plating that replaces the metal surface with copper can be used. . In particular, when a ceramic-modified or pseudo-ceramic-modified polyimide film is used on the surface of the outer insulating layer 30, the method of performing electroless copper plating following electroless metal oxide plating or electroless nickel plating is an adhesive property. It is particularly preferable from the standpoint of holding and insulation reliability.

The method of performing electroless metal plating on the pseudo-ceramic-modified polyimide film is, for example, the method disclosed in JP-A-2005-225228. Specifically, for example, as a degreasing / surface conditioning step, for example, with a surface conditioning agent Immersion treatment at 25-80 ° C. for 15 seconds-30 minutes,
2) As the catalyst application step, for example, a sensitizer such as 1 to 50 g / L of a water-soluble stannous salt such as tin chloride, 5 to 100 mL of an acid such as hydrochloric acid, and a solution having a pH of 1 to 5 is used. Containing 0.01 to 1 g / L of a water-soluble Pd salt such as Pd chloride, 0.01 to 1 mL / L of hydrochloric acid or the like, and 10 to 10% of a palladium activation solution having a pH of 1 to 5 Immerse at 50 ° C. for 5 seconds to 5 minutes, or / and soak in water-activated Ag salt (silver nitrate, etc.) 0.1-2 g / L, pH 5-8 silver activation solution at 10-50 ° C. for 5 seconds to 5 minutes. Catalyst,
3) As a base treatment layer forming step for electroless plating, a process containing 0.001 to 5 mol / L of zinc ions (such as zinc nitrate) and 0.00001 to 0.1 mol / L of indium ions (such as indium nitrate), respectively. Process by immersing in liquid at 50 to 90 ° C. for 1 minute or more to form a zinc-containing indium oxide underlayer,
Thereafter, a conductive layer is formed by a general electroless copper plating process. Specifically, as a catalyst application process, for example, the concentration of a water-soluble metal salt such as a water-soluble Pd salt (such as Pd chloride) is 0. In contact with an aqueous solution of 01 to 1 g / L, pH 1 to 5 at 10 to 80 ° C. for 5 seconds to 5 minutes by dipping, spraying or coating,
5) As an electroless metal plating step, for example, a water-soluble metal salt such as copper sulfate 0.01 to 0.5 mol / L, a reducing agent 0.1 to 1 mol / L such as formaldehyde, a complexing agent such as EDTA 0. Electroless metal plating is applied to the pseudo-ceramic modified polyimide film by immersing it in a solution containing 01-1 mol / L and pH 9-14 at 10-70 ° C. for 5-60 minutes. .

  After the above process, as shown in FIG. 12 (b), the exposed conductor portions 20 projecting from the peripheral edge portions on the left and right sides of the adhesive layer 25 and the outer insulating layer 30 by the power feeding means composed of a pair of upper and lower power feeding rollers 105, 105. Each power supply roller 105 is brought into contact with each exposed conductor portion 20 and electricity is supplied through the power supply roller 105. Then, through the conductive layer 52 on the outer peripheral surface of the outer layer in contact with the exposed conductor portion 20, the conductive layer formed on the surface of the outer insulating layer 30 and the inner peripheral surface of each via 47, the inner layer conductor serving as the via bottom A cathode-side voltage is applied to the exposed portion, and copper ions in the plating bath layer 103 adhere to each surface to form the plating conductor layer 50 (see FIG. 12C).

  After the above steps, as shown in FIG. 13A, a resist layer 60 is laminated on the plated conductor layer 50, the photomask is aligned with reference to the outer layer alignment mark 57, and the target pattern is exposed. Thereafter, as shown in FIG. 13B, the unnecessary resist layer 60 is developed and removed. After that step, as shown in FIG. 14A, the unnecessary plated conductor layer 50 and conductive layer 52 are removed by etching to form a target outer layer wiring pattern 40. Further, as shown in FIG. 14B, the resist layer 60 used as an etching mask is removed with a strong alkaline stripping solution, and unnecessary portions of the inner circuit board 10 are cut and removed, thereby removing the resist layer 60 shown in FIG. The multilayer wiring board 1a shown can be manufactured.

  Here, the outer layer wiring pattern 40 is formed by the subtractive method, but, of course, the outer layer wiring pattern 40 may be formed by the semi-additive method as described above. In this case, after the conductive layer 52 is formed by the above-described electroless metal plating or the like, the resist layer formation, the exposure process, and the development process are performed in the same manner as the above process. Thereafter, in the electrolytic plating step, the plating conductor layer 50 is formed, and the outer layer wiring pattern portion and the plating conductor layer 50 inside the via are formed at the same time, and the inner layer wiring pattern 15 of the inner layer circuit board 10 is formed via the via 47. The outer wiring pattern 40 is electrically connected. Of course, in the exposure process, alignment is performed with reference to the outer layer alignment mark. And after performing the said resist peeling process, the exposed unnecessary conduction | electrical_connection layer 52 is removed by flash etching, and the outer layer wiring pattern 40 is formed.

  Also in this embodiment, when forming the via 47 on the outer insulating layer 30 with reference to the inner alignment mark 22 formed on the inner circuit board 10, the outer alignment mark 57 is formed at the same time. Since the outer layer wiring pattern 40 is formed on the basis of the above, the outer layer wiring pattern is less affected by the expansion / contraction difference of the base material between the portion where the outer layer laminate 55 is present and the portion where the outer layer laminated body 55 is not present due to an intermediate process or storage environment. The position accuracy of 40 can be improved.

1 is a schematic cross-sectional view of a multilayer wiring board manufactured by a method for manufacturing a multilayer wiring board according to an embodiment of the present invention. It is a schematic structure sectional view showing the first process of the manufacturing method of the multilayer wiring board. FIG. 3 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 2 in the method for manufacturing the multilayer wiring board. FIG. 4 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 3 in the method for manufacturing the multilayer wiring board. FIG. 5 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 4 in the method for manufacturing the multilayer wiring board. It is a top view in the manufacturing process of the inner layer circuit board in the manufacturing method of the multilayer wiring board. FIG. 6 is a plan view of a state in which an outer layer stack is stacked on an inner circuit board and vias and outer layer alignment marks are formed in the same multilayer wiring board manufacturing method. It is principal part sectional drawing of the manufacturing apparatus used for the manufacturing method of the same multilayer wiring board. It is a schematic perspective view of the manufacturing apparatus used for the manufacturing method of the multilayer wiring board. FIG. 6 is a schematic cross-sectional view of a multilayer wiring board manufactured by a method for manufacturing a multilayer wiring board according to another embodiment of the present invention. It is a schematic structure sectional view showing the first process of the manufacturing method of the multilayer wiring board. FIG. 12 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 11 in the method for manufacturing the multilayer wiring board. FIG. 13 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 12 in the method for manufacturing the multilayer wiring board. FIG. 14 is a schematic sectional view showing a step subsequent to the step shown in FIG. 13 in the method for manufacturing the multilayer wiring board.

Explanation of symbols

1, 1a Multilayer wiring board 10 Inner layer circuit board 11 Inner layer insulating substrate 13 Conductor wiring 15 Inner layer wiring pattern 17 Via 18 Connection part 20 Exposed conductor parts 22, 26, 27 Inner layer alignment mark 25 Adhesive layer 30 Outer layer insulating layer 40 Outer layer wiring pattern 45 Conductor layer 47 Via 50 Plating conductor layer 52 Conductive layer 55 Laminate 57 Outer alignment mark 60 Resist layer 105 Feed roller

Claims (5)

  An inner layer circuit board having an inner layer wiring pattern formed on at least one side of the inner layer insulating substrate; and an outer layer circuit board having an outer layer wiring pattern formed on an outer surface of the outer layer insulating layer with respect to the inner layer insulating substrate. In the method of manufacturing a multilayer wiring board in which one or more outer layer circuit boards are laminated on at least one side of the inner layer circuit board by a build-up method, the inner layer circuit board or an intermediate layer laminated on the inner layer circuit board After laminating the outer layer insulating layer on the outer layer circuit board, via holes are formed in the outer layer insulating layer based on alignment marks formed on the inner layer circuit board or the intermediate outer layer circuit board, and the outer layer An alignment mark hole is formed, and an outer layer wiring pattern is formed on the outer insulating layer with reference to the outer layer alignment mark including the hole. Method for manufacturing a multilayer wiring board, characterized in that.   The alignment mark formed on the inner circuit board or the intermediate outer circuit board is an alignment mark used as a reference when forming a wiring pattern on the circuit board, or used as a reference when forming a wiring pattern on the circuit board. 2. The method of manufacturing a multilayer wiring board according to claim 1, wherein the method is an alignment mark formed simultaneously with the alignment mark or an alignment mark formed simultaneously with the wiring pattern of the circuit board.   The alignment mark formed on the inner layer circuit board or the intermediate outer layer circuit board is formed on a portion of the circuit board that extends outward from an edge of the outer layer insulating layer. A method for manufacturing a multilayer wiring board.   The method for manufacturing a multilayer wiring board according to claim 1, wherein after forming the via hole and the outer layer alignment hole, the inner wall of each hole is cleaned by physical cleaning.   Formation of an outer layer wiring pattern based on the outer layer alignment mark is performed by patterning with a photoresist by exposing and developing using a photomask aligned with the outer layer alignment mark as a reference. The manufacturing method of the multilayer wiring board as described in any one of Claims 1-4 performed by forming.

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