JP2009076907A - Stressor for engineered strain on channel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stressor for engineered strain on a channel and a forming method thereof. <P>SOLUTION: A semiconductor substrate has recesses filled with heteroepitaxial silicon-containing material with different portions having different impurity concentrations. Strained layers can fill recessed source/drain regions in a graded, bottom-up fashion. Layers can also line recess sidewalls with one concentration of strain-inducing impurity and fill the remainder to the recess with a lower concentration of the impurity. In the latter case, the sidewall liner can be tapered. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates generally to the deposition of silicon-containing materials in semiconductor processing, and more specifically to epitaxial deposition of silicon-containing materials in recessed source and drain regions of a semiconductor substrate.

  In forming an integrated circuit, an epitaxial layer is often desired at a selected location, such as on an active region between isolation regions, or more specifically on defined source and drain regions. Non-epitaxial materials that can be amorphous or polycrystalline can be selectively removed from the isolation region after deposition, but typically provide chemical vapor deposition (CVD) and etching chemistry at the same time, and provide isolation It is believed that it is more efficient to match the conditions so that a zero net deposition on the area and a net epitaxial deposition on the exposed semiconductor window occur. This process, known as selective epitaxial CVD, takes advantage of the slow nucleation of typical semiconductor deposition processes on insulators such as silicon oxide or silicon nitride. Such selective epitaxial CVD further utilizes the naturally greater sensitivity of amorphous and polycrystalline materials to etchants as compared to the sensitivity of epitaxial layers.

  Examples of many situations where selective epitaxial formation of semiconductor layers is desirable include several schemes that generate strain. The electrical properties of semiconductor materials such as silicon, silicon doped with carbon, germanium, and silicon-germanium alloys are affected by the degree of strain of the material. For example, semiconductor materials may exhibit increased electron mobility under tensile strain conditions that are particularly desirable for NMOS devices, and increased hole mobility under compressive strain conditions that are particularly desirable for PMOS devices. is there. Methods for enhancing the performance of semiconductor materials are of considerable interest and potential application for various semiconductor process applications. Semiconductor processing is typically used in the manufacture of integrated circuits, which in particular involve strict quality requirements, and in various other fields. For example, semiconductor process technology is also used in the manufacture of flat panel displays using various technologies and in the manufacture of microelectromechanical systems (MEMS).

  Many approaches that cause strain in silicon-containing and germanium-containing materials have focused on exploiting the difference in lattice constants between various crystalline materials. For example, the lattice constant of crystalline germanium is 5.65Å, the lattice constant of crystalline silicon is 5.431Å, and the lattice constant of diamond carbon is 3.567Å. Heteroepitaxy involves depositing a thin layer of a particular crystalline material on a different crystalline material so that the formed film takes in the lattice constant of the underlying crystalline material. For example, using this approach, a strained silicon-germanium layer can be formed by heteroepitaxial deposition on a single crystal silicon substrate. Since germanium atoms are slightly larger than silicon atoms and the deposited heteroepitaxial silicon germanium is bound to the lower lattice constant of the underlying silicon, the silicon germanium varies to some extent (as a function of germanium content ) Until compression. Typically, the band gap of the silicon-germanium layer decreases monotonically from 1.12 eV for pure silicon to 0.67 eV for pure germanium with increasing germanium content in the silicon germanium. In another approach, tensile strain is formed in a single crystal silicon film by heteroepitaxially depositing a silicon layer on a relaxed silicon-germanium layer. In this example, the deposited silicon is distorted because the lattice constant of the heteroepitaxially deposited silicon is constrained to the larger lattice constant of the underlying relaxed silicon germanium. Tensile strained channels typically show increased electron mobility. Also, the compressively distorted channel exhibits increased hole mobility.

In these examples, strain is introduced into the single crystal silicon-containing material by replacing silicon atoms with other atoms in the lattice structure. This technique is typically referred to as substitutional doping. For example, because germanium atoms are larger than the silicon atoms that the germanium atoms substitute, the substitution of germanium atoms for some of the silicon atoms in the lattice structure of the single crystal silicon will result in the substitutionally doped single atoms formed. Generate compressive strain in crystalline silicon material. Since the carbon atom is smaller than the silicon atom that the carbon atom substitutes, tensile strain can be introduced into the single crystal silicon by substitution doping using carbon. For further details, see New York 2002, Taylor and Francis, “Silicon-Germanium Carbon Alloy”, pages 59-89, Chapter 3, Provided by Hoyt in “Substitutional carbon incorporation and electrical properties of Si _1-y C _y / Si, Si _1-xy Ge _x C _y / Si heterojunctions”. Here, it is called “Hoyt paper”. However, non-substituted impurities do not cause distortion.

  Similarly, electrical dopants should be substituted into the epitaxial layer for electrical activation. Either the dopant must be incorporated to deposit or the substrate should be annealed to achieve the desired level of substitution and dopant activation. In incorporation of dopants into the lattice structure, in situ doping of impurities or electrical dopants for adjusting the lattice constant is often preferred over ex situ doping followed by annealing. This is because annealing consumes a thermal budget. In practice, however, in situ substitutional doping is complicated by the tendency of dopants to be incorporated non-substituted during deposition. For example, the dopant is assembled not into the silicon atoms in the lattice structure, but into the gaps in the domains or clusters in the silicon. Non-substituted doping complicates, for example, carbon doping of silicon, carbon doping of silicon germanium, and doping of semiconductors with electrically active dopants. As shown in FIG. 3.10 on page 73 of the Hoyt paper, conventional deposition methods are used to produce crystalline silicon having in situ doped substitutional carbon content up to 2.3 atomic percent. Used for. This atomic% corresponds to a lattice spacing of 5.4 mm or more and a tensile stress of less than 1.0 GPa.

  In order to apply a compressive strain or tensile strain to the silicon channel between the source and drain, a silicon-containing alloy can be embedded in the source and drain recess as a “stresser”. For example, strained epitaxial silicon germanium (SiGe) at the source and drain recesses can create compressive strain in the silicon channel and increase hole mobility. Similarly, carbon-doped silicon (Si: C) epitaxial alloys having tensile strain at the source / drain recesses can introduce tensile strain into the channel and improve electron mobility. In general, the strain on the channel is related to the concentration of impurities such as C or Ge. In other words, the higher the Ge or C content, the greater the generated strain.

  According to one aspect of the present invention, a method for selectively forming a semiconductor material is provided. The substrate is provided in a chemical vapor deposition chamber. The substrate includes an insulating surface and a single crystal semiconductor surface. The single crystal semiconductor surface includes a recess. The semiconductor stressor is selectively formed in the recess. The semiconductor stressor is tilted so that the top of the semiconductor stressor in the recess has a greater strain than the bottom and the top extends to the sidewall of the recess.

  According to another aspect of the invention, a method for selectively forming a heteroepitaxial semiconductor material is provided. The semiconductor material is formed on the bottom and sidewall surfaces of the recessed single crystal semiconductor region of the substrate. A portion of the semiconductor material is selectively removed from the sidewall surface of the recessed region while leaving a heteroepitaxial film of the semiconductor material on the bottom surface. Deposition and selective removal is performed so that the heteroepitaxial film of semiconductor material deposited later contains different concentrations of impurities that cause distortion compared to the heteroepitaxial film of semiconductor material deposited earlier. Repeated.

  According to another aspect of the present invention, a method for forming a semiconductor material in a recess is provided. A substrate is provided in which an insulating region and a recess are formed. A liner layer of heteroepitaxial silicon-containing material is formed in the recess. The liner layer includes impurities that cause strain and partially fills the recess. The recess is filled with a filler formed on the liner layer. The filler includes a silicon-containing material having a lower concentration of impurities than the liner layer.

  According to another aspect of the invention, a semiconductor device is provided having a recess in a substrate, a heteroepitaxial liner, a filler, and a transistor channel adjacent to the recess. The heteroepitaxial silicon-containing liner substantially covers all of the recess single crystal sidewall surfaces. The liner contains impurities that change the lattice constant. A filler is formed on the liner and embeds the recess. The filler includes a silicon-containing material having a lower concentration of impurities than the liner.

  According to another aspect of the present invention, a semiconductor substrate having a recess and a transistor channel adjacent to the recess is provided. The recess is filled with a heteroepitaxial stressor material. The upper portion of the stressor material in the recess has a first impurity concentration. Also, the lower portion of the stressor material in the recess has a second impurity concentration. The first impurity concentration is higher than the second impurity concentration. The upper part extends to connect to the recess side wall.

  Exemplary embodiments of the methods and systems disclosed herein are also shown in the accompanying drawings for illustrative purposes only. In the drawings, like reference numerals designate like parts.

  The term “impurity” is used herein to refer to an additive such as germanium or carbon that modifies the semiconductor lattice constant in the case of silicon alone. The produced semiconductor compound is often referred to as an alloy or simply a heteroepitaxial film. “Dopant” can refer to either an impurity such as phosphorus, arsenic, boron, or an electrical dopant. The term “silicon-containing material” and similar terms are used herein to refer to various silicon-containing materials within a wide range. Such silicon-containing materials include, but are not limited to, silicon (including crystalline silicon), carbon-doped silicon (Si: C), silicon-germanium (SiGe), and carbon-doped silicon-germanium ( SiGe: C). As used herein, “carbon doped silicon”, “Si: C”, “silicon germanium”, “SiGe”, “carbon doped silicon germanium”, “SiGe: C” , And similar terms, refer to materials that contain the indicated chemical elements in various proportions, and optionally trace amounts of other elements. For example, “silicon germanium” is a material that includes silicon, germanium, and optionally other elements such as dopants such as carbon and electrically active dopants. Abbreviated terms such as “Si: C” and “SiGe: C” are not themselves stoichiometric chemical formulas, and thus are not limited to materials containing the indicated elements in a particular ratio. Further, terms such as Si: C and SiGe: C exclude the presence of other dopants so that phosphorus and carbon doped silicon materials are included within the terms Si: C and the term Si: C: P, respectively. Not intended to do. Unless stated otherwise herein, the proportion of dopants such as carbon or germanium in a silicon-containing film is expressed as an atomic percentage (atomic%) relative to the total film or subfilm. As will be appreciated, the concentration of impurity dopants (excluding elements such as electrical dopants) such as carbon or germanium in the silicon-containing film is at least about 0.3, as described herein. Atomic%. However, those skilled in the art will appreciate that electrical dopants can cause strain in the film and thus can be included in such films.

  The amount of impurities, such as germanium or carbon, that are substitutionally doped in the silicon-containing material is measured, for example, by X-ray diffraction by measuring the vertical lattice spacing of the doped silicon-containing material and then in the case of SiGe alloys It can be determined by applying the Vegard rule by performing linear interpolation between single crystal silicon and single crystal germanium, or in the case of carbon in a Si: C alloy by applying the Kelires / Berti relationship. Further details on this technique are provided in the Hoyt paper. Secondary ion mass spectrometry (SIMS) can be used to determine the total impurity content in the doped silicon. By subtracting the substitutional impurity content from the total impurity content, it is possible to determine the unsubstituted or interstitial impurity content. The amount of another element that is substitutionally doped with another silicon-containing material can be determined in a similar manner.

  “Substrate”, as the term is used herein, refers to either the workpiece being deposited thereon or the surface exposed to one or more deposition gases. For example, in some embodiments, the substrate is a single crystal silicon wafer, a semiconductor on insulator (SOI) substrate, or an epitaxial silicon surface, a silicon germanium surface, or a III-V material deposited on the wafer. is there. The workpiece is not limited to a wafer, but includes glass, plastic, or another substrate used in semiconductor processes. In the illustrated embodiment, the substrate has already been patterned to have two or more different types of surfaces. In some embodiments, a silicon-containing film is selectively formed on a single crystal semiconductor material while minimizing and more preferably avoiding deposition on adjacent dielectrics or insulators. In another embodiment, the deposition deposits amorphous or polycrystalline material on the adjacent insulator, but epitaxy deposition occurs on the single crystal semiconductor surface. Examples of dielectric or insulator materials include silicon dioxide, silicon nitride, metal oxide, and metal silicates, including those with low dielectric constants such as carbon and fluorine doped silicon oxides.

  The terms "epitaxial", "by epitaxy", "heteroepitaxial", "by heteroepitaxial", and similar terms are used herein to take in or follow the lattice constant of the underlying film or substrate. Is used to refer to the deposition of a crystalline silicon-containing material on a crystalline substrate. Epitaxial deposition is heteroepitaxial if the composition of the deposited film is different from that of the underlying film or substrate. Epitaxial deposition is homoepitaxial if the composition of the deposited film is the same as that of the underlying film or substrate.

  In some applications, the patterned substrate has a first surface having a first surface morphology and a second surface having a second surface morphology. Even if the surface is made from the same element, the surface is considered different if the surface has a different morphology or crystallinity. Amorphous and crystalline states are examples of different morphologies. Polymorphic morphology is a crystalline structure that consists of a messy arrangement of orderly crystals and thus has a moderate order. The atoms in a polycrystal are ordered in individual crystals, but the crystals themselves lack long-range order with respect to each other. Single crystal morphology is a crystalline structure with a high degree of long-range order. An epitaxial film is characterized by an in-plane crystal structure and the same orientation as the typically single crystal substrate on which the film is grown. The atoms in these materials are arranged in a lattice-like structure that lasts for a relatively long distance on an atomic scale. Amorphous morphology results in a low-order amorphous structure because the atoms lack a constant periodic arrangement. Other morphologies include microcrystals and mixtures of amorphous and crystalline materials. Thus, “non-epitaxial” includes amorphous, polycrystalline, microcrystalline, and mixtures thereof. As used herein, “single crystal” or “epitaxial” is used to describe a significantly larger crystal structure with an acceptable number of defects, as commonly used in transistor fabrication. The crystallinity of the film usually decreases continuously from amorphous to polycrystalline to single crystal. Despite the low density of defects, the crystal structure is often considered single crystal or epitaxial. Specific examples of mixed substrates having two or more different types of surfaces, whether due to different morphologies and / or due to different materials, are not meant to be limiting, but include monocrystalline / polycrystalline, monocrystalline, Crystal / amorphous, epitaxial / polycrystalline, epitaxial / amorphous, single crystal / dielectric, epitaxial / dielectric, conductor / dielectric, and semiconductor / dielectric. The method described herein for depositing a silicon-containing film on a mixed substrate having two types of surfaces is also applicable to mixed substrates having three or more different types of surfaces.

Tensile strained silicon-containing materials cause uniaxial tensile strain in the silicon channel adjacent to the recessed source / drain region when grown to a sub-critical thickness in the recessed source / drain region. . Such tensile-strained materials include, but are not limited to, carbon-doped silicon films (Si: C films) and carbon-doped silicon-germanium films (SiGe: C films). This SiGe: C film has a germanium concentration of about 8-10 times the carbon concentration and causes enhanced electron mobility, which is also particularly beneficial for NMOS devices. This eliminates the need to provide a relaxed silicon-germanium buffer layer to support the strained silicon layer. In such applications, the electrically active dopant is incorporated by in situ doping using a dopant source or dopant precursor. Typical n-type dopant sources include arsenic vapors and dopants, hydrides, such as phosphine and arsine. Silyl phosphine, for example _{(H 3 Si) 3-x} PR x, and silyl arsine, for example _{(H 3 Si) 3-x} AsR x is an alternative precursor of phosphorus and arsenic dopants. Here, x is 0, 1, or 2, and Rx is H and / or deuterium (D). Phosphorus and arsenic are particularly useful for doping the source and drain regions of NMOS devices. SbH ₃ and trimethylindium are alternative sources of antimony and indium, respectively. Such dopant precursors are useful in the preparation of films as described below, preferably phosphorous, antimony, indium, and arsenic doped silicon, Si: C, or SiGe: C films and alloys. is there.

When grown to a sub-critical thickness in the recessed source / drain region, the compressively distorted silicon-containing material is uniaxial to the silicon channel adjacent to the recessed source / drain region. It causes compressive strain and provides enhanced hole mobility that is particularly beneficial for PMOS devices. Such compressively distorted materials include, but are not limited to, silicon-germanium films (SiGe films), and carbon-doped silicon / silicon-doped silicon atoms with a germanium concentration of about 8-10 times or more of the carbon concentration. A germanium film (SiGe: C film) is included. In such applications, the electrically active dopant is incorporated by in situ doping using a dopant source or dopant precursor. Typical p-type dopant precursors include diborane (B ₂ H ₆ ) and boron trichloride (BCl ₃ ) for boron doping. Other p-type dopants for Si include Al, Ga, In, and any metal to the left of Si in the Mendeleev element table. Such dopant precursors are useful in the preparation of films as described below, preferably boron-doped silicon, SiGe, or SiGe: C films and alloys.

  There is a limit to the thickness of the SiGe or Si: C film that can be grown in the recessed source and drain regions without having excessive dislocations. The thickness of the film that can be grown is usually inversely proportional to the impurity content. Currently, SiGe alloys of uniform composition and thickness in the range of about 10-50 nm are acceptable for SiGe having less than about 40 atomic percent Ge and Si: C having less than about 3 atomic percent C It can be formed with a small amount of dislocation. Beyond these ranges, the acceptable thickness and growth rate of the film is dramatically reduced as the processing temperature is lowered to suppress dislocation nucleation. For example, typically only a few monolayers of pure Ge can be grown on silicon without dislocations. Beyond this critical thickness, a significant amount of dislocations are created in the film that are detrimental to device performance. The overall high impurity content can lead to dislocations. In the preferred embodiment described herein, the strain is located on the sidewall of the recess adjacent to the transistor channel, thereby reducing the overall impurity content in the stressor while maximizing the effect of the strain.

  A technique for forming a strained film containing a silicon-containing material such as Si: C, SiGe, and SiGe: C on an exposed semiconductor window has been developed. In the illustrated embodiment, a strained film is formed in the recessed source / drain regions to exert stress on adjacent channel regions and is therefore also referred to as a “stresser”. In accordance with a preferred embodiment, the strained heteroepitaxial semiconductor material is formed into a recessed source to increase the strain induced on the adjacent transistor channel region compared to the overall strain induced in the substrate. / Deposited in the drain region. The stressor slopes because the stressor has a different composition in different regions within the recess. However, this gradient can be continuous or stepped in two or more discrete films.

Inclined stressor with maximum strain on surface extending to recess sidewall FIGS. 1-5D illustrate one embodiment. In this embodiment, the heteroepitaxial stressor material is deposited in a bottom-up manner and is tilted so that the maximum strain is on the top surface and extends to the recess sidewalls. Such deposition can be performed, for example, by (a) forming a Si: C film in the recess by blanket growth, and (b) selecting a semiconductor material from the recess sidewall to leave a heteroepitaxial film at the bottom of the recess. This can be achieved by selective etching. Step (b) can simultaneously etch the non-epitaxial semiconductor material on the insulator. Steps (a) and (b) are optionally repeated periodically at different impurity levels until the target epitaxial film thickness on the recessed source / drain regions is achieved, thus different levels of strain are Repeated periodically. In alternative embodiments, another deposition technique can be used to form a silicon-containing material that is tilted perpendicular to the substrate recess.

  Recessed source / drain regions can be formed by dry etching with subsequent HF cleaning and in situ annealing. In embodiments where dry etching is used, a selectively deposited thin silicon seed film of about 1 to 3 nm facilitates reducing etch damage. The seed film further facilitates compensation for damage caused by previous dopant implantation steps. In one example embodiment, such a seed film may be selectively deposited using a simultaneous supply of HCl and silane dichloride at a deposition temperature of about 700-800 ° C.

  A periodic blanket deposition and etching process according to some embodiments is shown in the flow chart provided in FIG. 1 and is a schematic representation of the partially formed semiconductor structure shown in FIGS. Is shown in In the following, the contextual conditions of the embodiments relating to tensile strained Si: C deposition by a specific periodic process will be discussed, but it should be understood that the recess bottom-up, gradient embedding described herein is Can be used to form epitaxial films of other strained materials that are formed in a bottom-up manner by other techniques. The Si: C embodiment preferably includes substitutional carbon in the range of about 0.1-4 atomic percent, more preferably about 1-3 atomic percent, with the highest strain near the substrate surface. Tilted to have. A preferred periodic process is to selectively form Si: C at a higher carbon concentration for a given film quality than to flow simultaneous etchants and precursors for conventional selective deposition. And allows the highest strained portion of the stressor to be located at the top of the recess and extend to the recess wall adjacent to the channel. This will be well understood by those skilled in the art. Of course, in some implementations, the recess wall may be defined by an epitaxial layer formed to line the recess (meaning to cover the inside) after the recess is etched. it can. The techniques described herein can also be used to deposit other epitaxial films such as SiGe and SiGe: C in the recessed source / drain regions.

  In particular, FIG. 1 shows that in the operational block 10 a substrate with a recessed source / drain region is placed in the processing chamber. As shown in the operation block 20, the semiconductor alloy layer is formed conformally on the substrate. In one embodiment, this conformal deposition is a blanket that leaves an amorphous or polycrystalline material on any insulator region of the substrate and an epitaxial deposit on the bottom and sidewalls of the source / drain regions. Film formation. After conformal deposition, all regions of amorphous or polycrystalline material and sidewall epitaxial material are selectively etched, as shown in operation block 30. After selective etching, as shown in operation block 40, it is determined whether the target thickness of the epitaxial film in the recessed source / drain regions has been achieved. If the target thickness has been achieved, the process ends as indicated in operation block 45. If the target thickness has not been achieved, the process is continued periodically by incrementing or increasing the concentration of impurities that cause strain, such as carbon, as shown in operation block 50. This increased concentration is used for subsequent conformal deposition of the semiconductor alloy layer shown in operation block 20. Subsequent conformal deposition using the increased impurity concentration is followed by selective etching of amorphous or polycrystalline and sidewall epitaxial materials, as shown in operation block 30. After this deposition and etching step, the thickness of the epitaxial film in the recessed source / drain is evaluated to determine whether the target thickness has been achieved, as shown in operation block 40. This periodic process is repeated until the target thickness is achieved. In order to achieve an inclined stressor, the operating blocks 20-50 are performed for at least two cycles.

  FIG. 2 provides a schematic illustration of an exemplary substrate that includes a patterned insulator 110 formed in a semiconductor substrate 100, such as a silicon wafer. The illustrated insulator 110 in the form of shallow trench isolation (STI) buried in oxide defines a device isolation region 112 and is recessed as shown on either side of the gate electrode 115 structure. Adjacent to the source / drain region 114. Note that the gate electrode 115 overlaps the channel region 117 of the substrate. Channel 117, source and drain regions 114 together define the active region of the transistor. The active region is usually surrounded by the element isolation region 112 to prevent crosstalk with adjacent devices. In another configuration, the composite transistor may be surrounded by the element isolation region. In one example, the top surface of the gate structure 115 can be covered with a dielectric material. Thereafter, this surface acts in the same manner as the field region 110 with respect to the film formation thereon, and the film formation on the upper surface of the gate has the same degree of crystallinity as film formation on the field region. In the case where the gate 115 is not covered with a dielectric material, a polycrystalline material grows on the surface of the gate. The polycrystalline material can then be removed by in situ etching of the polycrystalline material. However, different condition sets such as pressure, gas flow, etc. may be applied to ensure removal of material from region 110.

  In the following, embodiments with specific examples of carbon-doped silicon (Si: C) for NMOS applications are described. As schematically shown in FIG. 3, blanket Si: C layers 120, 125, 130 are preferably formed on a mixed substrate by using trisilane as the silicon precursor and then flowing a carbon precursor. . This includes Si: C predominantly amorphous or polycrystalline or non-epitaxial deposition 120 on isolation regions 112, Si: C lower epitaxial deposition 125 lined with recessed source / drain regions 114, and sidewalls. Epitaxial deposition 130 is provided. Note that “Blanket deposition” means that a net deposition is made on both the amorphous insulator 110 and the single crystal source / drain regions 114 during the deposition phase. The absence of an etchant or halide is preferred in the blanket deposition process, in which case the deposition can be considered “non-selective”, but a certain amount of etchant is deposited on various areas. It may be desirable to match the thickness ratio. The deposition process where such a small amount of etchant is desired can be a blanket while being partially selective. This is because each deposition step has a final deposition on both the insulator 110 and the single crystal region 114.

  According to one embodiment, the regions of amorphous or polycrystalline deposition 120 and sidewall epitaxial deposition 130 are then selectively etched, thus forming the structure schematically shown in FIG. In another embodiment, the deposition on the sidewall region can be a polycrystalline or amorphous material. Some of the Si: C deposited by epitaxy is removed from the lower epitaxial layer 125 in the recessed source / drain regions 114 during the selective etch, but at least some of the lower epitaxial layer 125 is removed. Remains. Due to the difference in growth rates on the two surfaces, the sidewall epitaxial layer 130 tends to grow on different crystal planes and be more defective than the lower epitaxial layer 125. One skilled in the art will fully understand the following. That is, the lattice spacing in the vertical sidewall epitaxial layer 130 is smaller than that in the lower epitaxial layer 125. It results in a difference in growth rate between the two surfaces. Thus, the sidewall epitaxial layer 130 is more easily removed along with the non-epitaxial material 120. Thus, each cycle of the process can be adjusted to achieve a large bottom-up fill in recess 114. As will be appreciated from the discussion of FIG. 1, each cycle includes a blanket conformal deposition 20 and a selective etch 30 from the recess sidewall.

As will be discussed in more detail below, in an exemplary embodiment, the gas phase etch chemical is preferably a halide, such as fluorine, bromine or chlorine containing gas phase compounds, and particularly HCl or containing chlorine source such as Cl _2. In some embodiments, the etch chemistry further includes a germanium source, eg, germane such as monogermane (GeH ₄ ), GeCl ₄ , organometallic Ge precursor or solid source Ge. One skilled in the art will recognize that the same etch chemistry is also suitable for SiGe and SiGe: C films.

  After the selective etching process described above with reference to FIG. 4, second blanket Si: C layers 122, 132, 135 are deposited on the mixed substrate, as shown in FIG. 5A. The second blanket Si: C layers 122, 132, and 135 contain carbon at a higher concentration than the first blanket Si: C layers 120 to 130 shown in FIG. According to one embodiment, the carbon concentration of the first blanket Si: C layers 120, 125, 130 is between about 1-1.5 atomic% and the second blanket Si: C layers 122, 132, The carbon concentration of 135 is greater than about 1.5 atomic percent, preferably in the range of about 1.5 to 4 atomic percent. In another embodiment for the growth of SiGe films, the germanium concentration of the first blanket SiGe layers 120, 125, 130 is in the range of 10-20 atomic percent, and preferably about 15 atomic percent. The germanium concentration of the second blanket SiGe layers 122, 132, 135 is in the range of 20-100 atomic percent, and preferably in the range of about 30-60 atomic percent. As shown in FIG. 5A, the second blanket Si: C layers 122, 132, 135 include amorphous or polycrystalline silicon portions 122, sidewall epitaxial portions 132, and recessed bottom portions 135. Thereafter, as shown in FIG. 5B, this second Si: C film 122, 132, and 135 is formed by Si: C non-epitaxial portions on the amorphous insulator 110 in the oxide region 112 and the sidewall epitaxial layer 132. Is selectively etched to remove. In other embodiments, the sidewall deposition is amorphous or polycrystalline. In any case, in this embodiment, the sidewall layer is more easily removed than the bottom epitaxial material.

  As shown in decision block 40 of FIG. 1, a blanket deposition of a Si: C layer having a higher carbon concentration sequentially until the target thickness of the epitaxial Si: C film reaches the recessed source / drain region 114. , And subsequent periodic processes including selective etching. This periodic process is schematically illustrated in FIG. 5A, which illustrates the deposition of a second cycle blanket Si: C film 122, 132, and 135, and the second cycle of amorphous or polycrystalline Si. : C layer 122 and sidewall epitaxial layer 132 are also etched in FIG. 5B, leaving the epitaxial Si: C covering the bottom with increased thickness. Epitaxial Si: C covering the bottom with increasing thickness includes discrete graded films 125 and 135 in recessed source / drain regions 114. FIG. 5C shows the result of a further cycle that leaves the epitaxially buried source / drain regions 114. In FIG. 5C, the top layer 145 of the discrete selectively tilted epitaxial layer is substantially coplanar with the oxide region 110. Although shown as one further cycle, those skilled in the art will recognize that additional cycles may be performed to fill the recessed source / drain regions 114.

  Although FIG. 5C shows three discrete graded films, those skilled in the art will recognize that, in other embodiments, the epitaxially buried source / drains have a top surface that is substantially flush with the oxide region. It will be appreciated that a greater or lesser number of discrete tilted membranes are possible to achieve the region. Of course, in another embodiment, discrete graded epitaxial layers 125, 135, 145 can be selectively formed as high source / drain regions 114. As shown in FIG. 5C, each formed film covers at least a part of the sidewall surface of the recessed region 114. According to another embodiment, the films 125, 135, 145, etc. can form a continuously graded film with a continuously deposited film having progressively higher carbon concentrations. For example, each layer can be tilted as deposited, and / or a subsequent heat treatment can flatten this tilt by diffusion. Whether the tilted film is continuous or stepped, the highest strain in the recessed region 14 is at the top of the recess (almost flush with the surface of the wafer), and Each of the graded epitaxial layers 125, 135, 145, etc. extends to a recess sidewall adjacent to the channel. Thus, even on the sidewalls, the slope extends away from the sidewalls and is primarily vertical rather than horizontal. As noted above, in some configurations, the recess sidewalls are defined by an etching process having an optional recess cleaning or thermal smoothing step. In another configuration, the recess sidewall is defined by a lining layer, such as a thin epitaxial layer. Each deposited film of graded structure has a thickness of about 1-100 nm. According to another embodiment, the thickness of each deposited film is about 3-50 nm. According to another embodiment, the thickness of each deposited film is about 3-5 nm. In some embodiments, each of the graded epitaxial layers has the same thickness. In another embodiment, the graded epitaxial layer has a different relative thickness.

  The selective formation process further includes additional cycles of blanket deposition and selective etching to remove deposited material from the dielectric region and form an optional capping layer 150, as shown in FIG. 5D. be able to. The capping layer 150 may or may not have impurities or electrical dopants. For example, the portion of the high source / drain region 114 that is on the original substrate surface and the channel 117 between the source / drain regions 114 is above the level of the channel 117 and contributes to strain on the channel. Therefore, it can contain no carbon. Thus, the optional capping layer 150 can be formed from Si, SiGe, SiGe: C, or Si: C and can serve to supply additional Si for contact silicidation. . In one embodiment, the capping layer 150 is formed of Si, SiGe, SiGe: C, or Si: C, but the films 125, 135, and 145 can be formed of Si: C. In another embodiment, the capping layer 150 is formed of Si, SiGe, SiGe: C, or Si: C, but the films 125, 135, 145 can be formed of SiGe. In an exemplary embodiment, the formed graded Si: C layer optionally includes an electrically active dopant, particularly a dopant suitable for NMOS devices such as phosphorus or arsenic.

In one embodiment, the substrate temperature is at least the etching step of FIG. 1 to facilitate maintaining a high concentration of substitutional carbon and electrically active dopants while simultaneously minimizing the temperature ramp / stabilization time. At 30, it is preferably kept low, for example in the range of about 350-700 ° C. Using a low temperature for etching further reduces the likelihood that electrically active dopant atoms will be deactivated during etching. For example, etching with Cl ₂ gas advantageously allows the etching temperature to be lowered, thereby facilitating maintenance of substitutional carbon and electrically active dopants. The low temperature during the etching stage allows to roughly match the temperature during the deposition stage, taking advantage of the high dopant incorporation achieved at low temperatures. The etch rate can be determined by including a germanium source such as GeH ₄ , GeCl ₄ , organometallic Ge precursor, and solid source Ge at the etch stage, or flash ramping the temperature at the etch stage. Thus, by improving throughput, these low temperatures can be increased without sacrificing throughput. An isothermal process in which the setpoint temperature remains relatively constant, for example within ± 10 ° C., over multiple cycles improves throughput and minimizes temperature ramping and stabilization times. Similarly, both the blanket deposition and etching steps are preferably isobaric with the pressure setpoint of each other within ± 20 Torr. Isothermal and / or isobaric conditions avoid lamp and stabilization times and promote better throughput.

  As shown in FIG. 1, the two-step process of blanket deposition followed by selective etching is optionally periodic until the target thickness of the epitaxial film that fills the source / drain recess is achieved. Repeated. Typical process parameters for one cycle and stabilization are summarized in Table A below. Table A lists both typical operating points and preferred operating ranges in parentheses. As is apparent from Table A, process conditions such as chamber temperature, chamber pressure, and carrier gas flow rate are preferably substantially similar during the deposition and etching steps, thereby increasing throughput. To. Thus, the following example uses isothermal and isobaric conditions for both stages of a cycle. The other parameters are used for subsequently deposited films with different impurity concentrations. For example, to deposit a layer with a higher impurity concentration, the flow of Si and C precursors may be different, or the chamber temperature may be adjusted.

Table A provides typical process parameters for forming an epitaxial Si: C film in the recessed source / drain regions, as discussed above with respect to FIGS. 1-5D. Using the parameters provided in Table A, it is preferably between about 4-11 nm / min for epitaxial Si: C: P films selectively formed in recessed source / drain regions. More preferably, it is possible to achieve a net growth rate of between about 8-11 nm / min. It is also possible to achieve Si: C: P thin films with up to 3.5% substitutional carbon and a resistivity of about 0.4-2 mΩcm as determined by the application of the Kelires / Berti relationship. is there. It is possible to obtain other film properties by manipulating the film forming conditions. One skilled in the art will understand that deposition conditions are typically adjusted for subsequent deposition.

  In the etching process disclosed herein, epitaxial Si: C etches significantly slower than amorphous or polycrystalline Si: C with an etch selectivity in the range of about 10: 1 to 30: 1 at each etching stage. Is done. Sidewall epitaxial material is also preferentially removed during the etching stage. In a preferred embodiment, the conditions of the periodic deposition and etching steps are such that amorphous growth is achieved in each cycle on the recessed epitaxial source / drain region 114, particularly on the bottom surface of the recess 114, while in each cycle. Adjustments are made to reduce or eliminate net growth on the insulator 110. This periodic process is distinguishable from the conventional selective film formation process in which film formation and etching reaction occur simultaneously.

Tables B and C below list two examples of film formation, etching duration, and resulting film thickness using a recipe similar to the recipe in Table A. The two recipes are tuned differently to adjust both deposition and etch rates by increasing the Si ₃ H ₈ partial pressure and optimizing the etchant partial pressure.

As described above, in another embodiment, instead of the periodic blanket deposition / selective etch process described above, another selective deposition technique is recessed into the recess in a bottom-up buried manner. It may be used to form a stressor.

Retrograde Stressor with Maximum Strain Lining Recess FIG. 6 shows that in its operational block 300, a substrate with a recess is provided. As shown in operation block 310 of FIG. 6, the single crystal surface of the substrate recess is lined by a heteroepitaxial strain liner. After the recess is lined, the lined recess is filled with a material having a reduced strain compared to the strain liner, as shown in operation block 320.

  7 and 8 show an embodiment of the method of FIG. FIG. 7 provides a schematic representation of an exemplary substrate that includes a patterned insulator 210 formed in a semiconductor substrate 200, such as a silicon wafer. The illustrated insulator 210 defines an isolation region 212 in the form of an STI buried with oxide, and a recessed source / drain region 214, shown on either side of the gate electrode 215 structure. Adjacent to. The gate electrode 215 structure overlaps the channel region 217 of the substrate 200. For illustrative purposes, the insulator 210 is shown separated from the recessed source / drain regions 214 such that the entire recessed surface is defined by single crystal silicon. However, as will be appreciated, in other configurations, some recess surfaces may be defined by an insulator material as shown in FIG. A liner layer 225 of heteroepitaxial silicon-containing material, such as SiGe, SiGe: C, and Si: C, may be used to provide a recessed source / recess of substrate 200 that also has an insulator region 210, as shown in FIG. A drain region 214 is formed. The heteroepitaxial liner layer 225 is preferably formed selectively and heteroepitaxy on the single crystal surface of the recessed source / drain region 214.

  According to another embodiment, the heteroepitaxial liner layer 225 is formed on a mixed substrate having an insulator region and a recessed source / drain region, as described above with respect to FIGS. A blanket film of a silicon-containing material such as SiGe: C or Si: C is selectively formed, and the blanket film is selected so that the formed silicon-containing material remains only in the recessed source / drain regions. It can be formed by etching. Those skilled in the art will recognize that the blanket film of silicon-containing material is substantially amorphous, polycrystalline or non-epitaxial material on the isolation region 212 and epitaxial material on the bottom surface of the recessed region 214. You will understand. As shown in FIG. 7, the single crystal sidewalls of the recessed region 214 are also covered by a heteroepitaxial liner layer 225 of silicon-containing material. The epitaxial material on the bottom surface of the recessed region 214 and the epitaxial material on the sidewall together constitute a heteroepitaxial liner layer 225 in the recessed region 214. After selective etching, only the heteroepitaxial liner layer 225 remains in the recessed source / drain region 214.

  As shown in FIG. 7, the heteroepitaxial liner layer 225 lines the recessed region 214 so as to cover all the sidewall surfaces and bottom surfaces of the recessed region 214 where the heteroepitaxial liner layer 225 is recessed. Preferably, the heteroepitaxial liner layer 225 is deposited substantially uniformly on the exposed silicon in the recessed region 214. The heteroepitaxial liner layer 225 of heteroepitaxial silicon-containing material can be formed at a temperature in the range of about 350-1000 ° C, preferably at a temperature in the range of about 400-800 ° C. In another embodiment, the epitaxial silicon-containing material is formed at a temperature in the range of about 400-750 ° C, preferably at a temperature in the range of about 450-650 ° C. According to another embodiment, the heteroepitaxial liner layer 225 may be a graded film having an impurity concentration that causes strain to decrease with distance from the bottom and sides of the recessed region 214. The slope can be discrete or continuous.

  Thereafter, as shown in FIG. 8, the remaining portion of the recessed region 214 is filled with filler 260 until the target thickness on the recessed source / drain region 214 is achieved. Filler 260 includes an epitaxial material having a lower concentration of impurities such as Ge or C. The impurities introduce strain into the heteroepitaxial liner layer 225. According to one embodiment, the filler 260 includes silicon. In the embodiment shown in FIG. 8, the filler 260 embeds a recess between the insulator 210 and the channel region 217 such that the top surface of the filler 260 is substantially coplanar with the top surface of the insulator 210. . However, one skilled in the art will readily appreciate that this target thickness can be lower or higher than the top surface of the insulator 210. Those skilled in the art will recognize that the recessed source / drain regions 214 embedded using the stressor formed by the heteroepitaxial liner 225 and the relaxed strain filler 260 are more than the conventional stressor using a uniform silicon alloy. You will fully understand that it is stable. This is because impurities that cause strain, such as stressor Ge or C, have an overall reduced concentration. This structure still provides the desired high level of strain at the end of the channel 217. For example, for a heteroepitaxial liner layer 225 comprising SiGe, the Ge content is typically 20-50 atomic percent, and the Ge content of filler 260 is preferably about 20 atomic percent or less. . The C content of the Si: C liner is typically 0.5-4 atomic percent, and the C content of the filler 260 is preferably less than about 1 atomic percent and the liner layer 225 Or less of the C content. As shown in FIG. 8, an optional cap layer 250 can be formed on the buried source / drain regions 214, preferably by a selective deposition technique. In one embodiment, the cap layer 250 is formed from Si, SiGe, SiGe: C, or Si: C. The cap layer 250 preferably has a lower impurity concentration than the liner layer of the epitaxial material 225.

FIG. 9 shows that in its operational block 400, a substrate with a recess is provided. As shown in operational block 410, the single crystal surface of the substrate recess is lined by a heteroepitaxial strain liner. After the recess is lined, as shown in operation block 420, redistribution annealing is performed to form facets in the lower corners of the recess. Thereafter, as shown in operational block 430, the recess is embedded with a material having a relaxed strain as compared to the strain liner.

  The liner layer can be annealed to redistribute the epitaxial liner layer material, i.e., to move the material to the corners of the recess sidewalls. Typically, such annealing causes the epitaxial material to taper to have a faceted cross-sectional shape. The annealed epitaxial material is generally wider at the bottom of the recess than at the top. Preferably, the annealed epitaxial material that substantially covers all of the recess sidewall surfaces exerts lateral strain on adjacent transistor channels.

  10 and 11 show the method of FIG. After the liner layer 225 is deposited on the structure shown in FIG. 7, it can be either selective deposition techniques, or periodic blanket deposition / selective etching, or non-selective deposition and patterning. The substrate 200 is annealed by being heated to about 600 to 1100 ° C. In one embodiment, the substrate is annealed at a temperature of about 650-900 ° C. In another embodiment, the annealing temperature is between about 725-775 ° C. One skilled in the art can readily determine an appropriate annealing time, depending on the temperature selected to achieve the desired redistribution. Although the recesses 214 have been shown as fully defined within the semiconductor material such that the wedge-shaped heteroepitaxial material 230 forms a ring, those skilled in the art will have shown for the embodiment of FIGS. In addition, it will be appreciated that one or more sidewall surfaces can be defined by the element isolation material. As noted with respect to the embodiments described above, the sidewalls of the recessed region 214 may be further cleaned or rounded by etching to form the sidewalls, or an additional lining film such as a thin epitaxial layer. (Not shown).

  As a result of the annealing process, silicon and dopant atoms in the liner layer 225 shown in FIG. 7 move, and this material redistribution is caused by the fact that the annealed heteroepitaxial material 230 is faceted as shown in FIG. ) Resulting in having a transverse lateral shape. From a crystallographic point of view, facet heteroepitaxial material 230 corresponds to crystal facets on both sides of channel region 217 under gate electrode 215. As shown in FIG. 10, facet heteroepitaxial material 230 is a film that is substantially tapered along the sidewalls of recessed region 214.

  In addition, this faceted epitaxial material 230 is strained without dislocations but has a higher alloy content than the epitaxial liner 225 of FIG. 7 prior to annealing. As shown, the faceted epitaxial material 230 is located adjacent to the channel 217 under the gate electrode structure 215 and is at least the sidewall of the recess 214 next to the channel, preferably the single crystal sidewall of the recessed region 214. Substantially line or cover all surfaces. Accordingly, the strained facet heteroepitaxial material 230 causes strain in the channel region 217 underlying the gate electrode structure 215.

  In the illustrated embodiment, some of the epitaxial material of the original liner 225 remains on the bottom surface of the recessed region 214 after annealing. As shown in FIG. 10, the epitaxial material of the bottom liner 280 after annealing is thin, has an uneven surface, and is discontinuous with the heteroepitaxial material 230 covering the wedge-shaped sidewalls. Is possible. The bottom coverage discontinuity can reduce the strain at the bottom of the recess without affecting the top of the recess adjacent to the surface of the channel. Although the annealed bottom liner 280 epitaxial material is separated from facet heteroepitaxial material 230 in the illustrated embodiment, it will be appreciated that in other embodiments (not shown), It is possible that the epitaxial material of the bottom liner is not separated from the faceted epitaxial material that covers the sidewall surface. The presence or absence of this separation can be achieved by adjusting the deposition time or by adding a post-epitaxial deposition chemical etch step, eg, an in situ post-epitaxial deposition HCl etch.

  Thereafter, as shown in FIG. 11, the remaining portion of the recessed region 214 is filled with a filler 260. Filler 260 has an impurity concentration that causes a lower strain than facet heteroepitaxial material 230. As shown in FIG. 11, the filler film 260 may be formed so as to be substantially flush with the upper surface of the substrate 200. In another embodiment, the filler film 260 can be lower or higher than the upper surface of the substrate 200. For silicon <100> substrates, the facet angle at the interface between facet heteroepitaxial material 230 and filler 260 is about 25-55 degrees with respect to the horizontal plane [001] at the bottom of recessed region 214. Is in range. According to another embodiment, the facet angle is in the range of about 11-72 degrees. Of course, the interface between the faceted heteroepitaxial material 230 and the filler 260 may have a slight curvature. Also, the stressors 230 and 260 in the recessed region 214 have a higher strain, i.e., a higher impurity concentration, on the sidewalls and a lower strain, i.e., a lower impurity concentration, in the center of the recessed region 214. In general, it has been reversed. In practice, the filler 260 can be formed from Si that contains only electrical dopants for conductivity and no impurities that cause strain. An optional cap layer (not shown) can be formed on the filler 260. FIG. 12 is a photomicrograph showing a faceted SiGe liner layer formed using the method shown in FIG. Filler 260 (FIG. 11) is labeled as “Si Cap” in the micrograph and polysilicon growth is shown on the gate electrode. This indicates that non-selective film formation was used in this example.

  The critical thickness constraint is relaxed because the volume of highly distorted epitaxial silicon-containing material 280 and 230 is dramatically reduced by the use of a thin lining film rather than completely embedding the recess with a very distorted material. And it will be appreciated that substantial gains in strain design and thermal budgets arise. The impurity content of the epitaxial silicon-containing materials 280 and 230 can be adjusted to produce different amounts of strain. The processing temperature can be increased to lead to a significant increase in growth rate.

  While the above detailed description discloses several embodiments of the invention, it is to be understood that this disclosure is illustrative only and does not limit the invention. Of course, the specific configuration and operation may differ from those described above. Moreover, the method described herein can be used in situations other than the manufacture of semiconductor devices.

It is a flowchart which shows the method of selectively forming a strain-processed epitaxial semiconductor film by the bottom-up method in the recessed source / drain area | region of a board | substrate. 1 is a schematic cross-sectional view of a partially formed semiconductor structure that includes recessed source / drain regions formed in a semiconductor substrate. FIG. FIG. 3 is a schematic cross-sectional view of the partially formed semiconductor structure of FIG. 2 after blanket deposition of a carbon impurity doped silicon film including epitaxial deposition on the bottom surface of the recessed source / drain region. . FIG. 4 is a schematic cross-sectional view of the partially formed semiconductor structure of FIG. 3 after performing a selective chemical vapor etching step to remove carbon doped silicon from the insulator and recessed sidewall regions. . FIG. 5 is a schematic cross-sectional view of the partially formed semiconductor structure of FIG. 4 after performing additional cycles of blanket deposition and selective etching to form an increasing strain film in a bottom-up manner. FIG. 5 is a schematic cross-sectional view of the partially formed semiconductor structure of FIG. 4 after performing additional cycles of blanket deposition and selective etching to form an increasing strain film in a bottom-up manner. FIG. 5 is a schematic cross-sectional view of the partially formed semiconductor structure of FIG. 4 after performing additional cycles of blanket deposition and selective etching to form an increasing strain film in a bottom-up manner. FIG. 5 is a schematic cross-sectional view of the partially formed semiconductor structure of FIG. 4 after performing additional cycles of blanket deposition and selective etching to form an increasing strain film in a bottom-up manner. 6 is a flow chart showing a method of forming a strained liner film in a recessed source / drain region of a substrate. The partially formed semiconductor structure of FIG. 2 after forming a liner layer including a silicon-containing film in the recessed region of the mixed substrate surface and filling the recessed region with filler, according to another embodiment FIG. The partially formed semiconductor structure of FIG. 2 after forming a liner layer including a silicon-containing film in the recessed region of the mixed substrate surface and filling the recessed region with filler, according to another embodiment FIG. 6 is a flow chart illustrating a method for forming a faceted strain liner film in a recessed source / drain region of a substrate. FIG. 7 is a schematic cross-sectional view of the partially formed semiconductor structure of FIG. 6 after annealing the liner layer and filling the recessed regions with filler, according to another embodiment. FIG. 7 is a schematic cross-sectional view of the partially formed semiconductor structure of FIG. 6 after annealing the liner layer and filling the recessed regions with filler, according to another embodiment. It is a microscope picture which shows the SiGe liner layer after being annealed.

Claims (52)

Providing a substrate comprising an insulating surface and a single crystal semiconductor surface having a recess in a chemical vapor deposition chamber;
Selectively forming a semiconductor stressor in the recess;
The semiconductor stressor is
The upper portion of the semiconductor stressor in the recess is inclined to have a higher strain than the lower portion;
A method of selectively forming a semiconductor material wherein the upper portion extends to a sidewall of the recess. The method of claim 1, wherein the semiconductor stressor comprises a discrete film. The step of selectively forming the semiconductor stressor comprises:
Blanket depositing a semiconductor material on the insulating surface and the single crystal semiconductor surface of the substrate;
2. Selectively removing non-epitaxial semiconductor material from the insulating surface and selectively removing epitaxial material from the sidewalls of the recess while leaving the epitaxial material at the bottom of the recess. The method described in 1. Further comprising repeating the blanket deposition step and the selective removal step a plurality of cycles;
Each cycle increases the thickness of the epitaxial material at the bottom of the recess;
4. The method of claim 3, wherein in the recess, the blanket deposited semiconductor material film contains a higher concentration of dopant than the blanket deposited semiconductor material film underlying the film. The method according to claim 3, wherein the blanket film forming step includes a non-selective film forming step. The method of claim 3, wherein the blanket deposition includes forming a primarily amorphous semiconductor material on the insulating surface. The method of claim 3, wherein the blanket deposition step comprises flowing trisilane and carbon precursors into the chemical vapor deposition chamber. The method of claim 1, wherein the semiconductor material comprises carbon doped silicon. Depositing a semiconductor material on the bottom and sidewall surfaces of the recessed region of the single crystal semiconductor of the substrate;
Selectively removing a portion of the semiconductor material from a sidewall surface of the recessed region, leaving a heteroepitaxial film of the semiconductor material on the bottom surface;
Repeating the steps of depositing and selectively removing the semiconductor material;
A heteroepitaxial film of the semiconductor material deposited later selectively forms a heteroepitaxial semiconductor material containing different concentrations of impurities that cause strain compared to a heteroepitaxial film of the semiconductor material deposited earlier. Method. The method of claim 9, wherein the deposited film of semiconductor material is discretely tilted. 10. The method of claim 9, wherein the step of depositing the semiconductor material forms the heteroepitaxial film of the semiconductor material to a thickness of 1-100 nm in each cycle. The method of claim 9, wherein the heteroepitaxial film of the semiconductor material in the recessed region causes strain in an adjacent region of the substrate. The method of claim 12, wherein the strain is greatest at a top portion of the recessed area. The method of claim 9, wherein the semiconductor material comprises silicon doped with carbon impurities. The method of claim 9, wherein the largest strain of the semiconductor material in the recess is at a top portion of the recessed region. The method of claim 9, wherein the semiconductor material embeds the recessed region. The method of claim 9, wherein at least the heteroepitaxial film of the semiconductor material of the uppermost layer has a tensile strain. Providing a substrate having an insulating region and a recess formed thereon;
Forming in the recess a liner layer of heteroepitaxial silicon-containing material comprising impurities that cause strain to partially embed the recess;
Covering the liner layer by forming a filler containing a silicon-containing material having a lower concentration of impurities than the liner layer on the liner layer, and forming a semiconductor material in the recess. The method of claim 18, wherein the step of forming the liner layer comprises line the recess with silicon germanium. A capping layer formed from one material selected from the group consisting of silicon, silicon germanium, silicon doped with carbon, and silicon germanium doped with carbon is further formed on the filler. 18. The method according to 18. Forming the liner layer comprises forming a graded silicon germanium layer;
The step of covering the liner layer comprises filling the recess with silicon after forming the liner layer;
The method of claim 18, wherein the germanium concentration decreases as it moves away from the bottom and sides of the recess. The method of claim 21, wherein the tilted silicon-germanium layer comprises a discretely tilted layer. The method of claim 21, wherein the tilted silicon-germanium layer is a continuously tilted layer. The step of forming the liner layer and the step of covering the liner layer include:
The recess results in being embedded by a tilted silicon-germanium material;
20. The method of claim 19, wherein the germanium concentration decreases as it moves away from the bottom and sides of the recess. The step of forming the liner layer comprises:
19. The method of claim 18, comprising line the recess with carbon doped silicon. 26. The method of claim 25, further comprising forming a capping layer on the filler including one material selected from the group consisting of silicon, silicon germanium, silicon doped with carbon, and silicon germanium doped with carbon. the method of. The method of claim 18, wherein the liner layer of heteroepitaxial silicon-containing material in the recess acts in a lateral tensile strain on an adjacent region of the substrate. 28. The method of claim 27, wherein the adjacent region is a transistor channel region. The method of claim 18, further comprising annealing the substrate after forming the liner layer and before covering the liner layer with a silicon-containing material having a low concentration of impurities. 30. The method of claim 29, wherein the step of annealing the substrate comprises heating the substrate to a temperature of 650-900 <0> C. 30. The method of claim 29, wherein after the step of annealing the substrate, a heteroepitaxial silicon-containing material substantially covers the entire sidewall surface of the recess. The step of annealing the substrate comprises:
30. The method of claim 29, causing a portion of the heteroepitaxial silicon-containing material of the liner layer to migrate to the recess corner. 30. The method of claim 29, wherein after the step of annealing the substrate, the liner layer has a faceted cross-sectional shape. 34. The method of claim 33, wherein an interface between the liner layer and the filler is in the range of 25 to 55 degrees with respect to the bottom surface of the recess. 34. The method of claim 33, wherein after the step of annealing the substrate, the liner layer is substantially tapered along a recess sidewall. The recesses in the substrate,
A heteroepitaxial silicon-containing liner containing impurities that alters the lattice constant, covering substantially all of the single crystal sidewall surface of the recess;
A filler formed on the liner and embedding the recess;
A transistor channel adjacent to the recess;
The semiconductor device, wherein the filler includes a silicon-containing material having the impurity at a concentration lower than that of the liner. The semiconductor device according to claim 36, wherein the liner includes silicon-germanium. 38. The capping layer according to claim 37, further comprising a capping layer formed on the filler and including a material selected from the group consisting of silicon, silicon germanium, carbon-doped silicon, and carbon-doped silicon germanium. Semiconductor device. 37. The semiconductor device according to claim 36, wherein the liner includes carbon-doped silicon. 40. The capping layer of claim 39, further comprising a capping layer formed on the filler and including one material selected from the group consisting of silicon, silicon germanium, silicon doped with carbon, and silicon germanium doped with carbon. Semiconductor device. 37. The semiconductor device according to claim 36, further comprising a capping layer that is formed on the filler and that includes the impurity at a concentration lower than that of the heteroepitaxial liner that covers the entire sidewall surface of the recess. The interface between the liner and the filler is tapered;
37. The semiconductor device according to claim 36, wherein the liner is discontinuous on the bottom surface of the recess. The liner is tapered, and
37. The semiconductor device according to claim 36, wherein the liner includes a thinner portion on the bottom surface of the recess than the liner on the sidewall surface of the recess. 37. The semiconductor device according to claim 36, wherein the liner has tensile strain. 37. The semiconductor device according to claim 36, wherein the liner causes compressive strain in the transistor channel. 46. The semiconductor device according to claim 45, wherein the liner is silicon-germanium. A recess embedded with a heteroepitaxial stressor material;
A transistor channel adjacent to the recess;
An upper portion of the stressor material in the recess has a first impurity concentration;
A lower portion of the stressor material in the recess has a second impurity concentration;
The first impurity concentration is higher than the second impurity concentration;
A semiconductor device in which the upper part extends to connect to the side wall of the recess. 48. The semiconductor device according to claim 47, wherein the stressor substance has a higher impurity concentration on the top surface than on the bottom surface. 48. The semiconductor device according to claim 47, wherein the stressor material is silicon-germanium. 48. The semiconductor device according to claim 47, wherein the stressor material is silicon doped with carbon impurities. The stressor material comprises a discrete membrane;
48. The semiconductor device according to claim 47, wherein each of the films has a higher impurity concentration than a film under the film. 48. The semiconductor device according to claim 47, wherein the stressor material has tensile strain.