CN103779215B - A semiconductor device and method of preparation - Google Patents

A semiconductor device and method of preparation Download PDF

Info

Publication number
CN103779215B
CN103779215B CN 201210398804 CN201210398804A CN103779215B CN 103779215 B CN103779215 B CN 103779215B CN 201210398804 CN201210398804 CN 201210398804 CN 201210398804 A CN201210398804 A CN 201210398804A CN 103779215 B CN103779215 B CN 103779215B
Authority
CN
Grant status
Grant
Patent type
Prior art keywords
etching
sige
method according
sige layer
method
Prior art date
Application number
CN 201210398804
Other languages
Chinese (zh)
Other versions
CN103779215A (en )
Inventor
金兰
何永根
何有丰
涂火金
林静
Original Assignee
中芯国际集成电路制造(上海)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Abstract

本发明涉及一种半导体器件及其制备方法,所述方法包括:提供半导体衬底,至少包含栅极结构;在所述栅极两侧形成凹槽;沉积SiGe,在所述凹槽的底部和侧壁形成SiGe层;然后蚀刻去除部分所述SiGe层,以在所述凹槽的底部和侧壁上形成厚度均一共形的SiGe层。 The present invention relates to a semiconductor device and method of preparation, the method comprising: providing a semiconductor substrate, comprising at least a gate structure; forming a recess in the sides of the gate; depositing SiGe, and the bottom of the recess forming sidewall SiGe layer; and etching away the portion of the SiGe layer, SiGe layer thicknesses are conformal to form on the bottom and sidewalls of the recess. 在本发明中通过在所述凹槽中形成厚度均一共形的SiGe层,最终得到源漏,所述器件的性能更好。 In the present invention, by a conformal SiGe layer thickness are formed in the groove, to give the final source and drain, the better the performance of the device.

Description

一种半导体器件及其制备方法 A semiconductor device and method of preparation

技术领域 FIELD

[0001] 本发明涉及半导体领域,具体地,本发明涉及一种半导体器件及其制备方法。 [0001] The present invention relates to the field of semiconductors, in particular, the present invention relates to a semiconductor device and method of preparation. 背景技术 Background technique

[0002] 随着集成电路技术的持续发展,芯片上将集成更多器件,芯片也将采用更快的速度。 [0002] With the continued development of integrated circuit technology, more devices integrated on chip, the chip will also use a faster speed. 在这些要求的推进下,器件的几何尺寸将不断缩小,在芯片的制造工艺中不断采用新材料、新技术和新的制造工艺。 In advance of these requirements, the geometry of the device will continue to shrink, the chip manufacturing process in use of new materials, new technologies and new manufacturing processes. 目前半导体器件的制备已经发展到纳米级别,同时常规器件的制备工艺逐渐成熟。 Currently preparing a semiconductor device has been developed to nanometers, while the conventional device manufacturing process maturity.

[0003] 目前半导体器件中制备PM0S的方法的过程中为了获得更好的性能,通常在PM0S的源漏区进行外延SiGe以对衬底的沟道处施加压应力,现有技术中一般在PM0S源漏上形成凹陷,然后外延生长SiGe,所述SiGe可以外延至与所述衬底平齐,现有技术制备过程中可以在所述凹陷的侧壁生长一层SiGe,以在凹陷中形成镶嵌的SiGe(embedded SiGe on different facet),然后重复多次,每次形成的SiGe如图1所示,通过所述方法得到的SiGe 层厚度不均一,在所述凹陷底部晶面(1〇〇)上的厚度要大于所述凹陷侧壁晶面(111)上的厚度,由于所述凹陷的源漏上SiGe层厚度不均一导致制备得到的器件性能降低。 [0003] The method of the current process PM0S semiconductor device prepared in order to obtain better performance, usually carried out in PM0S epitaxial SiGe source and drain regions in the substrate at the channel of the compression stress is applied, the prior art generally PM0S a recess is formed on the source and drain, and then epitaxially growing SiGe, the SiGe substrate may be flush with the outer extended, the prior art manufacturing process SiGe layer may be grown in the recess sidewall, to form a recess in the insert the SiGe (embedded SiGe on different facet), and then repeated several times, each time formed as shown in FIG SiGe, SiGe obtained by the process 1 a non-uniform layer thickness, the crystal plane at the bottom of the recess (1〇〇) thickness greater than the thickness of the (111) crystal plane of the side wall recess, the recess due to the source and drain SiGe layer on a non-uniform thickness leads to reduced device performance is prepared. 引起所述厚度不均一的原因是由于所述SiGe在凹陷底部晶面(100)上和在凹陷侧壁晶面(111)上外延生长速度不一样造成的,其中所述SiGe在晶面(100)的生长速度大于晶面(111)的生长速度。 Causes non-uniform thickness due to the bottom surface of the SiGe crystal in the recess (100) on the recess side wall and the crystal plane (111) caused by the epitaxial growth rate is not the same, wherein the SiGe crystal face (100 ) grew faster than the growth rate of the crystal face (111).

[0004] 因此,现有技术中虽然有制备源漏(recessed Source/Drain)的方法,但是所述方法中在凹陷底部和侧壁上形成的SiGe的厚度不一样,造成器件性能降低,目前的方法不能制备厚度均一的SiGe层,需要对所述方法进行改进以克服所述问题。 [0004] Thus, although the prior art method of making the source-drain (recessed Source / Drain), but the process in the bottom of the recess and the thickness of SiGe is formed on the side walls are not the same, resulting in decreased device performance, the current the method of the SiGe layer having a uniform thickness can not be prepared, the method needs to be improved to overcome the problem. 发明内容 SUMMARY

[0005] 在发明内容部分中引入了一系列简化形式的概念,这将在具体实施方式部分中进一步详细说明。 [0005] introduced the concept of a series of simplified form in the Summary section, which will be described in further detail in the Detailed Description. 本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征,更不意味着试图确定所要求保护的技术方案的保护范围。 This summary of the present invention is not intended to identify key features or essential features of the claimed technical solutions, nor is it intended to determine the scope of the claimed technical solution.

[0006] 为了解决上述问题,本发明提供了一种半导体器件的制备方法,包括: [0006] In order to solve the above problems, the present invention provides a method for preparing a semiconductor device, comprising:

[0007] 提供半导体衬底,至少包含栅极结构; [0007] providing a semiconductor substrate, comprising at least a gate structure;

[0008] 在所述栅极两侧形成凹槽; [0008] The grooves are formed at both sides of said gate electrode;

[0009] 沉积SiGe,在所述凹槽的底部和侧壁形成SiGe层; [0009] deposition of SiGe, the SiGe layer is formed in the groove bottom and sidewalls;

[0010] 然后蚀刻去除部分所述SiGe层,以在所述凹槽的底部和侧壁上形成厚度均一共形的SiGe层。 [0010] and then etching away the portion of the SiGe layer, SiGe layer thicknesses are conformal to form on the bottom and sidewalls of the recess.

[0011] 作为优选,所述SiGe在所述凹槽底部晶面(100)上的外延生长速度大于所述侧壁晶面(111)上的外延生长速度。 [0011] Advantageously, the bottom of the recess in the SiGe epitaxial growth rate on a crystal face (100) is greater than the rate of epitaxial growth on the (111) crystal plane of the side wall.

[0012] 作为优选,所述SiGe在所述凹槽底部晶面(100)上的蚀刻速度大于所述侧壁晶面(111)上的蚀刻速度。 [0012] Advantageously, the bottom of the recess in the SiGe etching rate on a crystal plane (100) is greater than the etching rate on the (111) crystal plane of the side wall.

[0013] 作为优选,所述蚀刻为干法蚀刻。 [0013] Advantageously, said etching is dry etching.

[0014] 作为优选,所述蚀刻选用的蚀刻气体为HC1或Cl2。 [0014] Advantageously, said etching the etching gas is selected HC1 or Cl2. [〇〇15]作为优选,所述蚀刻气体的载气为H2。 [〇〇15] Advantageously, the etching gas for the carrier gas H2.

[0016] 作为优选,所述蚀刻时间以及气体流量取决于沉积的所述SiGe层的厚度。 [0016] Advantageously, the gas flow rate and etching time depends on the thickness of the deposited SiGe layer.

[0017] 作为优选,所述蚀刻温度为500〜800 °C。 [0017] Advantageously, the etching temperature is 500~800 ° C. [〇〇18] 作为优选,所述HC1或C12的气体流量为5〜500sccm。 [〇〇18] Advantageously, the gas flow rate is HC1 or C12 5~500sccm. [〇〇19] 作为优选,所述H2的气体流量为15〜45slm。 [〇〇19] Advantageously, the H2 gas flow rate is 15~45slm. [〇〇2〇] 作为优选,所述蚀刻压力为5〜700Torr。 [〇〇2〇] Advantageously, said etching pressure is 5~700Torr. [0021 ]作为优选,所述蚀刻时间为1-15分钟。 [0021] Advantageously, the etching time is 15 minutes.

[0022] 作为优选,所述SiGe的沉积方法为选择性的化学气相沉积法或者非选择性的化学气相沉积法。 [0022] Advantageously, the SiGe deposition process for selective chemical vapor deposition process or non-selective chemical vapor deposition.

[0023] 作为优选,蚀刻去除部分所述SiGe层,以使所述凹槽的底部和侧壁的SiGe层的厚度相同。 [0023] Advantageously, etching away the portion of the SiGe layer, the SiGe layer so that the thickness of the same groove bottom and side walls. [〇〇24]作为优选,所述凹槽为2形凹槽。 [〇〇24] Advantageously, the groove-shaped recess 2.

[0025] 作为优选,所述方法还包括多次重复上述沉积步骤和蚀刻步骤,直至所述SiGe层填满所述凹槽为止。 [0025] Advantageously, the method further comprises the step of repeating a plurality of times such deposition and etching steps, until the SiGe layer fills up the recess.

[0026] 本发明还提供了一种上述方法制备得到的半导体器件。 [0026] The present invention further provides a semiconductor device obtained by the above preparation method.

[0027] 在本发明中为了解决现有技术中存在的问题,首先在所述凹陷中沉积SiGe层,由于SiGe在凹陷底部晶面(100)上和在凹陷侧壁晶面(111)上外延生长速度不一样,使得到的SiGe层的厚度不均一,然后接着进行蚀刻去除部分所述SiGe层,在本发明中选择HC1为蚀刻气体,H2为蚀刻气体的载气,并根据沉积的所述SiGe层的厚度控制蚀刻温度、蚀刻气体流量以及蚀刻时间,通过控制所述SiGe在凹陷底部晶面(100)上和在凹陷侧壁晶面(111)上蚀刻速度,最终得到厚度一样的SiGe层,得到性能更好的器件。 [0027] In order to solve the problems in the prior art, in the first SiGe layer is deposited in the recess, since the recess in the bottom of the SiGe epitaxial crystal plane (100) on the recess side wall and the crystal plane (111) in the present invention, growth rate is not the same, the thickness of the SiGe layer to obtain a non-uniform, then subsequently removed by etching the portion of the SiGe layer, the etching gas is selected HC1 in the present invention, H2 as the carrier gas of an etching gas, according to the deposited the thickness of the SiGe layer to control the etching temperature, etching time and etching gas flow rate, by controlling the SiGe crystal plane at the bottom of the recess in the sidewall of the depressions on the crystal plane and (111) on the etch rate (100), to give the same final thickness of SiGe layer to give better device performance. 附图说明 BRIEF DESCRIPTION

[0028] 本发明的下列附图在此作为本发明的一部分用于理解本发明。 [0028] The following figures of the present invention is used herein as part of the present invention to understand the invention. 附图中示出了本发明的实施例及其描述,用来解释本发明的装置及原理。 Shown in the drawings and described in the present embodiment of the invention, serve to explain the principles of the invention and the apparatus. 在附图中, In the drawings,

[0029] 图1为现有技术中制备得到的凹陷源漏的结构示意图; [0029] FIG. 1 is a schematic view of the recessed source and drain of the prior art prepared;

[0030] 图2为图1中凹陷中SiGe层的结构的方法示意图; [0030] FIG. 2 is a schematic view of the method of the structure 1 in FIG recessed SiGe layer;

[0031] 图3为本发明中制备得到的凹陷源漏的结构示意图;[〇〇32]图4为图3中凹陷中S iGe层的结构的方法示意图。 [0031] FIG. 3 is a schematic structural diagram of a recess in the source and drain of the present invention is prepared; [〇〇32] FIG. 4 is a schematic structure of the method of recesses S iGe layer 3 is. 具体实施方式 detailed description

[0033] 在下文的描述中,给出了大量具体的细节以便提供对本发明更为彻底的理解。 [0033] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. 然而,对于本领域技术人员而言显而易见的是,本发明可以无需一个或多个这些细节而得以实施。 However, those skilled in the art will be apparent that the present invention may be practiced without one or more of these details are implemented. 在其他的例子中,为了避免与本发明发生混淆,对于本领域公知的一些技术特征未进行描述。 In other examples, in order to avoid confusion with the present invention, known in the art for some of the technical features are not described.

[0034] 为了彻底理解本发明,将在下列的描述中提出详细的描述,以说明本发明所述半导体器件的制备方法。 [0034] For a thorough understanding of the invention will be set forth in the following detailed description of the description, to illustrate the preparation of the semiconductor device of the present invention. 显然,本发明的施行并不限于半导体领域的技术人员所熟习的特殊细节。 Obviously, the purposes of the present invention is not limited to the specific details of the semiconductor art are familiar with the art. 本发明的较佳实施例详细描述如下,然而除了这些详细描述外,本发明还可以具有其他实施方式。 As described in detail preferred embodiments of the present invention, however, in addition to the detailed description, the present invention also may have other embodiments.

[0035] 应予以注意的是,这里所使用的术语仅是为了描述具体实施例,而非意图限制根据本发明的示例性实施例。 [0035] should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments of the present invention. 如在这里所使用的,除非上下文另外明确指出,否则单数形式也意图包括复数形式。 As used herein, unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms. 此外,还应当理解的是,当在本说明书中使用术语“包含”和/或“包括” 时,其指明存在所述特征、整体、步骤、操作、元件和/或组件,但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。 Further, it should be appreciated that, when used in the present specification "comprises" and / or "including" when that specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0036] 现在,将参照附图更详细地描述根据本发明的示例性实施例。 [0036] Now, with reference to the accompanying drawings according to an exemplary embodiment of the present invention will be described in more detail. 然而,这些示例性实施例可以多种不同的形式来实施,并且不应当被解释为只限于这里所阐述的实施例。 However, these exemplary embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. 应当理解的是,提供这些实施例是为了使得本发明的公开彻底且完整,并且将这些示例性实施例的构思充分传达给本领域普通技术人员。 It should be understood that these embodiments are provided so that the disclosure of the present invention will be thorough and complete, and the concept of the exemplary embodiment fully convey the embodiments to those of ordinary skill in the art. 在附图中,为了清楚起见,夸大了层和区域的厚度,并且使用相同的附图标记表示相同的元件,因而将省略对它们的描述。 In the drawings, for clarity, it is exaggerated, and the thickness of the layer regions, and the same reference numerals denote like elements, and thus descriptions thereof will be omitted.

[0037] 如图3所示,首先提供半导体衬底201,所述半导体衬底可以是以下所提到的材料中的至少一种:硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SS0I)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。 [0037] As shown in FIG. 3, first, a semiconductor substrate 201, the semiconductor substrate may be a material mentioned below at least one of: silicon, silicon on insulator (the SOI), silicon-on-insulator laminate (SS0I ), laminated silicon-germanium-on-insulator (S-SiGeOI), silicon germanium (SiGeOI) and germanium-on-insulator (a GeOI) and the like on an insulator. 在本发明中优选绝缘体上硅(S0I),所述绝缘体上硅(SOI)从下往上依次为支撑衬底、氧化物绝缘层以及半导体材料层, 但并不局限于上述示例。 In the present invention, preferably a silicon-on-insulator (SOI), silicon-on-insulator (SOI) from bottom to top of a supporting substrate, an oxide insulating layer and the semiconductor material layer, but is not limited to the above example. [〇〇38]在所述半导体衬底中形成隔离结构,所述隔离结构为浅沟槽隔离(STI)结构或者局部氧化硅(L0C0S)隔离结构。 [〇〇38] forming an isolation structure in the semiconductor substrate, the isolation structure is a shallow trench isolation (STI) structures or local oxidation of silicon (L0C0S) isolation structures. 所述半导体衬底中还形成有各种阱(well)结构及衬底表面的沟道层。 Also in the semiconductor substrate and the channel layer of the substrate surface structure of various well (well). 一般来说,形成阱(well)结构的离子掺杂导电类型与沟道层离子掺杂导电类型相同,但是浓度较栅极沟道层低,离子注入的深度泛围较广,同时需达到大于隔离结构的深度。 In general, ion forming a well (Well) structure of the same conductivity type doped channel layer and the ion doping, but relatively low concentration of the channel layer, a gate, depth of ion implantation around a wide pan, and greater than required to achieve depth of the isolation structure.

[0039] 在所述衬底上形成栅极结构202,在所述衬底上形成栅极介电层,所述栅极介电层可以是氧化硅(Si02)或氮氧化硅(S1N)。 [0039] The gate structure 202 is formed on the substrate, forming a gate dielectric layer on the substrate, the gate dielectric layer may be silicon oxide (Si02) or silicon oxynitride (S1N). 可以采用本领域技术人员所习知的氧化工艺例如炉管氧化、快速热退火氧化(RT0)、原位水蒸气氧化(ISSG)等形成氧化硅材质的栅极介质层。 Those skilled in the art that conventional processes such as an oxidation furnace oxidation, rapid thermal anneal oxide (the RT0), in-situ steam oxidation (the ISSG) is formed like a gate dielectric layer of silicon oxide material may be employed. 然后沉积栅极材料层,包含半导体材料的多层结构,例如硅、锗、金属或其组合。 And depositing a gate material layer, the multilayer structure comprises a semiconductor material such as silicon, germanium, metals, or combinations thereof. 对所述栅极介质层以及栅极材料层进行蚀刻形成栅极结构。 The gate dielectric layer and a gate material layer is etched to form the gate structure.

[0040] 形成栅极结构后在栅极的两侧形成间隙壁,所述间隙壁可以为氧化硅、氮化硅、氮氧化硅中一种或者它们组合构成。 After [0040] forming a gate structure formed on both sides of the gate spacers, the spacer may be a silicon oxide, silicon nitride, silicon oxide composed of one or a combination thereof. 作为本实施例的一个优化实施方式,所述间隙壁为氧化硅、氮化硅共同组成,具体工艺为:在半导体衬底上形成第一氧化硅层、第一氮化硅层以及第二氧化硅层,然后采用蚀刻方法形成间隙壁。 As a preferred mode of the present embodiment, the spacer is a silicon oxide, composed, the specific process of: forming a first silicon oxide layer on a semiconductor substrate, a first silicon nitride layer and a second oxide silicon layer, and a method of forming the spacers by etching.

[0041] 其中上述浅沟槽以及栅极结构、离子注入等均是示例性的,并非局限于该实施方式,本领域技术人员可以根据制备器件的需要选择本领域常用的其他方法或者在该衬底中形成其他有源器件。 [0041] wherein said shallow trench and a gate structure, ion implantation and so is exemplary embodiment is not limited to this embodiment, those skilled in the art may select other methods commonly used in the art of fabricating a device needed in the liner or other active devices formed in the substrate.

[0042] 形成所述间隙壁后蚀刻所述栅极的两侧形成凹槽,在本发明中优选形成“E”形凹槽,如图3所示,然后在所述的凹槽中外延生长SiGe,以在所述凹陷中底部晶面(100)和侧壁晶面(111)上形成SiGe层。 [0042] After forming the spacers are formed on both sides of the gate recess etching, preferably formed "E" shaped groove in the present invention, shown in Figure 3, and then the epitaxial growth in the groove SiGe, SiGe layer to form on the bottom of the crystal plane (100) crystal plane and a side wall (111) of said recess. [〇〇43]其中,所述SiGe的沉积可以选用选择性的化学气相沉积(CVD)法、非选择性的化学气相沉积(CVD)法物理气相沉积(PVD)法或原子层沉积(ALD)法等形成的低压化学气相沉积(LPCVD)、激光烧蚀沉积(LAD)以及选择外延生长(SEG)中的一种。 [〇〇43] wherein the SiGe deposition can use selective chemical vapor deposition (CVD) method, a non-selective chemical vapor deposition (CVD) method, physical vapor deposition (PVD) or atomic layer deposition (ALD) low pressure chemical vapor deposition (LPCVD) method or the like formed by laser ablation deposition (LAD) and a selection An epitaxial growth (SEG) of. 在本发明中优选化学气相沉积(CVD)法。 In the present invention, the preferred chemical vapor deposition (CVD) method. [〇〇44]具体地,在沉积所述SiGe层时通入原料气体,例如含Ge的气体GeH4,并选择H2作为载气,其中反应气体和载气的流量比为0.0001〜0.01,选择SiH2Cl2作为反应气体,选择H2作为载气,其中反应气体和载气的流量比为0.0001〜0.01,沉积的温度为500-950°C,优选为550-750 °C,气体压力为5-700Torr,优选为5-40Torr。 [〇〇44] Specifically, when the deposition material gas into the SiGe layer, Ge-containing gas e.g. GeH4, and H2 as a carrier gas selected, wherein the reaction gas and the carrier gas flow ratio is 0.0001~0.01 select SiH2Cl2 as the reaction gas, H2 as a carrier gas selected, wherein the reaction gas and the carrier gas flow ratio is 0.0001~0.01, the deposition temperature of 500-950 ° C, preferably 550-750 ° C, gas pressure 5-700Torr, preferably as 5-40Torr. [〇〇45]申请人发现,在一具体实施方式中,当所述沉积温度为700°C,气体压力为20T〇rr, 所述GeH4和H2的流量比为0.01,所述SiH2Cl2和H2的流量比为0.01时,所述SiGe在所述凹陷中底部晶面(100)和侧壁晶面(111)上的生长速度为5:4,经过一定时间,在凹陷中底部晶面(100)和侧壁晶面(111)上形成的厚度分别为50nm和40nm,因此所述厚度不均一。 [〇〇45] Applicants have discovered, in one specific embodiment, when the deposition temperature is 700 ° C, a pressure of the gas flow 20T〇rr, the ratio of GeH4 and H2 was 0.01, and the H2, SiH2Cl2 flow ratio of 0.01, the growth rate of the SiGe crystal plane on the bottom (100) crystal plane and a side wall (111) of the recess is 5: 4, after a certain time, the recess in the bottom surface of the crystal (100) crystal plane and the side wall thickness is formed on a (111) is 50nm and 40nm respectively, whereby said non-uniform thickness.

[0046] 继续参照图3,然后蚀刻去除部分所述SiGe层,以在所述凹槽的底部和侧壁上形成厚度均一共形的SiGe层。 [0046] With continued reference to FIG. 3, and then etching away the portion of the SiGe layer, the SiGe layer thickness are conformal to the recess formed on the bottom and side walls.

[0047] 在本发明中选用干法蚀刻所述SiGe,发明人通过实验发现在蚀刻过程中所述SiGe 在所述凹槽底部晶面(100)上的蚀刻速度小于所述侧壁晶面(111)上的蚀刻速度。 [0047] The selection of dry etching in the present invention, SiGe, the inventors found through experiments that the SiGe etch rate during etching on the (100) is smaller than the groove bottom of the side wall crystal plane crystallographic plane ( the etching rate 111). [〇〇48]作为优选,所述蚀刻选用的蚀刻气体为HC1和/或Cl2,所述蚀刻气体的载气为出,其中,所述蚀刻时间以及气体流量取决于沉积的所述SiGe层的厚度,所述蚀刻温度为500〜850 °C,更优选为550-700°C,所述HC1或Cl2的气体流量为5〜500sccm,所述H2的气体流量为15〜 45slm,所述HC1的气体流量与所述H2的气体流量比为0.0001〜0.001,在本发明中优选为0.5 〜4 X 1(T3,在所述优选范围内具有更好的蚀刻效果,以保证得到厚度均一的SiGe。 [〇〇48] Advantageously, said etching the etching gas is selected HC1 and / or carrier gas Cl2, the etching gas is out, wherein the gas flow rate depends on the etching time, and the deposited SiGe layer the thickness of the etching temperature is 500~850 ° C, more preferably 550-700 ° C, flow rate of the gas is HC1 or Cl2 5~500sccm, the H2 gas flow rate of 15~ 45slm, the HC1 is gas flow rate and H2 gas flow rate ratio of the 0.0001~0.001, preferably from 0.5 ~4 X 1 (T3, better etching effect is within the preferred range of the present invention, which guarantees a uniform thickness of SiGe.

[0049] 具体地,在本发明所述实施例中,当所述SiGe层在凹陷中底部晶面(100)和侧壁晶面(111)上形成的厚度分别为50nm和40nm时,然后通入蚀刻气体HC1以及载气出,当所述蚀刻温度为750°C时,在不同的HC1与所述出的气体流量比时,所述SiGe在所述凹陷中底部晶面(100)和侧壁晶面(111)上的蚀刻速度不同。 [0049] In particular, in the embodiment of the present invention, when the thickness of the SiGe layer on the bottom of the crystal plane (100) crystal plane and a side wall (111) formed in the recess is 50nm and 40nm respectively, and then through HC1 and the etching gas into the carrier gas, when the etching temperature is 750 ° C, at a different ratio of the HC1 gas flow out of the bottom of the SiGe crystal plane (100) and a concave side different crystal plane wall (111) of the etching rate. 其中当所述HC1的气体流量与所述H2的气体流量比为3.75 X1(T3时,所述SiGe在所述凹陷中底部晶面(100)和侧壁晶面(111)上的蚀刻速度为9:5,可以根据所述SiGe层的厚度选择蚀刻时间。例如本发明中所述SiGe层在凹陷中底部晶面(100)和侧壁晶面(111)上形成的厚度分别为50nm和40nm时,蚀刻时间为2.5分钟时即可使SiGe层在凹陷中底部晶面(100)和侧壁晶面(111)上形成的厚度相同,均为27.5nm. Wherein the gas flow when the gas flow rate of the HC1 and H2 ratio of 3.75 X1 (T3, said SiGe crystal plane in the bottom of the recess (100) crystal plane and a side wall (111) on the etch rate of 9: 5, the etching time may be selected depending on the thickness of the SiGe layer of the present invention, for example, a thickness of the SiGe layer is formed on the bottom of the crystal plane (100) crystal plane and a side wall (111) of the recess are 40nm and 50nm. when the etching time of the SiGe layer can be formed on the same crystal plane of the bottom (100) crystal plane and a sidewall (111) recessed thickness 2.5 minutes are 27.5nm.

[0050] 申请人还发现,在本发明中根据所述SiGe层在凹陷中底部晶面(100)和侧壁晶面(111)上形成的厚度选择所述蚀刻时间和温度,所述蚀刻温度为550-850°C时效果更好。 [0050] Applicant has also found that, in the present invention, the etching time and temperature selected according to the thickness of the SiGe layer is formed on the bottom of the crystal plane (100) crystal plane and a side wall (111) recesses, said etching temperature better when 550-850 ° C.

[0051] 在本发明中为了解决现有技术中存在的问题,首先在所述凹陷中沉积SiGe层,由于SiGe在凹陷底部晶面(100)上和在凹陷侧壁晶面(111)上外延生长速度不一样,使得到的SiGe层的厚度不均一,然后接着进行蚀刻去除部分所述SiGe层,在本发明中选择HC1为蚀刻气体,H2为蚀刻气体的载气,并根据沉积的所述SiGe层的厚度控制蚀刻温度、蚀刻气体流量以及蚀刻时间,通过控制所述SiGe在凹陷底部晶面(100)上和在凹陷侧壁晶面(111)上蚀刻速度,得到厚度一样的SiGe层,得到性能更好的器件。 [0051] In order to solve the problems in the prior art, in the first SiGe layer is deposited in the recess, since the recess in the bottom of the SiGe epitaxial crystal plane (100) on the recess side wall and the crystal plane (111) in the present invention, growth rate is not the same, the thickness of the SiGe layer to obtain a non-uniform, then subsequently removed by etching the portion of the SiGe layer, the etching gas is selected HC1 in the present invention, H2 as the carrier gas of an etching gas, according to the deposited the thickness of the SiGe layer to control the etching temperature, etching time and etching gas flow rate, by controlling the SiGe crystal plane at the bottom of the recess in the sidewall of the depressions on the crystal plane and (111) on the etch rate (100), to obtain a uniform thickness of the SiGe layer, better device performance. [〇〇52] 作为优选,所述方法还包括多次重复上述沉积步骤和蚀刻步骤,直至所述SiGe层填满所述凹槽为止。 [〇〇52] Advantageously, the method further comprises the step of repeating a plurality of times such deposition and etching steps, until the SiGe layer fills up the recess. [〇〇53] 本发明已经通过上述实施例进行了说明,但应当理解的是,上述实施例只是用于举例和说明的目的,而非意在将本发明限制于所描述的实施例范围内。 [〇〇53] The present invention has been described by the above embodiments, it should be understood that the above examples are only for purposes of illustration and description, and not intended to be within the scope of the embodiments of the present invention be limited to the described . 此外本领域技术人员可以理解的是,本发明并不局限于上述实施例,根据本发明的教导还可以做出更多种的变型和修改,这些变型和修改均落在本发明所要求保护的范围以内。 Moreover, those skilled in the art will be appreciated that the present invention is not limited to the above embodiment, in accordance with the teachings of the present invention may be made more of the variations and modifications, all such variations and modifications fall within the invention as claimed within the range. 本发明的保护范围由附属的权利要求书及其等效范围所界定。 The scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (16)

  1. 1.一种半导体器件的制备方法,包括:提供半导体衬底,至少包含栅极结构;在所述栅极两侧形成凹槽,所述凹槽为S形凹槽;沉积SiGe,在所述凹槽的底部和侧壁形成SiGe层,所述凹槽的底部形成的所述SiGe层的厚度大于所述侧壁形成的所述SiGe层的厚度;然后蚀刻去除部分所述SiGe层,以在所述凹槽的底部和侧壁上形成厚度均一共形的SiGe 层。 1. A method for preparing a semiconductor device, comprising: providing a semiconductor substrate, comprising at least a gate structure; forming a recess in the sides of the gate, the groove is S-shaped groove; deposited SiGe, the and sidewalls of the groove bottom SiGe layer is formed, the thickness of the SiGe layer forming the bottom of the groove is greater than the thickness of the SiGe layer formed on the sidewall; then etching away the portion of the SiGe layer, in order to the bottom and sidewalls of the groove have a total thickness of the SiGe layer is formed on the shape.
  2. 2.根据权利要求1所述的方法,其特征在于,所述SiGe在所述凹槽底部晶面(100)上的外延生长速度大于所述侧壁晶面(111)上的外延生长速度。 2. The method according to claim 1, wherein the groove bottom in the SiGe epitaxial growth rate on a crystal face of (100) crystal planes is larger than said side wall (111) on the epitaxial growth rate.
  3. 3.根据权利要求1所述的方法,其特征在于,所述SiGe在所述凹槽底部晶面(100)上的蚀刻速度大于所述侧壁晶面(111)上的蚀刻速度。 3. The method according to claim 1, wherein the groove bottom in the SiGe crystal plane etching rate on the (100) crystal planes is larger than said side wall (111) on the etching rate.
  4. 4.根据权利要求1所述的方法,其特征在于,所述蚀刻为干法蚀刻。 4. The method according to claim 1, wherein said etching is dry etching.
  5. 5.根据权利要求1所述的方法,其特征在于,所述蚀刻选用的蚀刻气体为HC1或Cl2。 5. The method according to claim 1, wherein said etching gas to etch selected HC1 or Cl2.
  6. 6.根据权利要求5所述的方法,其特征在于,所述蚀刻气体的载气为H2。 6. The method as claimed in claim 5, wherein the etching gas for the carrier gas H2.
  7. 7.根据权利要求5所述的方法,其特征在于,所述蚀刻时间以及气体流量取决于沉积的所述SiGe层的厚度。 7. The method according to claim 5, characterized in that the gas flow rate and etching time depends on the thickness of the deposited SiGe layer.
  8. 8.根据权利要求1或5所述的方法,其特征在于,所述蚀刻温度为500〜800°C。 8. The method according to claim 1 or claim 5, wherein said etching temperature is 500~800 ° C.
  9. 9.根据权利要求5所述的方法,其特征在于,所述HC1或C12的气体流量为5〜500sccm。 9. The method according to claim 5, characterized in that the flow rate of the gas is HC1 or C12 5~500sccm.
  10. 10.根据权利要求6所述的方法,其特征在于,所述H2的气体流量为15〜45slm。 10. The method according to claim 6, characterized in that the gas flow rate of the H2 is 15~45slm.
  11. 11.根据权利要求5或6所述的方法,其特征在于,所述蚀刻压力为5〜700Torr。 11. The method of claim 5 or claim 6, wherein the etching pressure is 5~700Torr.
  12. 12.根据权利要求5或6所述的方法,其特征在于,所述蚀刻时间为1-15分钟。 12. The method according to claim 5 or 6, wherein the etching time is 15 minutes.
  13. 13.根据权利要求1所述的方法,其特征在于,所述SiGe的沉积方法为选择性的化学气相沉积法或者非选择性的化学气相沉积法。 13. The method according to claim 1, wherein the SiGe deposition process for the selective chemical vapor deposition process or non-selective chemical vapor deposition.
  14. 14.根据权利要求1所述的方法,其特征在于,蚀刻去除部分所述SiGe层,以使所述凹槽的底部和侧壁的SiGe层的厚度相同。 14. The method according to claim 1, wherein etching away a portion of the SiGe layer, the SiGe layer so that the thickness of the same groove bottom and side walls.
  15. 15.根据权利要求1所述的方法,其特征在于,所述方法还包括多次重复上述沉积步骤和蚀刻步骤,直至所述SiGe层填满所述凹槽为止。 15. The method according to claim 1, wherein said method further comprises repeating the deposition step and the etching step a plurality of times, until the SiGe layer fills up the recess.
  16. 16.—种权利要求1-15之一所述方法制备得到的半导体器件。 The semiconductor device obtained by the method for preparing one of claims 1-15 16.- species.
CN 201210398804 2012-10-18 2012-10-18 A semiconductor device and method of preparation CN103779215B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201210398804 CN103779215B (en) 2012-10-18 2012-10-18 A semiconductor device and method of preparation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201210398804 CN103779215B (en) 2012-10-18 2012-10-18 A semiconductor device and method of preparation

Publications (2)

Publication Number Publication Date
CN103779215A true CN103779215A (en) 2014-05-07
CN103779215B true CN103779215B (en) 2016-09-21

Family

ID=50571337

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201210398804 CN103779215B (en) 2012-10-18 2012-10-18 A semiconductor device and method of preparation

Country Status (1)

Country Link
CN (1) CN103779215B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102074461A (en) * 2009-10-30 2011-05-25 台湾积体电路制造股份有限公司 Semiconductor device and method of fabricating same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7361563B2 (en) * 2004-06-17 2008-04-22 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device using a selective epitaxial growth technique
US7759199B2 (en) * 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102074461A (en) * 2009-10-30 2011-05-25 台湾积体电路制造股份有限公司 Semiconductor device and method of fabricating same

Also Published As

Publication number Publication date Type
CN103779215A (en) 2014-05-07 application

Similar Documents

Publication Publication Date Title
US20070023795A1 (en) Semiconductor device and method of fabricating the same
US20110227162A1 (en) Method of making a finfet, and finfet formed by the method
US20050170604A1 (en) Method for forming a semiconductor device with local semiconductor-on-insulator (SOI)
JP2006261283A (en) Semiconductor device and its manufacturing method
US20140357060A1 (en) Method for the formation of fin structures for finfet devices
US20130092954A1 (en) Strained Silicon Channel Semiconductor Structure and Method of Making the Same
US20120049201A1 (en) Semiconductor device and manufacturing method of the same
US20150108544A1 (en) Fin Spacer Protected Source and Drain Regions in FinFETs
JP2012004473A (en) Semiconductor device and method for manufacturing semiconductor device
JP2007214481A (en) Semiconductor device
CN101986423A (en) Method for forming high germanium concentration sige stressor and integrated circuit transistor structure
CN101925986A (en) Semiconductor device and method for production thereof
US20090280627A1 (en) Method of forming stepped recesses for embedded strain elements in a semiconductor device
US20050285194A1 (en) Semiconductor-on-insulating (SOI) field effect transistors with body contacts and methods of forming same
JP2007110098A (en) Semiconductor device subject to stress deformation and manufacturing method thereof
US20130252392A1 (en) Performing Enhanced Cleaning in the Formation of MOS Devices
US20090101945A1 (en) Semiconductor device
JP2006269768A (en) Semiconductor device and its manufacturing method
CN102208349A (en) Method of manufacturing finned semiconductor device structure
US20090050965A1 (en) Semiconductor device and method of fabricating the same
CN102169853A (en) Method of forming an integrated circuit structure
CN102157381A (en) Method of manufacturing semiconductor device
JP2011165859A (en) Semiconductor device, and method of manufacturing the same
US8450166B2 (en) Method of fabricating semiconductor devices
US20120187501A1 (en) Semiconductor structure and method for manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
C14 Grant of patent or utility model