JP2009075973A5 - - Google Patents
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- JP2009075973A5 JP2009075973A5 JP2007246094A JP2007246094A JP2009075973A5 JP 2009075973 A5 JP2009075973 A5 JP 2009075973A5 JP 2007246094 A JP2007246094 A JP 2007246094A JP 2007246094 A JP2007246094 A JP 2007246094A JP 2009075973 A5 JP2009075973 A5 JP 2009075973A5
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- JP
- Japan
- Prior art keywords
- data
- unit
- data processing
- processing unit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 241000723353 Chrysanthemum Species 0.000 claims 2
- 235000007516 Chrysanthemum Nutrition 0.000 claims 2
- 238000007906 compression Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007246094A JP2009075973A (ja) | 2007-09-21 | 2007-09-21 | 電子機器及び当該電子機器の電力制御方法 |
| US12/200,751 US20090083559A1 (en) | 2007-09-21 | 2008-08-28 | Electronic device and method of controlling power thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007246094A JP2009075973A (ja) | 2007-09-21 | 2007-09-21 | 電子機器及び当該電子機器の電力制御方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2009075973A JP2009075973A (ja) | 2009-04-09 |
| JP2009075973A5 true JP2009075973A5 (enExample) | 2010-11-04 |
Family
ID=40472990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007246094A Pending JP2009075973A (ja) | 2007-09-21 | 2007-09-21 | 電子機器及び当該電子機器の電力制御方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20090083559A1 (enExample) |
| JP (1) | JP2009075973A (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090061515A (ko) * | 2007-12-11 | 2009-06-16 | 한국전자통신연구원 | Ｇａｌｓ 시스템용 접속회로 및 그의 동작방법 |
| JP5171770B2 (ja) | 2009-09-24 | 2013-03-27 | キヤノン株式会社 | 画像処理装置及びその制御方法 |
| JP5434812B2 (ja) | 2010-06-21 | 2014-03-05 | 富士通セミコンダクター株式会社 | データ処理システム |
| JP2013146053A (ja) * | 2011-12-16 | 2013-07-25 | Ricoh Co Ltd | 画像処理装置、画像処理回路及び画像処理装置の制御方法 |
| JP5842881B2 (ja) | 2013-08-20 | 2016-01-13 | コニカミノルタ株式会社 | 画像形成装置 |
| JP7022605B2 (ja) | 2018-01-26 | 2022-02-18 | キヤノン株式会社 | 情報処理装置とその制御方法、及びプログラム |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5227790A (en) * | 1991-01-31 | 1993-07-13 | Oki Electric Industry Co., Ltd. | Cascaded drive units having low power consumption |
| US5710910A (en) * | 1994-09-30 | 1998-01-20 | University Of Washington | Asynchronous self-tuning clock domains and method for transferring data among domains |
| JPH0954753A (ja) * | 1995-08-11 | 1997-02-25 | Toshiba Corp | 計算機バスシステム |
| US5815006A (en) * | 1996-04-25 | 1998-09-29 | Industrial Technology Research Institute | Single transition per evaluation phase latch circuit for pipelined true-single-phase synchronous logic circuit |
| JPH10240371A (ja) * | 1997-02-27 | 1998-09-11 | Mitsubishi Electric Corp | ディジタル信号処理プロセッサのクロック速度制御装置 |
| JPH1153049A (ja) * | 1997-08-05 | 1999-02-26 | Toshiba Corp | コンピュータシステム |
| JP2000029779A (ja) * | 1998-07-09 | 2000-01-28 | Ricoh Co Ltd | 画像処理装置 |
| JP2001005552A (ja) * | 1999-06-18 | 2001-01-12 | Nec Eng Ltd | 消費電力低減回路 |
| US6166564A (en) * | 1999-07-09 | 2000-12-26 | Intel Corporation | Control circuit for clock enable staging |
| JP3549471B2 (ja) * | 2000-08-08 | 2004-08-04 | 株式会社デジタル | 電子回路ブロック |
| JP2004274099A (ja) * | 2003-03-05 | 2004-09-30 | Nec Corp | パケット処理回路 |
| JP2004326222A (ja) * | 2003-04-22 | 2004-11-18 | Renesas Technology Corp | データ処理システム |
| US6853929B2 (en) * | 2003-05-01 | 2005-02-08 | Via Technologies, Inc. | Pipeline control for power management |
| TWI259659B (en) * | 2005-05-13 | 2006-08-01 | Ind Tech Res Inst | Pipelined datapath with dynamically reconfigurable pipeline stages |
| US7660183B2 (en) * | 2005-08-01 | 2010-02-09 | Rambus Inc. | Low power memory device |
| KR100719360B1 (ko) * | 2005-11-03 | 2007-05-17 | 삼성전자주식회사 | 디지털 로직 프로세싱 회로, 그것을 포함하는 데이터 처리 장치, 그것을 포함한 시스템-온 칩, 그것을 포함한 시스템, 그리고 클록 신호 게이팅 방법 |
| US8291256B2 (en) * | 2006-02-03 | 2012-10-16 | National University Corporation Kobe University | Clock stop and restart control to pipelined arithmetic processing units processing plurality of macroblock data in image frame per frame processing period |
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2007
- 2007-09-21 JP JP2007246094A patent/JP2009075973A/ja active Pending
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2008
- 2008-08-28 US US12/200,751 patent/US20090083559A1/en not_active Abandoned