JP2009038266A - 半導体装置及びその製造方法 - Google Patents
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
【解決手段】本発明は、基板10と、基板10上にフェースアップで搭載され、基板10とボンディングワイヤ28で電気的に接続された第1半導体チップ20と、第1半導体チップ20にフリップチップボンディングされた第2半導体チップ30と、第2半導体チップ30の側面を覆い、第1半導体チップ20上面のボンディングワイヤ28が電気的に接続された領域が露出するように第1半導体チップ20の上面を覆う絶縁性樹脂部40と、第1半導体チップ20、第2半導体チップ30およびボンディングワイヤ28を封止する封止樹脂部50と、を具備する半導体装置およびその製造方法である。
【選択図】図3
Description
20 第1半導体チップ
26 パッド
28 ボンディングワイヤ
30 第2半導体チップ
40 絶縁性樹脂部
48 非被覆領域
50 封止樹脂部
Claims (13)
- 基板と、
該基板上にフェースアップで搭載され、前記基板とボンディングワイヤで電気的に接続された第1半導体チップと、
該第1半導体チップにフリップチップボンディングされた第2半導体チップと、
前記第2半導体チップの側面を覆い、前記第1半導体チップ上面の前記ボンディングワイヤが電気的に接続された領域が露出するように前記第1半導体チップの上面を覆う絶縁性樹脂部と、
前記第1半導体チップ、前記第2半導体チップおよび前記ボンディングワイヤを封止する封止樹脂部と、
を具備することを特徴とする半導体装置。 - 前記第2半導体チップ上の前記絶縁性樹脂部の上面は第2半導体チップの上方から第2半導体チップが設けられていない周辺部にかけて平坦であることを特徴とする請求項1記載の半導体装置。
- 前記第2半導体チップの上面は前記絶縁性樹脂部から露出しており、前記絶縁性樹脂部の上面および前記第2半導体チップの上面は平坦であることを特徴とする請求項1記載の半導体装置。
- 前記第1半導体チップ上面の前記ボンディングワイヤが前記第1半導体チップに接続された領域から前記第1半導体チップの外側に至る非被覆領域には、前記絶縁性樹脂部が覆っておらず、
前記ボンディングワイヤは、前記非被覆領域上方を通過していることを特徴とする請求項1から3のいずれか一項記載の半導体装置。 - 前記第1半導体チップと前記第2半導体チップとの間を満たす接着剤を具備することを特徴とする請求項1から4のいずれか一項記載の半導体装置。
- 前記第2半導体チップ上に搭載された第3半導体チップを具備し、
前記封止樹脂部は前記第3半導体チップを封止していることを特徴とする請求項1から5のいずれか一項記載の半導体装置。 - 前記基板上に搭載されたダミースペーサを具備し、
前記第3半導体チップは、前記ダミースペーサおよび前記第2半導体チップ上に搭載されていることを特徴とする請求項6記載の半導体装置。 - 前記絶縁性樹脂部はボンディングワイヤが電気的に接続された領域を露出する開口部を有し、
前記開口部は、前記第1半導体チップの上面に形成された前記ボンディングワイヤが接続されたパッドを含むことを特徴とする請求項1から7のいずれか一項記載の半導体装置。 - 前記絶縁性樹脂部は感光性樹脂であることを特徴とする請求項1から8のいいずれか一項記載の半導体装置。
- ウエハ上に複数の第2半導体チップをフリップチップボンディングする工程と、
前記第2半導体チップを覆い、前記ウエハ上面のボンディングワイヤが電気的に接続される領域が露出するように、前記ウエハ上に絶縁性樹脂部を形成する工程と、
前記ウエハを個片化し、前記第2半導体チップが搭載された第1半導体チップを形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記個片化された第1半導体チップを基板に搭載する工程と、
前記第1半導体チップと前記基板とを前記ボンディングワイヤを用い電気的に接続する工程と、
前記第1半導体チップ、前記第2半導体チップおよび前記ボンディングワイヤを封止する工程と、
を有することを特徴とする請求項10記載の半導体装置の製造方法。 - 前記個片化された第1半導体チップを基板に搭載する工程の後に前記第2半導体チップ上に第3半導体チップを搭載する工程を有し、
前記第1半導体チップ、前記第2半導体チップおよび前記ボンディングワイヤを封止する工程は、前記第3半導体チップを封止する工程を含むことを特徴とする請求項11記載の半導体装置の製造方法。 - 前記第2半導体チップの上面が露出するように前記絶縁性樹脂部を研削する工程を有する請求項10から13のいずれか一項記載の半導体装置の製造方法。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011086611A1 (ja) * | 2010-01-14 | 2011-07-21 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US8703600B2 (en) | 2009-06-02 | 2014-04-22 | Kabushiki Kaisha Toshiba | Electronic component and method of connecting with multi-profile bumps |
WO2022044804A1 (ja) * | 2020-08-24 | 2022-03-03 | ソニーセミコンダクタソリューションズ株式会社 | センサデバイスおよび電子機器 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10335577A (ja) * | 1997-06-05 | 1998-12-18 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JPH11121686A (ja) * | 1997-10-21 | 1999-04-30 | Rohm Co Ltd | 多層チップの組み立て方法 |
JP2001230369A (ja) * | 2000-02-21 | 2001-08-24 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2002198487A (ja) * | 2000-12-26 | 2002-07-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005183934A (ja) * | 2003-11-28 | 2005-07-07 | Nec Electronics Corp | オフセット接合型マルチチップ半導体装置 |
JP2006108327A (ja) * | 2004-10-04 | 2006-04-20 | Sharp Corp | 半導体装置およびその製造方法並びに積層型半導体装置 |
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- 2007-08-03 JP JP2007202451A patent/JP4937856B2/ja not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10335577A (ja) * | 1997-06-05 | 1998-12-18 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JPH11121686A (ja) * | 1997-10-21 | 1999-04-30 | Rohm Co Ltd | 多層チップの組み立て方法 |
JP2001230369A (ja) * | 2000-02-21 | 2001-08-24 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2002198487A (ja) * | 2000-12-26 | 2002-07-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005183934A (ja) * | 2003-11-28 | 2005-07-07 | Nec Electronics Corp | オフセット接合型マルチチップ半導体装置 |
JP2006108327A (ja) * | 2004-10-04 | 2006-04-20 | Sharp Corp | 半導体装置およびその製造方法並びに積層型半導体装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8703600B2 (en) | 2009-06-02 | 2014-04-22 | Kabushiki Kaisha Toshiba | Electronic component and method of connecting with multi-profile bumps |
WO2011086611A1 (ja) * | 2010-01-14 | 2011-07-21 | パナソニック株式会社 | 半導体装置及びその製造方法 |
WO2022044804A1 (ja) * | 2020-08-24 | 2022-03-03 | ソニーセミコンダクタソリューションズ株式会社 | センサデバイスおよび電子機器 |
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