JP2009008891A5 - - Google Patents
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- JP2009008891A5 JP2009008891A5 JP2007170164A JP2007170164A JP2009008891A5 JP 2009008891 A5 JP2009008891 A5 JP 2009008891A5 JP 2007170164 A JP2007170164 A JP 2007170164A JP 2007170164 A JP2007170164 A JP 2007170164A JP 2009008891 A5 JP2009008891 A5 JP 2009008891A5
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Claims (9)
前記ソースドライバは、第１のビデオ信号出力回路と、第２のビデオ信号出力回路と、前記第１のビデオ信号出力回路の出力信号及び前記第２のビデオ信号出力回路の出力信号の中から前記画素部に出力する信号を選択する第１の選択回路と、を有し、
前記ゲートドライバは、第１の選択信号出力回路と、第２の選択信号出力回路と、前記第１の選択信号出力回路の出力信号及び前記第２の選択信号出力回路の出力信号の中から前記画素部に出力する信号を選択する第２の選択回路と、を有し、
前記制御回路は、前記第１のビデオ信号出力回路の出力信号と第１の基準となる信号とを比較する第１の比較回路と、前記第２のビデオ信号出力回路の出力信号と前記第１の基準となる信号とを比較する第２の比較回路と、前記第１の基準となる信号のデータが記憶された第１のメモリと、前記第１の比較回路の比較結果及び前記第２の比較回路の比較結果に応じた制御信号を前記第１の選択回路に出力する第１の比較結果判定回路と、前記第１の選択信号出力回路の出力信号と第２の基準となる信号とを比較する第３の比較回路と、前記第２の選択信号出力回路の出力信号と前記第２の基準となる信号とを比較する第４の比較回路と、前記第２の基準となる信号のデータが記憶された第２のメモリと、前記第３の比較回路の比較結果及び前記第４の比較回路の比較結果に応じた制御信号を前記第２の選択回路に出力する第２の比較結果判定回路と、を有することを特徴とする表示装置。 Includes a pixel portion having a plurality of pixels, and Seo Sudoraiba, a gate driver, and a control circuit,
The source driver includes a first video signal output circuit, and the second video signal output circuit, wherein from the output signal of the output signal and the second video signal output circuit of the first video signal output circuit A first selection circuit that selects a signal to be output to the pixel portion ,
The gate driver includes a first selection signal output circuit, a second selection signal output circuit, wherein among the first output signal and the output signal of the second selection signal output circuit of the selection signal output circuit possess a second selection circuit for selecting a signal to be output to the pixel portion,
The control circuit compares the output signal of the first video signal output circuit with the first reference signal, the output signal of the second video signal output circuit, and the first signal A second comparison circuit for comparing the reference signal of the first reference circuit, a first memory storing data of the first reference signal, a comparison result of the first comparison circuit, and the second comparison circuit A first comparison result determination circuit that outputs a control signal corresponding to a comparison result of the comparison circuit to the first selection circuit; an output signal of the first selection signal output circuit; and a second reference signal. Third comparison circuit for comparison, fourth comparison circuit for comparing the output signal of the second selection signal output circuit and the second reference signal, and data of the second reference signal And the comparison result of the second memory storing the third comparison circuit and the previous Display device characterized by having a second comparison result decision circuit for outputting a control signal according to the comparison result of the fourth comparator circuit to the second selection circuit.
前記第１の選択回路は、第１のクロックドインバータと、第２のクロックドインバータと、を有し、
前記第２の選択回路は、第３のクロックドインバータと、第４のクロックドインバータと、を有し、
前記第１のビデオ信号出力回路は、前記第１のクロックドインバータを介して前記画素部と電気的に接続され、
前記第２のビデオ信号出力回路は、前記第２のクロックドインバータを介して前記画素部と電気的に接続され、
前記第１の選択信号出力回路は、前記第３のクロックドインバータを介して前記画素部と電気的に接続され、
前記第２の選択信号出力回路は、前記第４のクロックドインバータを介して前記画素部と電気的に接続されることを特徴とする表示装置。 In claim 1 ,
The first selection circuit includes a first clocked inverter and a second clocked inverter,
The second selection circuit, possess a third clocked inverter, a fourth clocked inverter, a,
The first video signal output circuit is electrically connected to the pixel portion via the first clocked inverter,
The second video signal output circuit is electrically connected to the pixel portion via the second clocked inverter,
The first selection signal output circuit is electrically connected to the pixel portion via the third clocked inverter,
The display device, wherein the second selection signal output circuit is electrically connected to the pixel portion through the fourth clocked inverter .
前記画素部、前記第１のビデオ信号出力回路、前記第２のビデオ信号出力回路、前記第１の選択信号出力回路、及び前記第２の選択信号出力回路に用いられるトランジスタの半導体層には、絶縁表面を有する基板に剥離によって形成された単結晶半導体が用いられることを特徴とする表示装置。 In claim 1 or claim 2,
Semiconductor layers of transistors used in the pixel portion, the first video signal output circuit, the second video signal output circuit, the first selection signal output circuit, and the second selection signal output circuit include: A display device using a single crystal semiconductor formed by peeling on a substrate having an insulating surface .
前記ゲートドライバは、第１の選択信号出力回路と、第２の選択信号出力回路と、前記第１の選択信号出力回路の出力信号及び前記第２の選択信号出力回路の出力信号の中から前記画素部に出力する信号を選択する選択回路と、を有することを特徴とする表示装置。 Includes a pixel portion having a plurality of pixels, and gain gate driver, a,
The gate driver includes a first selection signal output circuit, a second selection signal output circuit, wherein among the first output signal and the output signal of the second selection signal output circuit of the selection signal output circuit And a selection circuit that selects a signal to be output to the pixel portion.
前記第１の選択信号出力回路の出力信号と基準となる信号とを比較する第１の比較回路と、前記第２の選択信号出力回路の出力信号と前記基準となる信号とを比較する第２の比較回路と、前記基準となる信号のデータが記憶されたメモリと、前記第１の比較回路の比較結果及び前記第２の比較回路の比較結果に応じた制御信号を前記選択回路に出力する比較結果判定回路と、を有することを特徴とする表示装置。 In claim 4 ,
Comparing a first comparison circuit for comparing the signal to be pre-SL output signal and the reference of the first selection signal output circuit, and a pre-SL signal as an output signal and the reference of the second selection signal output circuit a second comparator circuit, and a memory in which data of the signal serving as the reference is stored, a control signal corresponding to the comparison result of the comparison result and the second comparison circuit of said first comparator circuit to the selection circuit A display device comprising: a comparison result determination circuit for outputting.
前記画素部、前記第１の選択信号出力回路、及び前記第２の選択信号出力回路に用いられるトランジスタの半導体層には、酸化物半導体が用いられることを特徴とする表示装置。 In any one of Claims 1 to 5,
An oxide semiconductor is used for a semiconductor layer of a transistor used for the pixel portion, the first selection signal output circuit, and the second selection signal output circuit .
前記ソースドライバは、第１のビデオ信号出力回路と、第２のビデオ信号出力回路と、前記第１のビデオ信号出力回路の出力信号及び前記第２のビデオ信号出力回路の出力信号の中から前記画素部に出力する信号を選択する選択回路と、を有することを特徴とする表示装置。 Includes a pixel portion having a plurality of pixels, and source Sudoraiba and,
The source driver includes a first video signal output circuit, from among the second video signal output circuit and, before SL output signal of the output signal and the second video signal output circuit of the first video signal output circuit And a selection circuit that selects a signal to be output to the pixel portion.
前記第１のビデオ信号出力回路の出力信号と基準となる信号とを比較する第１の比較回路と、前記第２のビデオ信号出力回路の出力信号と前記基準となる信号とを比較する第２の比較回路と、前記基準となる信号のデータが記憶されたメモリと、前記第１の比較回路の比較結果及び前記第２の比較回路の比較結果に応じた制御信号を前記選択回路に出力する比較結果判定回路と、を有することを特徴とする表示装置。 In claim 7 ,
The comparing a first comparison circuit for comparing the signal to be output signal and the reference of the first video signal output circuit, and a pre-SL signal as an output signal and the reference of the second video signal output circuit and second comparison circuit, the output memory in which the data of the signal serving as the reference is stored, a control signal corresponding to the comparison result of the comparison result and the second comparison circuit of said first comparator circuit to the selection circuit And a comparison result determination circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007170164A JP5520437B2 (en) | 2007-06-28 | 2007-06-28 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007170164A JP5520437B2 (en) | 2007-06-28 | 2007-06-28 | Display device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009008891A JP2009008891A (en) | 2009-01-15 |
| JP2009008891A5 true JP2009008891A5 (en) | 2010-07-15 |
| JP5520437B2 JP5520437B2 (en) | 2014-06-11 |
Family
ID=40324030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007170164A Active JP5520437B2 (en) | 2007-06-28 | 2007-06-28 | Display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5520437B2 (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4277055B2 (en) | 2007-05-29 | 2009-06-10 | シャープ株式会社 | Drive circuit, display device, and television system |
| WO2009107469A1 (en) | 2008-02-28 | 2009-09-03 | シャープ株式会社 | Drive circuit, and display device |
| JP2010078870A (en) * | 2008-09-25 | 2010-04-08 | Sharp Corp | Display device, and television system |
| JP2010081254A (en) * | 2008-09-25 | 2010-04-08 | Sharp Corp | Display apparatus and television system |
| JP2010081255A (en) * | 2008-09-25 | 2010-04-08 | Sharp Corp | Display apparatus and television system |
| JP2010078869A (en) * | 2008-09-25 | 2010-04-08 | Sharp Corp | Display device, and television system |
| US8665201B2 (en) | 2008-10-10 | 2014-03-04 | Sharp Kabushiki Kaisha | Display device and method for driving display device |
| JP5786294B2 (en) * | 2010-08-31 | 2015-09-30 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
| WO2012157649A1 (en) * | 2011-05-18 | 2012-11-22 | シャープ株式会社 | Display device |
| JP6482847B2 (en) * | 2014-12-16 | 2019-03-13 | シチズンファインデバイス株式会社 | Liquid crystal display element and image projection system |
| WO2019017364A1 (en) * | 2017-07-21 | 2019-01-24 | シャープ株式会社 | Display device |
| EP4068262A4 (en) | 2019-11-27 | 2022-12-28 | BOE Technology Group Co., Ltd. | Display substrate and display device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60124715A (en) * | 1983-12-12 | 1985-07-03 | Mitsubishi Electric Corp | Power supply control circuit |
| JPS6225272A (en) * | 1985-07-26 | 1987-02-03 | Nec Corp | Gate array |
| JPS63204170A (en) * | 1987-02-18 | 1988-08-23 | Nec Corp | Semiconductor integrated circuit with testing mechanism |
| JPH04191680A (en) * | 1990-11-26 | 1992-07-09 | Mitsubishi Electric Corp | Semiconductor integrated circuit having incorporated self-diagnostic function |
| JPH06324651A (en) * | 1992-10-19 | 1994-11-25 | Fujitsu Ltd | Driving circuit of liquid crystal display device |
| JPH0850465A (en) * | 1994-05-30 | 1996-02-20 | Sanyo Electric Co Ltd | Shift register and driving circuit of display device |
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2007
- 2007-06-28 JP JP2007170164A patent/JP5520437B2/en active Active
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