JPS63204170A - Semiconductor integrated circuit with testing mechanism - Google Patents

Abstract

PURPOSE:To curtail necessary memory capacity, by placing a compression mechanism of information on results of test in front of an expected value collating section. CONSTITUTION:A control signal is inputted from a control signal input terminal 11 to operate selectors 4-1 and 4-2 with a controller 8, a circuit 3 to be tested is separated from an internal circuit 2 to fetch a test signal involved from a test signal generating memory section 7 and the signal is supplied to a circuit through the selector 4-1 to implement a function test. Then, the results of testing are inputted into a check sum generation circuit 13 through the selector 4-2 to weight (n) input signals as grouped by the number (m) and output signals are cut down to the number n/m to be inputted into an expected value collating section 5. The collating section 5 collates said output signals with a check sum expected value for the results of testing previously taken out of an expected value memory section 6 with the controller 8 and the results are outputted with an expected value collation results output terminal 12. Thus, necessary memory capacity can be curtailed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit with a test mechanism.

[Conventional technology]

In recent years, there has been an increasing market need to integrate existing programmable counters, DMA controllers, etc. into gate array integrated circuits, but test patterns for such additional circuits have been established. Therefore, semiconductor integrated circuits with a test mechanism have been commercialized in which the test mechanism is also provided within the same integrated circuit.

A conventional semiconductor integrated circuit of this type has one control signal input terminal 11 for each circuit under test, as shown in FIG.
In addition, the controller 8° test signal generation storage section 71 expected value storage section 61 expected value collation section 5 and selector 4
-1.4-2 was installed.

In FIG. 3, by inputting a control signal from the control signal input terminal 11-, the controller 8 is activated by the selector 4-.
1 and 4-2 to disconnect the circuit under test 3 from the internal circuit 2, take out the corresponding test signal from the test signal generation storage section 7, and supply it to the circuit under test 3 through the selector 4-1. A functional test of the circuit under test 3 is performed.

The test result is input to the expected value matching section 5 through the selector 4-2, and is compared with the test result expected value taken out from the expected value storage section 6 by the controller 8 in advance, and the matching result is outputted as the expected value matching result. It comes out from the terminal 12.

[Problem that the invention seeks to solve]

In the conventional semiconductor integrated circuit with a test mechanism described above,
The required storage capacity of the test signal generation storage section and the expected value storage section increases in proportion to the circuit scale of the circuit under test and the number of input/output signals. In particular, the expected value storage section has the disadvantage that the required capacity is enormous because it is necessary to store the expected test result values for all output signals of the circuit under test.

In contrast to the conventional semiconductor integrated circuit with a test mechanism described above, the present invention compresses the amount of information by placing a mechanism for compressing the amount of information of the test results from the circuit under test in front of the expected value matching section. It has an original content of preventing an increase in the capacity required for the value storage section.

[Means for solving problems]

The semiconductor integrated circuit of the present invention includes a storage section for generating test signals for the purpose of functional testing of an internal circuit under test.

In a semiconductor integrated circuit with a test mechanism equipped with an expected value storage section and an expected value comparison section, test result value compression is performed to compress the test result value output by the circuit under test in response to a test signal from the test signal generation storage section. The present invention is characterized in that a mechanism is provided, and the expected value matching section matches the compressed test result value with the corresponding expected value in the expected value storage section.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention, in which a checksum generation circuit 13 is introduced.

In Figure 1, 1 is the entire integrated circuit, 2 is the internal circuit, and 3 is the internal circuit.
is the circuit under test, 4-1 and 4-2 are selectors, 5 is an expected value comparison section, 6 is an expected value storage section, 7 is a storage section for test signal generation, 8 is a controller, 9 is an output terminal, and 10 is an input 11 is a control signal input terminal, 12 is an expected value comparison result output terminal, and 13 is a checksum generation circuit. Internal circuit 2 refers to a random logic section implemented by a gate array.

By inputting a control signal from the control signal input terminal 11, the controller 8 operates the selectors 4-1 and 4-2, disconnects the circuit under test 3 from the internal circuit 2, and selects the corresponding signal from the test signal generation storage section 7. A test signal is taken out and supplied to the circuit under test 3 through the selector 4-1 to perform a functional test on the circuit under test 3.

Next, the test result is input to the checksum generation circuit 13 through the selector 4-2, and this circuit converts the number of input signals to m.
By weighting each signal individually, the number of output signals is reduced to n/m, and this result is sent to the expected value comparison unit 5.
Enter.

The expected value matching section 52 matches the expected value of the test result obtained from the expected value storage section 6 by the controller 8 in advance with the output signal described in "1", and outputs the matching result from the expected value matching result output terminal 12. Output.

In this example, for the total number n of output signals of the circuit under test,
Since m checksums are generated in batches, the capacity required to store the expected value is n / compared to the conventional method.
This has the advantage of being reduced to less than m.

FIG. 2 shows a configuration diagram of a second embodiment in which a parity generation circuit 14 is introduced.

The test result of the circuit under test 3 outputted through the selector 4-2 is input to the parity generating circuit 14 to generate a parity of the test result, which is input to the expected value matching section 5 to generate the expected parity value. Verify with.

In this embodiment, since expected value verification is performed using the generated parity signal, the capacity required for storing expected values is reduced to 1/n or less when the total number of output signals of the circuit under test is n. There is an advantage.

〔Effect of the invention〕

As explained above, the present invention reduces the amount of memory required for the expected value storage section by placing a compression mechanism for test result information in the expected value matching section for the test results from the circuit under test. There are some effects that can be done.

This effect also has the additional effect of allowing a plurality of circuits under test within the integrated circuit to be simultaneously and independently tested.

[Brief explanation of the drawing]

FIG. 1 shows a first embodiment of the present invention, and FIG. 2 shows a second embodiment of the present invention.
Embodiment 1 and FIG. 3 respectively show a conventional example. DESCRIPTION OF SYMBOLS 1... Entire integrated circuit, 2... Internal circuit, 3... Circuit under test, l-1, 4-2... Selector, 5... Expected value comparison section, 6... Expected value Memory unit, 7... Memory unit for test signal generation, 8... Controller I to roller, 9... Output terminal, 10... Input terminal, 11... Control signal input terminal, ]-2. ...Expected value matching result output terminal, ]3...
- Checksum generation circuit, 14... Parity generation circuit.

Claims (1)

[Scope of Claims] A semiconductor integrated circuit with a test mechanism that includes a test signal generation storage section, an expected value storage section, and an expected value comparison section for the purpose of functional testing of an internal circuit under test, wherein the test signal generation storage section A test result value compression mechanism is provided for compressing the test result value output by the circuit under test in response to a test signal from the circuit under test, and the expected value collation unit compares the compressed test result value with the expected value storage unit. 1. A semiconductor integrated circuit with a test mechanism, characterized in that the circuit is compared with a corresponding expected value.