JP2007207413A5 - - Google Patents
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- JP2007207413A5 JP2007207413A5 JP2007000447A JP2007000447A JP2007207413A5 JP 2007207413 A5 JP2007207413 A5 JP 2007207413A5 JP 2007000447 A JP2007000447 A JP 2007000447A JP 2007000447 A JP2007000447 A JP 2007000447A JP 2007207413 A5 JP2007207413 A5 JP 2007207413A5
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- 239000004065 semiconductor Substances 0.000 claims 11
- 239000012212 insulator Substances 0.000 claims 2
- 239000003990 capacitor Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Claims (14)
前記第1のトランジスタは、第1端子が前記第1の配線に電気的に接続され、第2端子が前記第2のトランジスタの第2端子に電気的に接続され、ゲート端子が前記第4のトランジスタのゲート端子に電気的に接続され、
前記第2のトランジスタは、第1端子が前記第2の配線に電気的に接続され、ゲート端子が前記第3のトランジスタの第2端子に電気的に接続され、
前記第3のトランジスタは、第1端子が前記第3の配線に電気的に接続され、ゲート端子が前記第4のトランジスタの第2端子、及び前記第5のトランジスタの第2端子に電気的に接続され、
前記第4のトランジスタは、第1端子が前記第2の配線に電気的に接続され、
前記第5のトランジスタは、第1端子が前記第4の配線に電気的に接続され、ゲート端子が前記第4の配線に電気的に接続され、
前記第1のトランジスタのゲート端子は、当該ゲート端子を浮遊状態にするためのトランジスタに電気的に接続されていることを特徴とする半導体装置。 The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the first wiring, the second wiring, the third wiring, and the fourth With wiring of
The first transistor has a first terminal electrically connected to the first wiring, a second terminal electrically connected to a second terminal of the second transistor, and a gate terminal connected to the fourth terminal. Electrically connected to the gate terminal of the transistor,
The second transistor has a first terminal electrically connected to the second wiring, a gate terminal electrically connected to the second terminal of the third transistor,
The third transistor has a first terminal electrically connected to the third wiring, and a gate terminal electrically connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor. Connected,
The fourth transistor has a first terminal electrically connected to the second wiring,
The fifth transistor has a first terminal electrically connected to the fourth wiring, a gate terminal electrically connected to the fourth wiring,
The semiconductor device is characterized in that the gate terminal of the first transistor is electrically connected to a transistor for bringing the gate terminal into a floating state.
前記第1のトランジスタは、第1端子が前記第1の配線に電気的に接続され、第2端子が前記第2のトランジスタの第2端子に電気的に接続され、ゲート端子が前記第4のトランジスタのゲート端子、及び前記第6のトランジスタの第2端子に電気的に接続され、
前記第2のトランジスタは、第1端子が前記第2の配線に電気的に接続され、ゲート端子が前記第3のトランジスタの第2端子に電気的に接続され、
前記第3のトランジスタは、第1端子が前記第3の配線に電気的に接続され、ゲート端子が前記第4のトランジスタの第2端子、及び前記第5のトランジスタの第2端子に電気的に接続され、
前記第4のトランジスタは、第1端子が前記第2の配線に電気的に接続され、
前記第5のトランジスタは、第1端子が前記第4の配線に電気的に接続され、ゲート端子が前記第4の配線に電気的に接続され、
前記第6のトランジスタは、第1端子が前記第4の配線に電気的に接続され、ゲート端子が前記第5の配線に電気的に接続されていることを特徴とする半導体装置。 The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the first wiring, the second wiring, and the third Wiring, fourth wiring, and fifth wiring,
The first transistor has a first terminal electrically connected to the first wiring, a second terminal electrically connected to a second terminal of the second transistor, and a gate terminal connected to the fourth terminal. Electrically connected to a gate terminal of the transistor and a second terminal of the sixth transistor;
The second transistor has a first terminal electrically connected to the second wiring, a gate terminal electrically connected to the second terminal of the third transistor,
The third transistor has a first terminal electrically connected to the third wiring, and a gate terminal electrically connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor. Connected,
The fourth transistor has a first terminal electrically connected to the second wiring,
The fifth transistor has a first terminal electrically connected to the fourth wiring, a gate terminal electrically connected to the fourth wiring,
The semiconductor device, wherein the sixth transistor has a first terminal electrically connected to the fourth wiring and a gate terminal electrically connected to the fifth wiring.
前記第1のトランジスタは、第1端子が前記第1の配線に電気的に接続され、第2端子が前記第2のトランジスタの第2端子に電気的に接続され、ゲート端子が前記第4のトランジスタのゲート端子、前記第6のトランジスタの第2端子、及び前記第7のトランジスタの第2端子に電気的に接続され、
前記第2のトランジスタは、第1端子が前記第2の配線に電気的に接続され、ゲート端子が前記第3のトランジスタの第2端子、及び前記第7のトランジスタのゲート端子に電気的に接続され、
前記第3のトランジスタは、第1端子が前記第3の配線に電気的に接続され、ゲート端子が前記第4のトランジスタの第2端子、及び前記第5のトランジスタの第2端子に電気的に接続され、
前記第4のトランジスタは、第1端子が前記第2の配線に電気的に接続され、
前記第5のトランジスタは、第1端子が前記第4の配線に電気的に接続され、ゲート端子が前記第4の配線に電気的に接続され、
前記第6のトランジスタは、第1端子が前記第4の配線に電気的に接続され、ゲート端子が前記第5の配線に電気的に接続され、
前記第7のトランジスタは、第1端子が前記第2の配線に電気的に接続されていることを特徴とする半導体装置。 A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first wiring, and a second wiring; Wiring, third wiring, fourth wiring, and fifth wiring,
The first transistor has a first terminal electrically connected to the first wiring, a second terminal electrically connected to a second terminal of the second transistor, and a gate terminal connected to the fourth terminal. Electrically connected to a gate terminal of a transistor, a second terminal of the sixth transistor, and a second terminal of the seventh transistor;
The second transistor has a first terminal electrically connected to the second wiring, and a gate terminal electrically connected to the second terminal of the third transistor and the gate terminal of the seventh transistor. And
The third transistor has a first terminal electrically connected to the third wiring, and a gate terminal electrically connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor. Connected,
The fourth transistor has a first terminal electrically connected to the second wiring,
The fifth transistor has a first terminal electrically connected to the fourth wiring, a gate terminal electrically connected to the fourth wiring,
The sixth transistor has a first terminal electrically connected to the fourth wiring , a gate terminal electrically connected to the fifth wiring,
In the semiconductor device, the first transistor has a first terminal electrically connected to the second wiring.
前記第1のトランジスタは、第1端子が前記第1の配線に電気的に接続され、第2端子が前記第2のトランジスタの第2端子に電気的に接続され、ゲート端子が前記第4のトランジスタのゲート端子、前記第6のトランジスタの第2端子、前記第7のトランジスタの第2端子、及び前記第8のトランジスタの第2端子に電気的に接続され、
前記第2のトランジスタは、第1端子が前記第2の配線に電気的に接続され、ゲート端子が前記第3のトランジスタの第2端子、及び前記第7のトランジスタのゲート端子に電気的に接続され、
前記第3のトランジスタは、第1端子が前記第3の配線に電気的に接続され、ゲート端子が前記第4のトランジスタの第2端子、及び前記第5のトランジスタの第2端子に電気的に接続され、
前記第4のトランジスタは、第1端子が前記第2の配線に電気的に接続され、
前記第5のトランジスタは、第1端子が前記第4の配線に電気的に接続され、ゲート端子が前記第4の配線に電気的に接続され、
前記第6のトランジスタは、第1端子が前記第4の配線に電気的に接続され、ゲート端子が前記第5の配線に電気的に接続され、
前記第7のトランジスタは、第1端子が前記第2の配線に電気的に接続され、
前記第8のトランジスタは、第1端子が前記第2の配線に電気的に接続され、ゲート端子が前記第6の配線に電気的に接続されていることを特徴とする半導体装置。 A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a first transistor; A wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring,
The first transistor has a first terminal electrically connected to the first wiring, a second terminal electrically connected to a second terminal of the second transistor, and a gate terminal connected to the fourth terminal. Electrically connected to a gate terminal of a transistor, a second terminal of the sixth transistor, a second terminal of the seventh transistor, and a second terminal of the eighth transistor;
The second transistor has a first terminal electrically connected to the second wiring, and a gate terminal electrically connected to the second terminal of the third transistor and the gate terminal of the seventh transistor. And
The third transistor has a first terminal electrically connected to the third wiring, and a gate terminal electrically connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor. Connected,
The fourth transistor has a first terminal electrically connected to the second wiring,
The fifth transistor has a first terminal electrically connected to the fourth wiring, a gate terminal electrically connected to the fourth wiring,
The sixth transistor has a first terminal electrically connected to the fourth wiring , a gate terminal electrically connected to the fifth wiring,
The seventh transistor has a first terminal electrically connected to the second wiring,
The semiconductor device, wherein the eighth transistor has a first terminal electrically connected to the second wiring and a gate terminal electrically connected to the sixth wiring.
前記第4のトランジスタのチャネル長Lとチャネル幅Wの比W/Lは、前記第5のトランジスタのチャネル長Lとチャネル幅Wの比W/Lの10倍以上であることを特徴とする半導体装置。 In claims 1 to 4 Neu deviation or claim,
The ratio W / L of the channel length L to the channel width W of the fourth transistor is 10 times or more the ratio W / L of the channel length L to the channel width W of the fifth transistor apparatus.
前記第1のトランジスタ及び前記第3のトランジスタは、同じ導電型であることを特徴とする半導体装置。 In claims 1 to 5 gall deviation or claim,
The semiconductor device, wherein the first transistor and the third transistor have the same conductivity type.
前記第1のトランジスタ及び前記第3のトランジスタは、Nチャネル型であることを特徴とする半導体装置。 In claims 1 to 6 Neu deviation or claim,
The semiconductor device, wherein the first transistor and the third transistor are n-channel transistors.
前記第1のトランジスタの第2端子と、前記第1のトランジスタのゲート端子との間に電気的に接続された容量素子が設けられていることを特徴とする半導体装置。 In claims 1 to 7 Neu deviation or claim,
A semiconductor device, wherein a capacitor element electrically connected is provided between a second terminal of the first transistor and a gate terminal of the first transistor.
前記容量素子は、第1の電極と、第2の電極と、前記第1の電極と前記第2の電極とに挟持された絶縁体とを有し、前記第1の電極が半導体層であり、前記第2の電極がゲート配線層であり、前記絶縁体がゲート絶縁膜であることを特徴とする半導体装置。 In claim 8 ,
The capacitive element includes a first electrode, a second electrode, and a first electrode and the second electrode and the sandwiched an insulator, the first electrode is located in the semiconductor layer The semiconductor device is characterized in that the second electrode is a gate wiring layer and the insulator is a gate insulating film.
前記第1の配線には、クロック信号が供給され、前記第3の配線には、反転クロック信号が供給されていることを特徴とする半導体装置。 In claims 1 to 9 Neu deviation or claim,
A semiconductor device, wherein a clock signal is supplied to the first wiring and an inverted clock signal is supplied to the third wiring.
前記画素は、前記駆動回路により制御されることを特徴とする表示装置。 Includes a drive circuit having a semiconductor device according to claims 1 to 10, and a plurality of pixels,
The display device, wherein the pixel is controlled by the driving circuit.
前記画素はトランジスタを有し、
前記画素が有するトランジスタと、前記駆動回路が有するトランジスタとは、同じ導電型であることを特徴とする表示装置。 In claim 11 ,
The pixel has a transistor;
The display device, wherein the transistor included in the pixel and the transistor included in the driver circuit have the same conductivity type.
前記画素は、前記駆動回路と同一基板上に設けられていることを特徴とする表示装置。 In claim 11 or claim 12 ,
The display device is characterized in that the pixel is provided over the same substrate as the driving circuit.
Priority Applications (1)
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JP2007000447A JP5164383B2 (en) | 2006-01-07 | 2007-01-05 | Semiconductor device, display device, liquid crystal display device, display module, and electronic apparatus |
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JP2006001941 | 2006-01-07 | ||
JP2006001941 | 2006-01-07 | ||
JP2007000447A JP5164383B2 (en) | 2006-01-07 | 2007-01-05 | Semiconductor device, display device, liquid crystal display device, display module, and electronic apparatus |
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JP2012083448A Division JP5371158B2 (en) | 2006-01-07 | 2012-04-02 | Semiconductor device, display device, liquid crystal display device, display module, and electronic apparatus |
JP2012188696A Division JP5634457B2 (en) | 2006-01-07 | 2012-08-29 | Semiconductor device |
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JP2007207413A JP2007207413A (en) | 2007-08-16 |
JP2007207413A5 true JP2007207413A5 (en) | 2010-02-12 |
JP5164383B2 JP5164383B2 (en) | 2013-03-21 |
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