JPH06324651A - Driving circuit of liquid crystal display device - Google Patents

Abstract

PURPOSE:To avoid the influence of a defect of a shift register with simple constitution by selectively using the outputs of plural delay elements as the outputs of respective stages with a select signal which is common to the respective stages. CONSTITUTION:The driving circuit which drives the display elements of the liquid crystal display device has a shift register means which outputs (n) control signals for driving (n) signal lines coupled with the display elements, and the circuits in the respective stages of the shift register means delay input signals to the circuits by a unit time. Further, the circuit has plural delay elements 9ij (i=1-n and j=1-k) which are connected in parallel and selecting means 10i which select one of the output signals of the delay elements 9ij as a control circuit outputted by the circuit, and selecting means 10i of the circuits of the respective stages operate according to the select signal S which is common to the respective stages. Then this circuit has redundant constitution including plural delay elements 9ij for each stage and the outputs of the delay elements 9ij are selectively used as the outputs of the respective stages with the select signal S which is common to the respective stages.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used by being integrated on a so-called active matrix type liquid crystal display panel in which liquid crystal display panels each pixel (display element) arranged in a matrix form perform a storage operation. The present invention relates to a drive circuit of a liquid crystal display device.

An active matrix type liquid crystal display device can obtain a display quality comparable to that of a CRT display device having a CRT (cathode ray tube).
It is regarded as a promising display device as a substitute for the display device.

Here, the liquid crystal display device requires a drive circuit for driving the data lines and the scanning lines. An active matrix liquid crystal display device in which the drive circuit is integrated on a liquid crystal display panel. Has already been put into practical use as a viewfinder for video cameras.

As described above, in the liquid crystal display device in which the driving circuit is integrated on the liquid crystal display panel, the driving circuit is TAB.
(Tape automated bonding) and COG (chip on glass)
Compared with a liquid crystal display device that is externally mounted on a liquid crystal display panel by mounting technology such as the above, it is advantageous in terms of downsizing, high definition, and cost reduction.

Therefore, in recent years, it has been strongly demanded to put an active matrix type liquid crystal display device, in which the drive circuit is integrated on a liquid crystal display panel, into practical use as a display device for an information terminal.

Here, in the active matrix type liquid crystal display device which has been put to practical use as a viewfinder, since the display area is only about 1 inch, the scale of the drive circuit can be small and the defect of the drive circuit can be prevented. Probability is low.

On the other hand, in the active matrix type liquid crystal display device for information terminals, since a large display area is required, the scale of the drive circuit becomes large and the probability of occurrence of defects in the drive circuit becomes high.

Here, in an active matrix type liquid crystal display device in which a drive circuit is integrated in a liquid crystal display panel, when a defect occurs in the drive circuit, the device itself including the liquid crystal display panel becomes a defective product. I will end up.

Therefore, in this type of liquid crystal display device, it is necessary to configure the drive circuit so that when a defect occurs in the drive circuit, the defect can be repaired and corrected as much as possible.

[0010]

2. Description of the Related Art FIG. 41 shows the structure of a liquid crystal display device which is integrated and used on an active matrix type liquid crystal display panel. On the liquid crystal display panel 1, a liquid crystal display unit LDP having liquid crystal pixels arranged in a matrix, a timing generation circuit GEN, a data line drive circuit DDC,
The scanning line drive circuit SDC is integrated and formed.

The timing generation circuit GEN receives the timing signal TMG from the outside and receives the data line drive circuit DD.
The start signal SI and the clock signal CLK are output to C,
The start signal SI ′ and the clock signal CLK ′ are output to the scanning line drive circuit SDC. These signals are synchronized with each other. The data line drive circuit DDC further receives the display data D and the voltage signal V, and drives the data lines (column electrodes) DL coupled to the liquid crystal pixels LP arranged in a matrix. The scanning line driving circuit SDC drives the scanning lines (row electrodes) SL coupled to the liquid crystal pixels LP. Each liquid crystal pixel LP is provided with a transistor TR and a capacitor C, and these form one display element. The drain of the transistor TR is connected to the data line DL, and the gate is the scanning line SL.
Connected to. The capacitor C is connected between the source and the back gate (grounded). One end of the liquid crystal pixel LP is connected to the source of the transistor TR, and the other end is set to the reference potential.

FIG. 42 shows a structure of data line drive circuit DDC shown in FIG.

In the figure, 2 ₁ , 2 ₂ ... 2 _n are data lines (corresponding to DL in FIG. 41), 3 is a start signal SI supplied every horizontal scanning period in synchronization with a clock signal CLK. It is a serial input / parallel output type shift register for shifting.

Also, 4₁, 4₂... 4_nIs shift register
Output Q of star 3₁, Q₂... Q_n1 pixel in sync with
Digital image signals DI of
Drive voltage (grayscale voltage) V corresponding to signal DI₀, V₁・
..V_mData line 2₁, 2 ₂... 2_nDrive to output to
This is a dynamic voltage output circuit.

FIG. 43 shows a conventional data line driving circuit configured to repair defects in the shift register 3 as much as possible.
There has been proposed one showing the circuit configuration of the shift register section.

In the figure, reference numerals 5 _{1 to} 5 ₄ are regular registers having a 1-bit structure, which are D flip-flops, and 6 _{1 to} 6 ₄ are D flip-flops provided corresponding to the regular registers 5 _{1 to} 5 ₄ , respectively. It is a spare register having a 1-bit configuration.

The regular registers 5 _{1 to} 5 ₄ are connected in cascade, and the spare registers 6 _{1 to} 6 ₄ have their input terminals connected to the input terminals of the regular registers 5 _{1 to} 5 ₄ , respectively. The output terminal is open.

That is, in this shift register, if the normal registers 5 _{1 to} 5 ₄ are not defective, these normal registers 5 _{1 to} 5 ₄ are used as they are, and the normal registers 5 ₁ to 5 ₄
If any of 5 ₄ is defective, the corresponding spare registers 6 _{1 to} 6 ₄ are used to correct the defect.

[0019] For example, when there is a defect in the registers 5 ₂ regular is a suitable point 7 of the normal register 5 _{and second} output lines cut by a laser or the like, provided as a spare of the normal register 5 ₂ The output terminal of the existing register 6 ₂ is welded to the input wiring of the regular register 5 ₃ as indicated by the broken line 8 to correct the defect.

[0020]

Here, although the wiring can be cut relatively easily, the welding of the wiring is extremely difficult, and as described above, the regular register of the output terminal of the spare register 6 ₂ is used. It is not possible to easily weld 5 _{3 to} the input wiring.

In view of the above point, the present invention is a drive circuit for a liquid crystal display device integrated and used in an active matrix type liquid crystal display panel, and a defect within a certain range can be easily repaired or corrected. It is an object of the present invention to provide a drive circuit of a liquid crystal display device which can be manufactured.

[0022]

The invention according to claim 1 is
Corresponding to the first, second and third embodiments shown in FIGS. 1, 4 and 7, in a drive circuit for driving a display element of a liquid crystal display device, n signal lines coupled to the display element are driven. A shift register means for outputting n control signals for delaying the input signal of the shift register means by a unit time to delay a plurality of delay elements connected in parallel ( 9 _ij ; 11 _ij ; 13 _ij : i = 1-n, j
= 1-k) and selecting means (10 _i ; 12 _i ; 14 _i ) for selecting any of the output signals of the plurality of delay elements as a control signal output from the circuit, and each stage The circuit selecting means is configured to operate according to a selection signal (S; SEL) common to each stage.

The invention according to claim 4 corresponds to the fourth, fifth and sixth embodiments shown in FIGS. 10, 12 and 17, and in a drive circuit for driving a display element of a liquid crystal display device, the display element is Has shift register means for outputting n control signals for driving n signal lines coupled to each other, and each stage circuit of the shift register means delays an input signal of the circuit by a unit time. , A plurality of delay elements (15 _ij ; 18 _ij ; 22 _ij ) connected in parallel, and one of the output signals of the plurality of delay elements according to the selection signal, which is used as a control signal output from the circuit. Selection means (16 _i ; 20; 2
5) and defect detecting means (1) for detecting at least one defect of the plurality of delay elements and generating the selection signal.
7 _i ; 21; 26).

The invention according to claim 7 is based on FIG. 19 and FIG.
In the drive circuit for driving the display element of the liquid crystal display device corresponding to the seventh and eighth embodiments shown in FIG. 2, n normal drive circuits (2) for driving n signal lines coupled to the display element are provided.
9 _i ), n pre-driving circuits (30 _i ) provided for every n normal driving circuits, and control means (2) for outputting control signals for controlling the operations of the n normal driving circuits, respectively.
8), and defect detection means (32 _i ) for detecting defects of n normal driving circuits and outputting n selection signals, respectively.
Each of the n signal lines has a selecting means (31 _i ) for connecting either the normal drive circuit or the preliminary drive circuit to the signal line in accordance with the corresponding selection signal.

The invention as defined in claim 8 is shown in FIGS. 24 and 28.
In the drive circuit for driving the display element of the liquid crystal display device corresponding to the ninth and tenth embodiments shown in FIG. 1, n normal drive circuits (DR) for driving n signal lines coupled to the display element are provided.
1, DR2), a preliminary drive circuit (DS1) provided for each of m (m <n) normal drive circuits, and control means for outputting a control signal for controlling the operation of each of the n normal drive circuits. (CNTL), first switch means (SW11, SW21) for connecting n normal driving circuits to corresponding n signal lines, and the pre-driving circuit and m normal driving circuits. Second switch means (SW12, SW22) for selectively applying the control signal, and third switch means (SW13, SW13, for selectively connecting the preliminary drive circuit to the signal lines related to the m normal drive circuits.
SW23) and the respective defects of the m normal driving circuits are detected, and when a defect is detected in any one of the m normal driving circuits, the defect corresponds to the normal driving circuit in which the defect is detected. The configuration includes defect detection means (DD1, DD2) for controlling the first, second and third switch means so that the preliminary drive circuit drives the signal line.

The invention as defined in claim 10 is shown in FIGS. 29 and 3.
In the drive circuit for driving the display elements of the liquid crystal display device, corresponding to the eleventh and twelfth embodiments shown in FIG. 3, n driving for driving the n signal lines coupled to the display elements including the redundant display elements. Defect detection means (DD1-D) for detecting defects in each of the circuits (DR1-DR3) and the n driving circuits.
D3) and a control means (CNTL) for controlling the operation of the n drive circuits so that the display is performed only by the normal drive circuits other than the drive circuit in which the defect is detected.

The thirteenth aspect of the present invention corresponds to the thirteenth and fourteenth examples shown in FIGS. 36 and 39, and in the drive circuit for driving the display element of the liquid crystal display device, n is coupled to the display element. Shift register means (411, 41) for outputting n control signals for driving one signal line
2, 413), and the circuit of each stage of the shift register means delays the input signal of the circuit by a unit time, and a plurality of delay elements (221, 222, 22) connected in parallel.
k) and a majority decision of the output signals of the plurality of delay elements,
A majority decision processing means (20) which is used as a control signal output from the circuit.
3) and.

[0028]

According to the first aspect of the present invention, the redundant configuration has a plurality of delay elements for each stage, and the output of each stage selectively uses the output of the plurality of delay elements by the selection signal common to each stage. Therefore, it is possible to easily avoid the influence of defects in the shift register with a simple configuration without cutting or welding the wiring.

According to the invention described in claim 4, the defect detecting means is provided in each stage of the shift register to perform control for selecting one of the plurality of delay elements having a redundant configuration. Therefore,
Even if the shift register has a defect, it is possible to automatically avoid the influence of the defect and ensure normal operation.

According to a seventh aspect of the present invention, the drive circuit for receiving the control signal from the control means (corresponding to the shift register) to drive the signal line has a redundant structure, and if the normal drive circuit has a defect, the defect detection means operates. Based on this, the pre-driving circuit is automatically selected. Therefore, even if the normal drive circuit is defective, normal operation can be ensured.

According to the eighth aspect of the present invention, a preliminary drive circuit is provided for each of the m normal drive circuits, and the defect is generated by the action of the first, second and third switch means under the control of the defect detection means. One normal drive circuit with is automatically switched to the preliminary drive circuit. Therefore, as compared with the invention described in claim 7, it is possible to automatically avoid the influence of the defect of the normal drive circuit and secure the normal operation with a configuration having a small degree of redundancy.

According to the tenth aspect of the invention, the control means operates so as to jump over the defective signal line and display the data. For this reason, the display elements are provided with redundancy in advance so that they can be displayed in a range larger than a predetermined display area in the row and / or column direction. Therefore, the defect detection operation is not required, and even when a defect occurs, the row or column having the defective display element is not displayed, but the display information can be displayed in an identifiable state.

According to the thirteenth aspect of the present invention, the output of each stage of the shift register is determined by the majority of the input signals. Therefore, it is not necessary to inspect a defect, and when a defect is generated, the correct operation can be automatically continued without being affected by the defect.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a diagram for explaining the principle of the first embodiment of the present invention, in which a start signal SI necessary for horizontal scanning or vertical scanning is supplied as an input signal in a drive circuit. 1 shows a circuit configuration of a parallel output type shift register.

In the figure, 9 _{11 to} 9 ₄₁ and 9 _{12 to} 9 ₄₂ are, for example,
1-bit register consisting of D flip-flops,
Switching means 10 ₁ to 10 ₄ are turned on and off by a common control signal S.

Here, the registers 9 ₁₁ and 9 ₁₂ and the switching means 10 ₁ constitute a first stage portion, and the registers 9 ₂₁ and 9 ₂₂ and the switching means 10 ₂ constitute a second stage portion. is a register 9 _31, 9 _32, portions of the third stage by the switching means ₁₀₃ is configured, the register 9 _41,
9 ₄₂ and the switching means 10 ₄ constitute a fourth stage portion.

That is, in the drive circuit of the liquid crystal display device according to the first embodiment, a serial input / parallel output type shift register to which a start signal SI required for horizontal scanning or vertical scanning is supplied, a register 9 _i1, and a register 9 _i1 . 9 _i2 and a switching means 1 whose on / off is controlled by a common control signal S
The circuit is formed by connecting in parallel a series circuit composed of 0 _i in parallel. Note that i = a positive integer.

In the active matrix type liquid crystal display device in which the first embodiment is integrated on the liquid crystal display panel, first, the switching means 10 ₁ to 10 _{4 are} operated by the control signal S.
With the switch off, the display inspection of the liquid crystal display panel is performed.

As a result of this display inspection, if there is no abnormality in the display, the registers 9 _{11 to} 9 ₄₁ are considered to be defect-free, and the switching means 10 ₁ to 10 ₄ are turned off during normal operation.

On the other hand, for example, when it is detected that the register 9 ₂₁ has a defect, the output wiring of the register 9 ₂₁ is cut at the point A, and the switching means 10 _1-10.
Turn on ₄ and continue the display inspection.

As a result, for example, when it is detected that the register 9 ₃₂ is defective, the output wiring of the register 9 ₃₂ is cut at the point B, the switching means 10 ₁ to 10 ₄ are turned on, and the display is performed. Continue the inspection.

Thus, in the first embodiment,
The repair of the defects in the shift register.
It In this case, switching operation should be performed during normal operation.
Step 10 ₁-10_FourIs turned on.

Thus, according to this first embodiment,
Register 9 that constitutes 1-bit part _i1, 9_i2One of
If there is a defect in the output of the defective register
Ensure normal operation by cutting the wiring
Welding of wiring is necessary for repairing and repairing defects.
It does not require work.

Second Embodiment FIG. 2 is a diagram for explaining the principle of the second embodiment. FIG. 2 (a) is a serial circuit in which a start signal SI necessary for horizontal scanning or vertical scanning is supplied as an input signal in the drive circuit. A circuit configuration of an input / parallel output type shift register is shown, and FIG. 2B shows its operation.

In the figure, 11 _{11 to} 11 ₄₁ , 11 _{12 to} 11
Reference numeral ₄₂ is a 1-bit register composed of, for example, a D flip-flop, and reference numerals 12 _{1 to} 12 ₄ are 2-input selectors whose selection operation is controlled by a selection signal SEL.

Here, the registers 11 ₁₁ and 11 ₁₂ and the selector 12 ₁ constitute a first-stage portion.
₂₁ and 11 ₂₂ and the selector 12 ₂ constitute a second-stage portion, and the registers 11 ₃₁ and 11 ₃₂ and the selector 12 ₃ constitute a third-stage portion, and the registers 11 ₄₁ and 11 ₄₂ g,
4-stage portion in a selector 12 ₄ is constituted.

That is, in the drive circuit of the liquid crystal display device according to the second embodiment, a serial input / parallel output type shift register to which a start signal SI required for horizontal scanning or vertical scanning is supplied is connected to its input terminals. Registers 11 _i1 , 11
_A circuit composed of _i2 and a selector 12 _i , which selects and outputs the outputs of these registers 11 _i1 and 11 _i2 and whose selection operation is controlled by a common selection signal SEL, is formed by cascade connection. Note that i = a positive integer.

Even in the active matrix type liquid crystal display device in which the second embodiment is integrated on the liquid crystal display panel, the defective register can be detected by performing the display inspection.

Here, for example, when it is detected that the second-stage and third-stage registers 11 ₂₁ and 11 ₃₂ are defective, as shown in FIG. 2B, the level of the selection signal SEL is set. By controlling the selectors 12 _{1 to} 12 ₄ by changing the value, normal operation can be ensured.

That is, the second-stage portion comes out of the first-stage portion.
The period in which the input start signal SI should be latched and output
T₂, The level of the selection signal SEL is set to the selector
12 ₁~ 12_FourAre each register 11₁₂~ 11₄₂Choose
Select the level to be selected, for example, H level, and register 11
_{twenty two}The start signal SI latched by the selector
12₂Output via.

The third stage portion is the register 1 of the second stage.
In a period T ₃ which latches and outputs a start signal SI output from the 1 _22, the level of the selection signal SEL,
The selectors 12 _{1 to} 12 ₄ have registers 11 ₁₁ to 1 respectively.
1 ₄₁ is set to a level to be selected, for example, L level, and the start signal latched by the register 11 ₃₁ is output via the selector 12 ₃ .

The defect of the registers 11 ₂₁ and 11 ₃₂ is L.
In the case of a level-fixed defect, the output of the first stage and the output of the fourth stage are at the L level regardless of whether the selection signal SEL is at the H level or the L level during the period other than the periods T ₂ and T _3. Therefore, either one may be selected. Figure 2
The shaded portion of the waveform of the selection signal SEL in (b) indicates this.

The defect of the registers 11 ₂₁ and 11 ₃₂ is H.
In the case of a level fixed defect, the function of the shift register can be fulfilled by inverting the polarity of the start signal SI and operating in negative logic.

According to the second embodiment, when any of the registers 11 _i1 and 11 _i2 forming the 1-bit portion is defective, the selection signal SEL is set so that the output of the defective register is not selected. By changing the level, normal operation can be ensured, and the work of cutting the wiring or welding the wiring is not necessary to repair or correct the defect.

FIG. 3 is a diagram showing a main part of the second embodiment of the present invention, and shows a circuit configuration of a part of a shift register included in the second embodiment.

In the figure, 33 ₁₁ and 33 ₁₂ are registers in the first stage, and 33 ₂₁ and 33 ₂₂ are registers in the second stage.
41 is an nMOS transistor, 42 to 49 are inverters, φ ₁ is an nMOS transistor 35, 37, 39, 4
1 is a register control signal for controlling ON / OFF, φ ₂ is n
This is a register control signal for controlling ON / OFF of the MOS transistors 34, 36, 38, 40.

Further, 50 ₁ is a selector of the first stage, and 50 ₂
Is a second-stage selector, 51 to 54 are nMOS transistors, SEL is a selection signal for controlling on / off of the nMOS transistors 51 and 53, and / SEL is a selection signal for controlling on / off of the nMOS transistors 52 and 54. This is a selection signal having an inverted relationship with SEL.

FIG. 4 is a waveform diagram showing the operation of the second embodiment, in which the inverter 43 has an L level fixed defect, that is,
The case where the register 33 ₁₁ has a fixed L level defect is shown as an example.

FIG. 4A shows the register control signal φ.
₂ , FIG. 4 (B) is a register control signal φ ₁ , FIG. 4 (C) is a start signal SI, and FIG. 4 (D) is an inverter 42, 44.
4 (E) shows the outputs of the inverters 43 and 45, and FIG. 4 (F) shows the selection signal SEL.

That is, in the first embodiment, when the register control signal φ ₂ is set to the H level after the start signal SI of the H level is input, the nMOS transistors 34 and 36 are turned on and the start signal is set. SI is captured in the first stage, and the outputs of the inverters 42 and 44 become L level.

After that, when the register control signal φ ₂ = L level and the start signal SI = L level, the register control signal φ ₁ = H level and the nMOS transistors 35 and 37 are turned on.

In this case, the output of the inverter 45 is at the H level, but the output of the inverter 43 is maintained at the L level because the inverter 43 has the L level fixed defect.

Therefore, when the output of the inverter 45 becomes H level, the selection signal SEL = L level and the selection signal / SEL = H level are set, and the nMOS transistor 51 is turned on.
= OFF, the nMOS transistor 52 = ON, and the output of the inverter 45 is supplied to the second stage.

After that, the register control signal φ₁= L level
Control signal φ₂= H level, the inverter 4
2,44 output = H level, then register control
Signal φ ₂= L level, register control signal φ₁= H level
Then, the output of the inverter 45 becomes L level.

Therefore, when the output of the inverter 45 becomes L level, the selection signal SEL = H level and the selection signal / SEL = L level are set, and the nMOS transistor 51.
= ON, nMOS transistor 52 = OFF.

As described above, in the second embodiment,
For example, when the register 33 ₁₁ is at the L level fixed defects, if register 33 ₂₁ is normal, by controlling the level of the selection signal SEL, / SEL, it is possible to ensure the normal operation.

That is, in the second embodiment, when any one of the registers 33 _i1 and 33 _i2 forming the 1-bit portion is defective, the selection signal SEL is selected so that the output of the defective register is not selected. By controlling the level of / SEL, normal operation can be ensured.

Therefore, according to the second embodiment, the work of cutting the wiring or welding the wiring is not required to repair or correct the defect of the register, and the defect of the register in the shift register portion can be relieved. It can be done easily.

FIG. 5 is a diagram showing another example of the configuration of the essential parts of the second embodiment of the present invention, showing the circuit configuration of a portion of the shift register included in the second embodiment.

In the figure, 55 is an input switch circuit,
Reference numerals 6 and 57 are nMOS transistors. Also, 5
8 _11, 58 ₁₂ is the first stage of the register formed by using an nMOS transistor 56 and 57 as the input transistors, 59 to 62 are inverters, 63 and 64 are nMOS transistors.

Further, reference numeral 65 ₁ is the selector of the first stage,
66 and 67 are nMOS transistors. Also, 58
_21, 58 ₂₂ is 2-stage register formed by using an nMOS transistor 66 and 67 as the input transistors, 68 to 71 are inverters, 72 and 73 are nMOS transistors.

Further, 65 ₂ is a selector in the second stage,
74 and 75 are nMOS transistors. Also, φ ₁
Is a register control signal for controlling ON / OFF of the nMOS transistors 63, 64, 72, 73.

Further, φ _A is an nMOS transistor 57,
A selection signal for controlling on / off of 67 and 75, φ _B is n
This is a selection signal for controlling ON / OFF of the MOS transistors 56, 66, 74.

FIG. 6 is a waveform diagram showing the operation of the configuration shown in FIG. 5, in which the inverter 60 has an L level fixed defect, that is,
The case where the register 58 ₁₁ has an L level fixed defect is shown as an example.

Here, FIG. 6A shows the selection signal φ _A , FIG.
6B is the selection signal φ _B , FIG. 6C is the register control signal φ ₁ , FIG. 6D is the start signal SI, FIG. 6E is the output of the inverters 59 and 61, and FIG. Inverter 6
Outputs of 0 and 62, and FIG. 6 (G) show outputs of the inverters 68 and 70.

That is, in the second embodiment shown in FIG. 5, after the start signal SI of H level is input, the selection signals φ _A and φ _B are set to H level, and the nMOS transistors 56 and 57 are turned on. Then, the start signal SI is fetched in the first stage, and the outputs of the inverters 59 and 61 become L level.

After that, the selection signals φ _A and φ _B = L level,
When the start signal SI = L level, the register control signal φ ₁ = H level is set. In this case, the inverter 62
Output becomes high level, but since the inverter 60 has an L level fixed defect, the output of the inverter 60 maintains the low level.

Thereafter, the selection signal φ _A = H level is set, but in this case, the selection signal φ _B is maintained at the L level and n
The MOS transistor 67 = on and the nMOS transistor 66 = off, and the output of the inverter 62 is the selector 6
5 _{1 is} output, the start signal SI is captured in the second stage, and the outputs of the inverters 68 and 70 become L level.

After that, the selection signal φ_A= L level,
Register control signal φ₁= Inverter when set to H level
The output of the controller 62 becomes L level, and then the register control signal
No. φ ₁= L level, selection signal φ_A, Φ_B= H level
Then, the output of the inverters 68 and 70 becomes H level.
It

Thus, the second embodiment having the configuration shown in FIG.
In, for example, register 58 ₁₁L level fixed missing
Even in the case of a fall, the register 58_{twenty one}Is normal
Select signal φ_A, Φ_BBy controlling the level of
Therefore, normal operation can be ensured.

That is, in the second embodiment having the configuration shown in FIG. 5, the registers 58 _i1 and 58 _i2 forming the 1-bit portion are formed.
If any of these is defective, normal operation can be ensured by controlling the levels of the selection signals φ _A and φ _B so that the output of the defective register is not selected.

Therefore, according to the second embodiment, the work of cutting the wiring or welding the wiring is not required to repair or correct the defect of the register, and the defect of the register in the shift register section can be relieved. It can be done easily.

Third Embodiment FIG. 7 is a diagram for explaining the principle of the third embodiment of the present invention, in which a start signal SI required for horizontal scanning or vertical scanning is supplied as an input signal in the drive circuit. 1 shows a circuit configuration of a parallel output type shift register.

In the figure, 13₁₁~ 13_1k, 13_{twenty one}~ 13_2k，
Thirteen₃₁~ 13_3k, 13₄₁~ 13_4kIs, for example, D
1-bit register consisting of a flip-flop, 14₁~
14 _FourThe selection operation is controlled by the selection signal SEL
It is an input selector.

Here, the registers 13 _{11 to} 13 _1k and the selector 14 ₁ constitute a first-stage portion.
_{21 to} 13 _2k and the selector 14 ₂ constitute a second stage portion, the registers 13 _{31 to} 13 _3k and the selector 14 ₃ constitute a third stage portion, and the registers 13 _{41 to} 13 _4k and
The selector 14 ₄ constitutes the fourth stage.

In the drawing, the selectors are all provided in the first to fourth stages, but in the third embodiment, the selectors may be provided only in specific stages. That is, the drive circuit of the liquid crystal display device according to the third embodiment has a serial input / parallel output type shift register to which the start signal SI necessary for horizontal scanning or vertical scanning is supplied, with input terminals connected to each other. A plurality of registers 13 _{i1 to} 13 _ik and a plurality of these registers 13 _i1 to
A circuit including a selector 14 _i that selects and outputs the output of 13 _ik is configured in cascade connection with or without a circuit including a plurality of registers connected in parallel. Note that i = a positive integer and j = a positive integer.

Even in the active matrix type liquid crystal display device in which the third embodiment is integrated on the liquid crystal display panel, the defective register can be detected by performing the display inspection.

Here, in the stage where the selector is provided, even if a defective register is included _in the plurality of registers 13 _{i1 to} 13 _in , if there is at least one normal register, the normal register By varying the level of the selection signal SEL so as to select the output, normal operation can be ensured, and the work of cutting the wiring or welding the wiring is not required to repair the defect.

Fourth Embodiment FIG. 8 is a diagram for explaining the principle of the fourth embodiment. It is a serial input / parallel output type in which a start signal SI required for horizontal scanning or vertical scanning is supplied as an input signal in the drive circuit. The circuit structure of a shift register is shown.

In the figure, 15 ₁₁ to 15 ₃₁ , 15 ₁₂ to 15
_32, for example, register 1 bit configuration consisting of D flip-flop, _{161-164 3} are each two-input selector for selecting operation is controlled by a selection signal SEL ₁ to SEL _3.

Further, 17 _{1 to} 17 ₃ are, for example, defect detection / selector control circuits composed of RS flip-flops, and when initialized, the selectors 16 _{1 to} 16 ₃
To, to select the output of register 15 _{12-15 32,} after initialization, when monitoring the change in the output level of the register 15 _{11-15 31,} detects a change in output level of the register 15 _{11-15 31} , Selector _{1 to} 16 ₃ to register 1
Selector 16 selects the output of 5 ₁₁ to 15 _31.
It controls _{1 to} 16 ₃ .

Here, the registers 15 ₁₁ and 15 ₁₂ , the selector 16 ₁ and the defect detection / selector control circuit 17 ₁ constitute the first stage portion, and the registers 15 ₂₁ and 15 ₂₂ and
Selector 16 ₂ and defect detection / selector control circuit 17 ₂
And constitute the second stage part, and registers 15 ₃₁ , 15 ₃₂
, Selector 16 ₃ and defect detection / selector control circuit 1
7 ₃ and 7 _{3 form the} third stage.

That is, in the drive circuit of the liquid crystal display device according to the fourth embodiment, a serial input / parallel output type shift register to which a start signal SI required for horizontal scanning or vertical scanning is supplied is connected to its input terminals. Registers 15 _i1 , 15
_i2 , a selector 16 _i for selecting and outputting the outputs of these registers 15 _i1 and 15 _i2 , and when initialized, the selector 16 _i is caused to select the output of the register 15 _i2 , and after initialization, the register 15 _{i When} the change in the output level of _i1 is monitored and the change in the output level of the register 15 _i1 is detected,
As to select the output of register 15 _i1 to the selector 16 _i, is that in a circuit consisting of a defect detection selector control circuit 17 _i for controlling the selector 16 _i are connected in cascade. Note that i = a positive integer.

In the fourth embodiment, a defect detection / selector control circuit 17 _i is provided, and when this defect detection / selector control circuit 17 _i is initialized, it is stored in the selector 15 _i in the register 15 _i2. Output of the register 15 _i1 is monitored after the initialization, and when the change of the output level of the register 15 _i1 is detected, the selector 16 _i is caused to select the output of the register 15 _i1. In addition, the selector 16 _i is controlled.

Therefore, even if the register 15 _i1 is defective, if the register 15 _i2 is normal, normal operation can be automatically ensured, and
Even if the register 15 _i2 is defective, normal operation can be automatically ensured when the register 15 _i1 is normal.

That is, if either of the registers 15 _i1 and 15 _i2 is normal, normal operation can be automatically ensured. To repair or correct the defect of the register, disconnection of wiring or The work of welding the wiring is not required.

FIG. 9 is a circuit diagram showing an essential part of the fourth embodiment of the present invention, and shows the circuit configuration of the 1-bit portion of the shift register included in the fourth embodiment.

In the figure, reference numeral 76 is a 1-bit regular register composed of a positive edge trigger type D flip-flop, and 77 is a 1-bit spare register composed of a positive edge trigger type D flip-flop.

Reference numeral 78 is a selector which is controlled by the selection signal SEL to select and output the output of the regular register 76 and the output of the spare register 77.
Is a transmission gate, and 81 is an inverter.

This selector 78 has a selection signal SEL = H.
If level, transmission gate 79 = on, transmission gate 80
= OFF, the output Q ₇₆ of the regular register 76 is selected, and when the selection signal SEL = L level, the transmission gate circuit 79 =
With the transmission gate 80 turned off, the output Q ₇₇ of the spare register ₇₇ is selected.

Reference numeral 82 is the output Q of the normal register 76.
Regular register 7 based on ₇₆ and reset signal RES
6 is a defect detection / selector control circuit for detecting the defect 6 and controlling the selection operation of the selector 78, and 83 and 84 are RS
A flip-flop, 85 is an inverter, and 86 is an AND circuit.

The defect detection / selector control circuit 82 is
When the outputs Q ₈₃ and Q _{84 of the} RS flip-flops ₈₃ and ₈₄ are both at the H level, the selection signal SEL = H level is set, but the RS flip-flop 83 has the normal register 76.
_Is set when the output Q ₇₆ = H level, and the output Q ₈₃ is set to H level, and when the reset signal RES = H level is reset, the output Q _{83 is set} to L level.

[0103] In addition, RS flip-flop 84, when the output Q ₇₆ = L level of the normal register 76 is set, its output Q ₈₄ and H level, the reset signal RE
When S = H level, it is reset and its output Q ₈₄
Is set to L level.

FIG. 10 is a waveform diagram showing the operation of the fourth embodiment. FIG. 10 (A) is a clock signal CLK for controlling the registers 76 and 77, FIG. 10 (B) is a reset signal RES, and FIG. (C) shows the start signal SI.

FIG. 10D shows the regular register 76.
Output Q ₇₆ of FIG. 10, (E) is output Q ₇₇ of the spare register 77, FIG. 10 (F) is output Q ₈₃ of the RS flip-flop ₈₃ , and FIG. 10 (G) is output Q _{84 of} the RS flip-flop ₈₄ . FIG. 10H shows the selection signal SEL.

That is, in the fourth embodiment, first,
The reset signal RES = H level is set, the RS flip-flops 83 and 84 are reset, and their outputs Q ₈₃ and Q
₈₄ = L level

As a result, the selection signal SEL is set to L level, the transmission gate 79 is turned off and the transmission gate 80 is turned on, and the selector 78 selects the output Q ₇₇ of the spare register 77.

If the normal register 76 is not the H level fixed defect, the output of the normal register 76 = L level and the output of the inverter 85 = H level, so immediately after the reset signal RES = L level. Then, the RS flip-flop 84 is set, and its output Q ₈₄ = H level.

In this case, since the RS flip-flop 83 is not set, its output Q ₈₃ remains at L level, the selection signal SEL maintains L level, and the selector 78
Maintains the selected state of the output Q ₇₇ of the spare register 77.

After that, the start signal S of H level
When I is input, at the rising edge of the clock signal CLK, the start signal SI is latched in the regular register 76 and the spare register 77, and if there is no L level fixed defect, the outputs Q ₇₆ and Q _{77 are} output. Are both at the H level.

As a result, the RS flip-flop 83 is set and its output Q ₈₃ = H level. On the other hand, the output of the inverter 85 becomes L level, but the reset signal RES remains at L level, so the output Q ₈₄ of the RS flip-flop 84 maintains H level.

As a result, the selection signal SEL is set to H level, the transmission gate 79 is turned on and the transmission gate 80 is turned off, and the selector 78 is in a state of selecting the output of the regular register 76.

On the other hand, when the regular register 76 has the L level fixed defect and the start signal SI is input, the output Q ₇₇ of the spare register 77 becomes the H level, but the output of the regular register 76 is Maintains the L level as shown by the broken line 87 in FIG.

As a result, the RS flip-flop 83 is not set, and the output Q ₈₃ of the RS flip-flop ₈₃ is
The L level is maintained as indicated by the broken line 88 in FIG. 10 (F), and the selection signal SEL is maintained at the L level as indicated by the broken line 89 in FIG. 10 (H).

Therefore, the transmission gate 79 = off state and the transmission gate 80 = on state are maintained, and the selector 78 is
It will maintain the state of selecting the output Q ₇₇ of the spare register 77.

As described above, according to the fourth embodiment, even if the spare register 77 has a defect, normal operation can be ensured if the normal register 76 is normal. Even if the regular register 76 is defective, normal operation can be ensured if the spare register 77 is normal.

That is, according to the fourth embodiment, if either the normal register or the spare register forming the 1-bit portion is normal, normal operation can be automatically ensured.

Therefore, according to the fourth embodiment, in order to repair the defect of the register, the work of cutting the wiring, welding the wiring, and supplying the selection signal SEL from the outside is not required, and the shift register is not required. It is possible to easily relieve the defect of the register in the section.

FIG. 11 is a circuit diagram showing another structural example of the essential part of the fourth embodiment of the present invention, and shows the circuit structure of the 1-bit portion of the shift register included in the fourth embodiment.

The structure of the fourth embodiment shown in FIG. 11 differs from that of the fourth embodiment shown in FIG. 9 in that a defect detection / selector control circuit 90 having a different circuit structure is provided. Has the same configuration as that shown in FIG.

In the defect detection / selector control circuit 90, 91 and 92 are VCC power supply lines for supplying a power supply voltage VCC, 93 and 94 are pMOS transistors, 95 and 96 are nMOS transistors, 97 is an inverter, and 98 is AN.
It is a D circuit.

In the defect detection / selector control circuit 90, when the output Q ₇₆ of the normal register ₇₆ = L level, the pMOS transistor 93 = OFF and the pMOS transistor 94 = ON.

In this state, when the reset signal RES = H level, the nMOS transistors 95 and 96 are turned on, the node 99 = L level, the node 100 = L level, and the selection signal SEL = L level.

After that, when the reset signal RES = L level, the nMOS transistors 95 and 96 are turned off, the node 99 = L level is maintained, and the node 100 = H level.
And the selection signal SEL = L level is maintained.

Thereafter, the output Q ₇₆ of the regular register ₇₆ =
At H level, the pMOS transistor 93 is turned on,
pMOS transistor 94 = off, node 99 =
It becomes H level, node 100 = H level is maintained, and selection signal SEL = H level.

As described above, the defect detection / selector control circuit 90 operates similarly to the defect detection / selector control circuit 82 of FIG. 9, and therefore, the same effect as that of FIG. 9 can be obtained.

That is, according to the fourth embodiment having the configuration shown in FIG. 11, if either the normal register or the spare register forming the 1-bit portion is normal, the normal operation is automatically ensured. You can

Therefore, even with the configuration of FIG. 11, the repair of the defect of the register does not require the work of cutting the wiring, welding the wiring, and controlling the selection signal SEL from the outside, and the shift is performed. The defect of the register in the register section can be easily relieved.

Further, according to the configuration of FIG. 11, the defect detection / selector control circuit 90 has a simpler circuit configuration than the defect detection / selector control circuit 82 shown in FIG. 9, so that the drive circuit is simplified. Can be realized.

Fifth Embodiment FIG. 12 is a diagram for explaining the principle of the fifth embodiment of the present invention, in which a start signal SI necessary for horizontal scanning or vertical scanning is supplied as an input signal in the drive circuit. 1 shows a circuit configuration of a 1-bit portion of a parallel output type shift register.

In the figure, reference numerals 18 ₁ to 18 ₄ denote, for example, 1-bit registers composed of D flip-flops, and 19 ₁
Is a gate circuit such as an OR circuit or an AND circuit to which the outputs of the registers 18 ₁ and 18 ₂ are input, and 19 ₂ is a register 1
A gate circuit such as an OR circuit or an AND circuit to which the outputs of 8 ₃ and 18 ₄ are input, and a selector 20 that selects and outputs the outputs of the gate circuits 19 ₁ and 19 ₂ .

The register 21 detects from the output of the gate circuit 19 ₁ whether or not there is a defect in one or both of the registers 18 ₁ and 18 ₂ that makes the output level of the selector 20 abnormal. _When there is no defect that causes the output level of the selector 20 to be abnormal in one or both of ₁ and 18 ₂ , the selector 20 is caused to select the output of the gate circuit 19 ₁ and either of the registers 18 ₁ and 18 ₂ is selected. If either or both have a defect that causes the output level of the selector 20 to be abnormal, a defect detection / selector control circuit that controls the selector 20 so that the selector 20 selects the output of the gate circuit 19 _2. is there.

That is, the driving of the liquid crystal display device according to the fifth embodiment is performed.
The moving circuit is a start signal required for horizontal or vertical scanning.
Serial input / parallel output type shift register supplied with SI
The first plurality of registers whose input terminals are connected to each other.
Data, for example, two registers 18₁, 18₂And the second
A plurality of registers, for example two registers 18₃, 18
_FourAnd register 18₁, 18₂The game to which the output of
Circuit 19₁And register 18₃, 18_FourOutput of
Gate circuit 19₂And these gate circuits 19₁，
19₂Selector 20 for selecting and outputting the output of
Circuit 19₁Output from register 18₁, 18₂Nozu
Set either or both to make the output level of the selector 20 abnormal.
The register 18 detects whether there is a defect
₁, 18₂Either or both of the
If there are no defects that make the bell abnormal,
The gate circuit 19 is provided in the selector 20.₁Select the output of
Dista 18₁, 18₂Selector 2 for either or both
If there is a defect that causes the output level of 0 to be abnormal
If the selector 20 is connected to the gate circuit 19₂Output of
As described above, the defect detection / selection that controls the selector 20 is performed.
The circuit composed of the controller control circuit 21 is connected in cascade.
It is that.

In the fifth embodiment, defect detection / selection is performed.
A data control circuit 21 is provided to detect and select this defect.
The controller control circuit 21 includes a register 18₁, 18₂Nozuka
Or, make the output level of the selector 20 abnormal in both cases.
If there is no defect, the selector 20 is gated.
Circuit 19₁Select the output of register 18₁, 18 ₂
Output level of selector 20 is abnormal in either or both
If there is a defect that causes
Gate circuit 19₂Select the output of
It controls the data 20.

Therefore, even if one or both of the registers 18 ₃ and 18 ₄ has a defect that causes the output level of the selector 20 to be abnormal, the register 1
If there is no defect that causes the output level of the selector 20 to be abnormal in either or both of 8 ₁ and 18 ₂ , normal operation can be automatically ensured.

In addition, the register 18₁, 18₂One of
Or, make the output level of the selector 20 abnormal in both cases.
The register 18 is used even if there is a defect.₃，
18 _FourEither or both of the output levels of the selector 20
If there is no defect that makes the
Normal operation can be secured.

That is, even if any of the registers 18 ₁ to 18 ₄ is defective, the gate circuits 19 ₁ and 19
If either of the outputs of ₂ is normal, normal operation can be automatically secured, and work such as cutting the wiring or welding the wiring is required to repair or correct the defect in the register. do not do.

FIG. 13 is a circuit diagram showing an essential part of the fifth embodiment of the present invention, and shows the circuit configuration of the one-stage portion of the shift register included in the fifth embodiment.

In the figure, reference numerals 101 to 104 denote 1-bit registers consisting of positive edge trigger type D flip-flops, 105 and 106 select OR circuits, and 107 selects the output of the OR circuit 105 and the output of the OR circuit 106. Selectors 108 and 109 for outputting an AND circuit,
110 is an OR circuit.

Reference numeral 112 is a defect detection / selector control circuit for detecting the H level fixed defect of the registers 101 and 102 and controlling the selection operation of the selector 107.
Is an inverter, 114 is an AND circuit, 115 is an RS flip-flop composed of NOR circuits 116 and 117, and TS
Is a defect correction control signal.

FIG. 14 is a waveform diagram showing the operation when the register 101 has a fixed L level defect.
4A shows a clock signal CLK for controlling the operations of the registers 101 to 104, and FIG. 14B shows a start signal SI.

Further, FIG. 14C shows the normal phase output Q of the register 101, FIG. 14D shows the normal phase output Q of the register 102, FIG. 14E shows the normal phase output Q of the register 103, and FIG.
4 (F) indicates the positive phase output Q of the register 104.

14 (G) shows the output of the OR circuit 105, FIG. 14 (H) shows the output of the OR circuit 106, and FIG.
(I) shows the output of the selector 107.

Here, in the fifth embodiment, the OR
The circuit 105 is provided, and the output of the register 101 and the register 1
Since the output of 02 is OR-processed, a normal value can be obtained as the output of the OR circuit 105 even when either of the registers 101 and 102 has a fixed L level defect.

Further, the OR circuit 106 is provided, and the register 1
Since the output of 03 and the output of the register 104 are OR-processed, a normal value can be obtained as the output of the OR circuit 106 even when either of the registers 103 and 104 has a fixed L level defect. .

FIG. 15 shows a shift register having the circuit shown in FIG. 13 as one stage portion, and 118 is a start signal input terminal to which the start signal SI is inputted during the normal operation.

Further, FIG. 16 shows registers 101 and 102.
FIG. 16 (A) is a waveform diagram showing a correction method when there is an H level fixed defect in any of
K, FIG. 16B shows the level of the start signal input terminal 118.

FIG. 16C shows the reset signal RES applied to the RS flip-flop 115, and FIG.
(D) shows the defect correction control signal TS applied to the AND circuit 114.

Further, FIG. 16 (E) shows the output SO _{N-1 of} the _N- 1th stage portion, and FIG. 16 (F) shows the output SO _N of the Nth stage portion.
_N, FIG. 16 (G) shows the output SO _{N + 1} of the N + 1-stage portion.

Further, FIG. 16H shows the positive phase output Q of the RS flip-flop 115 at the (N-1) th stage,
16I shows the positive phase output Q of the Nth stage RS flip-flop 115, and FIG. 16J shows the positive phase output Q of the N + 1th stage RS flip-flop 115.

In the fifth embodiment, first, when the H-level fixed defect is repaired, until the repair is completed,
The start signal input terminal 118 is set to L level. Then, first, the reset signals RES of the RS flip-flops 115 of all the stages are set to the H level, the positive phase output Q = L level and the negative phase output / Q = H level, and the selector 107 selects the output of the OR circuit 105. Is set to

Immediately after the reset signal RES is set to L level, the defect correction control signal TS is set to H level.
The defect correction control signal TS is maintained at the H level until the correction is completed. Here, the output SO ₁ to SO _N-1 from the first stage to the (N-1) th stage has an L level.

However, in the Nth stage, the register 10
Since it is said that there is a fixed defect of H level in either of No. 1 and 102, the output of the OR circuit 105 becomes H level,
The output of the AND circuit 114 becomes H level.

As a result, the RS flip-flop 115 is set, the positive phase output Q = H level, the negative phase output / Q = L.
The level becomes the level, and the selector 107 selects the output of the OR circuit 106.

In this case, the registers 103 and 10
As described above, a normal level can be obtained at the output of the OR circuit 106 even when any of the four has a fixed L level defect.

When the H-level fixed defect does not exist in the registers 101 and 102, the RS flip-flop 115 is not set, so the selector 107 is used.
Keeps the state of selecting the output of the OR circuit 105.

In this case, the registers 101, 10
As described above, a normal level can be obtained at the output of the OR circuit 105 even when either of the two has an L level fixed defect.

As described above, in the fifth embodiment, even if either or both of the registers 101 and 102 have the H level fixed defect, either of the registers 103 and 104 must have the H level fixed defect. For example, register 10
Normal operation can be automatically ensured even if any of L3 and L104 has a fixed L level defect.

Even if either or both of the registers 103 and 104 have an H level fixed defect, if either of the registers 101 and 102 does not have an H level fixed defect, then one of the registers 101 and 102 is selected. Even if there is an L-level fixed defect, the normal operation can be automatically ensured.

That is, even if either or both of the registers 101 and 102 or both or both of the registers 103 and 104 have an H level fixed defect, OR
If a normal output level can be obtained in either of the circuits 105 and 106, normal operation can be automatically ensured.

Therefore, according to the fifth embodiment as well,
To repair and repair defects in registers, disconnect the wiring,
The work of welding the wiring and supplying the selection signal SEL from the outside is not required, and the defect of the register in the shift register portion can be easily repaired.

FIG. 17 is a circuit diagram showing another structural example of the essential parts of the fifth embodiment of the present invention, and shows the circuit structure of the one-stage portion of the shift register included in the fifth embodiment.

The configuration shown in FIG. 17 corresponds to the fifth configuration shown in FIG.
The difference from the embodiment is that the OR circuit 1 provided in the configuration of FIG.
AND circuits 119 and 120 are provided instead of 05 and 106, and the inverter 113 is connected between the AND circuit 119 and the AND circuit 114.
The configuration is similar to that of FIG.

In the configuration shown in FIG. 17, even if either or both of registers 101 and 102 have an L level fixed defect, if either register 103 or 104 does not have an L level fixed defect, Register 10
Normal operation can be automatically ensured even if any of H3 and H4 has an H level.

Even if either or both of the registers 103 and 104 have the L-level fixed defect, if either of the registers 101 and 102 has the L-level fixed defect, either of the registers 101 and 102 has the defect. Even if there is an H-level fixed defect, the normal operation can be automatically ensured.

That is, even when either or both of the registers 101 and 102 or both or both of the registers 103 and 104 have an L level fixed defect, AN
If a normal output level can be obtained in either of the D circuits 110 and 120, normal operation can be automatically ensured.

Therefore, the structure shown in FIG. 17 does not require the work of cutting the wiring, welding the wiring, or supplying the selection signal SEL from the outside in order to repair or repair the defect of the register. The defect of the register in the shift register section can be easily relieved.

Sixth Embodiment FIG. 18 is a diagram for explaining the principle of the sixth embodiment of the present invention, in which a start signal SI necessary for horizontal scanning or vertical scanning is supplied as an input signal in the drive circuit, serial input / parallel. The circuit configuration of the 1-bit portion of the output type shift register is shown.

In the figure, 22 ₁ , 22 ₂ , and 23 are, for example,
1-bit register consisting of D flip-flops,
24 is an OR to which the outputs of the registers 22 ₁ and 22 ₂ are input
Circuit, a gate circuit such as an AND circuit, 25 is a gate circuit 2
4 is a selector for selecting and outputting the output of 4 and the output of the register 23.

[0170] The selector 2 to either or both the output of the register 22 _1, 22 ₂ of the gate circuit 24 is 26
If there is no defect that causes the output level of the selector 25 to be abnormal in either or both of the registers 22 ₁ and 22, it is detected whether or not there is a defect that causes the output level of 5 to be abnormal. Causes the selector 25 to select the output of the gate circuit 24, and causes the selector 25 to select the output of the register 23 when the registers 22 ₁ and 22 ₂ have a defect that causes the output level of the gate circuit 24 to be abnormal. As described above, the defect detection / selector control circuit controls the selector 25.

That is, the driving of the liquid crystal display device according to the sixth embodiment is performed.
The moving circuit is a start signal required for horizontal or vertical scanning.
Serial input / parallel output type shift register supplied with SI
Grouped with input terminals connected to each other
Register, for example, two registers 22₁, 22₂Over
Register 23 that is not grouped
Star 22₁, 22₂Circuit 24 to which the output of
And the output of the gate circuit 24 and the output of the register 23
Of the selector circuit 25 for selecting and outputting
Output to register 22₁, 22₂To either or both
There is a defect that makes the output level of the selector 25 abnormal.
It is detected whether or not it exists, and the register 22 ₁, 22₂Noi
Either the output level of the selector 25 is abnormal
If there is no defect that causes it, the selector 25
The output of the gate circuit 24 is selected, and the register 22₁, 2
Two₂And make the output level of the gate circuit 24 abnormal.
If there is a defect, the selector 25
A defect that controls the selector 25 to select the output
The detection / selector control circuit 26 is connected in cascade.
Is to be configured.

In the sixth embodiment, a defect detection / selector control circuit 26 is provided, and this defect detection / selector control circuit 26 outputs the output level of the selector 25 to either or both of the registers 22 ₁ and 22 _2. If there is no defect that causes the selector 25 to be abnormal, there is a defect that causes the selector 25 to select the output of the gate circuit 24 and causes one or both of the registers 22 ₁ 22 ₂ to make the output level of the selector 25 abnormal. If there is, the selector 25 selects the output of the register 23.
Is to control.

Therefore, the selector 23 is added to the register 23.
Even if there is a defect that makes the output level of the selector 25 abnormal, if there is no defect that makes the output level of the selector 25 abnormal in either or both of the registers 22 ₁ and 22 ₂ , Normal operation can be automatically secured.

Even if one or both of the registers 22 ₁ and 22 ₂ has a defect that causes the output level of the selector 25 to be abnormal, the register 23 causes the output level of the selector 25 to be abnormal. If there is no such defect, normal operation can be automatically ensured.

That is, if either the output of the gate circuit 24 or the register 23 is normal, the normal operation can be automatically ensured, and the wiring is cut to repair or correct the defect of the register. Also, the work of welding wiring is not required.

Seventh Embodiment FIG. 19 is a diagram for explaining the principle of the seventh embodiment of the present invention. In the figure, 27 ₁ and 27 _n are signal lines (data lines or scanning lines) to be driven, and 28 is horizontal scanning. Alternatively, it is a serial input / parallel output type shift register that shifts the start signal SI required for vertical scanning in synchronization with the clock CLK.
_Reference numerals ₁ and 30 _{1 denote} drive voltage output circuits provided corresponding to the signal line 27 ₁ , and reference numerals 29 _n and 30 _{n denote} drive voltage output circuits provided corresponding to the signal line 27 _n .

31 ₁ is a selector for selecting and outputting the output of the drive voltage output circuit 29 _{1 and} the output of the drive voltage output circuit 30 ₁ , and 31 _n is the output of the drive voltage output circuit 29 _n and the drive voltage output circuit. A selector for selecting and outputting 30 _n outputs.

Further, 32 ₁ and 32 ₂ are defect detection / selector control circuits, and these defect detection / selector control circuits 32 ₁ and 32 _n are respectively drive voltage output circuit 2
9 _1, in case of supplying a reference voltage to 29 _n, driving voltage output circuit 29 _1, by the reference voltage from 29 _n to determine whether the output drive voltage output circuit 29 _1,
29 _n defects are detected, and drive voltage output circuits 29 ₁ , 29
_If there is no defect in _n , the selectors 31 ₁ , 31
_n to thereby select the output of the drive voltage output circuit 29 _1, 29 _n, when a defect is present in the drive voltage output circuit 29 _1, 29 _n, the selector 31 _1, 31 _n to the drive voltage output circuit 30 _1, 30 Selector 3 to select _n outputs
It controls 1 ₁ and 31 _n .

That is, in the drive circuit of the liquid crystal display device according to the seventh embodiment, of the signal lines to be driven, the portion which drives one signal line 27 _i is the drive voltage output circuit 2 which outputs the drive voltage.
9 _i and 30 _i , and these drive voltage output circuits 29 _i and 30 _i
a selector 31 _{i of i} output by selecting the output from the case of supplying a reference voltage to the drive voltage output circuit 29 _i, by determining whether the reference voltage from the drive voltage output circuit 29 _i is output to detect defects in the drive voltage output circuit 29 _i, when there is no defect in the drive voltage output circuit 29 _i, the selector 31 _i to thereby select the output of the drive voltage output circuit 29 _i, the drive voltage output circuit 29 _i If a defect is present, the selector 31 _i to the drive voltage output circuit 30
_The defect detection / selector control circuit 32 _i for controlling the selector 31 _i is provided so as to select the output of _i . Note that i = 1 to n is an integer.

In the seventh embodiment, a defect detection / selector control circuit 32 _i is provided, and this defect detection / selector control circuit 32 _i supplies the drive voltage output circuit 29 _i with a reference voltage. A defect of the drive voltage output circuit 29 _i is detected by determining whether or not the drive voltage output circuit 29 _i outputs the reference voltage. If no defect exists in the drive voltage output circuit 29 _i , the selector is selected. 31 _i a to select the output of the drive voltage output circuit 29 _i, if a defect is present in the drive voltage output circuit 29 _i, as to select the output of the drive voltage output circuit 30 _i to the selector 31 _i, the selector 31 _It controls _i .

Therefore, even if there is a defect in the drive voltage output circuit 29 _i , the drive voltage output circuit 30 _i
If there is no defect in the data line, the output of the drive voltage output circuit 30 _i can be supplied to the data line 27 _i to automatically ensure normal operation.

[0182] Further, even if a defect in the drive voltage output circuit 30 _i is present, the drive voltage if the fault is not present in the output circuit 29 _i, the output of the drive voltage output circuit 29 _i to the data line 27 _i Can be supplied and automatically ensure normal operation.

That is, if either of the drive voltage output circuits 29 _i and 30 _i is normal, normal operation can be automatically ensured, and a defect of the drive voltage output circuit can be repaired or corrected. No need to cut wires or weld wires.

FIG. 20 is a circuit diagram showing an essential part of the seventh embodiment of the present invention, showing a portion for driving the data lines.

In the figure, 121 ₁ and 121 ₆₄₀ are data lines,
Reference numeral 122 is a serial input / parallel output type shift register that shifts the start signal SI in synchronization with the clock signal CLK, and 123 ₁ and 123 ₆₄₀ are D flip-flops.

Further, 124 ₁ and 124 ₆₄₀ are normal drive voltage output circuits, and 125 ₁ and 125 ₆₄₀ are synchronized with the timing signals SO ₁ and SO ₆₄₀ output from the D flip-flops 123 ₁ and 123 ₆₄₀ , respectively. 3 bits for latching display data D0 to D2 having 3 bits
It is a register.

Also, 126₁, 126₆₄₀Each is 3
Bit register 125₁, 125 ₆₄₀Latched by 3
Decode display data D0 to D2 of bit configuration 3-
8 decoders.

Further, 127 ₁ and 127 ₆₄₀ are each 3
-8 is a selector which selects and outputs the drive voltages V0 to V7 corresponding to the display data D0 to D2 based on the decode signals output from the -8 decoders 126 ₁ and 126 ₆₄₀ .
Note that V0 to V7 are voltages obtained by dividing 2 to 4.8 [V] into eight equal parts.

Further, 128 ₁ and 128 ₆₄₀ are auxiliary drive voltage output circuits, and 129 ₁ and 129 ₆₄₀ are synchronized with the timing signals SO ₁ and SO ₆₄₀ output from the D flip-flops 123 ₁ and 123 ₆₄₀ , respectively. 3 bits for latching display data D0 to D2 having 3 bits
It is a register.

Also, 130₁, 130₆₄₀Each is 3
Bit register 129₁, 129 ₆₄₀Latched by 3
3 to 8 bits for decoding the bit display data D0 to D2
It is a coder.

Further, each of 131 ₁ and 131 ₆₄₀ is 3
-8 it is a selector for selecting and outputting driving voltage V0~V7 corresponding to the display data D0~D2 based on the decoded signal output from the decoder 130, 130 _640.

[0192] Further, 132 ₁ is a selector for selecting and outputting the driving voltage output from the drive voltage output circuit 128 ₁ of the drive voltage and the preliminary output from the drive voltage output circuit 124 ₁ of the normal, 133 ₁ , 134 ₁ are nMOS transistors forming a switching element.

[0193] In addition, 132 ₆₄₀ is a selector for selecting and outputting the driving voltage output from the driving voltage and the spare drive voltage output circuit 128 ₆₄₀ outputted from the normal drive voltage output circuit 124 _640, 133 ₆₄₀ , 134 ₆₄₀ are nMOS transistors forming a switching element.

A defect detection / selector control circuit 135 ₁ detects a defect in the normal drive voltage output circuit 124 ₁ and controls the selection operation of the selector 132 _1.
1 is an EOR circuit, 137 ₁ is an AND circuit, 138 ₁ is R
S flip-flops, T, E and R are defect correction control signals.

Reference numeral 135 ₆₄₀ is a defect detection / selector control circuit which detects a defect in the normal drive voltage output circuit 124 ₆₄₀ and controls the selecting operation of the selector 132 ₆₄₀ .
136 ₆₄₀ is an EOR circuit, 137 ₆₄₀ is an AND circuit, 1
_Reference numeral ₃₈₆₄₀ denotes an RS flip-flop. FIG. 21 is a waveform diagram showing the operation of the seventh embodiment.
The operation of the circuit portion that drives ₁ is shown as a representative, and the operation of this circuit portion will be described below as a representative.

21A shows a horizontal synchronizing signal, FIG. 21B shows a start signal SI, FIG. 21C shows a defect correction control signal R, and FIG. 21D shows a defect correction control signal E. Shows.

21E shows the display data D0, FIG. 21F shows the display data D1, FIG. 21G shows the display data D2, FIG. 21H shows the driving voltage V0, and FIG. 21I. Indicates the drive voltage V1, and FIG. 21 (J) indicates the drive voltage V2.

FIG. 21K shows the drive voltage output circuit 1
24 ₁ output, FIG. 21 (L) is defective modified control signal T, FIG. 21 (M) shows a positive-phase output Q of the RS flip-flop 138 _1.

Further, TN is a normal operation period, TX is a defect detection / correction period, TR is a defect detection initialization period,
T0 to T7 are periods for checking whether or not V0 to V7 are normally output, and correcting any defects.

In the normal operation period TN, the pulse-shaped start signal SI of H level is supplied every horizontal scanning period, and the drive voltage output circuits 124 ₁ , 128 are supplied.
₁ is a D flip-flop 123 of the shift register 122
_The display data D0 to D2 are latched in synchronism with the timing signal SO ₁ output from ₁ and the corresponding drive voltage V0
~ V7 is output.

In this case, when the drive voltage output circuit 124 ₁ has no defect and no defect is corrected, the RS flip-flop 138 ₁ is reset and its normal phase output Q = L level, negative phase output. Output / Q = H level, nM
OS transistor 133 ₁ = OFF, the nMOS transistor 134 ₁ = ON, the output of the drive voltage output circuit 124 ₁ is supplied to the data lines 121 _1.

Next, in the defect detection period TX, the level of the start signal input terminal is set to H level and 3 bits.
Register 125 _1, 129 D flip-flop 123 ₁ as ₁ by the display data D0~D2 is latched simultaneously
Is set to the H level, and in the initialization period TR of the defect detection, the defect correction control signal R is set to the H level, and the RS flip-flop 138 ₁ is reset.

Next, when the period T0 for confirming whether the drive voltage V0 is normally output from the drive voltage output circuit 124 ₁ is reached, the defect correction control signals E, T = H level are set and the display data is displayed. [D0, D1, D2] = [0,
0, 0], and the selectors 127 ₁ and 131 ₁ select the drive voltage V0.

In this case, the drive voltage V0 = 5 [V], the drive voltages V1 to V7 = 0 [V], and if the selector 127 ₁ outputs 5 [V], the output of the EOR circuit 136 ₁ = At the L level, the output of the AND circuit 137 ₁ becomes the L level, and the RS flip-flop 138 ₁ is not set and maintains the reset state.

Next, when the period T1 for checking whether or not the drive voltage V1 is normally output from the drive voltage output circuit 124 ₁ comes, the display data [D0, D1, D2] =
As [1, 0, 0], the selector 127 ₁ selects the drive voltage V
Make sure to select 1.

In this case, the drive voltage V1 = 5 [V] and the drive voltages V0, V2 to V7 = 0 [V], and the select 12
If 7 ₁ outputs 5 [V], the EOR circuit 13
6 ₁ output = L level, AND circuit 137 ₁ output =
The L level is set, and the RS flip-flop 138 ₁ is not set and maintains the reset state.

On the other hand, the drive voltage output circuit 124 ₁
There is a defect in this drive voltage output circuit 124 ₁ to 0
When [V] is output, the output of the EOR circuit 136 ₁ =
At the H level, the output of the AND circuit 137 ₁ becomes the H level, the RS flip-flop 138 ₁ is set, and the normal phase output Q = H level and the negative phase output / Q = L level.

As a result, in the selector 132 ₁ ,
The nMOS transistor 133 ₁ = on, the nMOS transistor 134 ₁ = off, and the drive voltage output circuit 128
The output of ₁ is selected to be supplied to the data line 121 ₁ .

In this case, thereafter, unless the defect detection / correction period TX is set again, that is, the defect correction control signal R becomes H.
Unless it is set to the level, it is not reset. Therefore, the selector 132 ₁ continues to select the drive voltage output circuit 128 ₁ .

Thus, in this seventh embodiment,
Even if a defect occurs in the normal drive voltage output circuit 124 ₁ , the output of the spare drive voltage output circuit 128 ₁ is automatically selected, and the output of this spare drive voltage output circuit 128 ₁ is output to the data line 121 ₁ . Since it is supplied, normal operation can be ensured.

Even if a defect occurs in the spare drive voltage output circuit 128 ₁ , if the drive voltage output circuit 124 ₁ is normal, the normal drive voltage output circuit 124 ₁
Is supplied to the data line 121 ₁ , and normal operation can be ensured.

Therefore, according to the seventh embodiment, in order to correct the defect of the drive voltage output circuit, the wiring is cut or the
It is possible to easily repair defects in the drive voltage output circuit section without requiring the work of welding the wiring.

Eighth Embodiment FIG. 22 is a circuit diagram showing an essential part of the eighth embodiment of the present invention, showing a circuit portion for driving one data line.

The eighth embodiment is different from the seventh embodiment in that instead of the normal drive voltage output circuit 124 ₁ and the spare drive voltage output circuit 128 ₁ , an analog input voltage supplied from the outside is taken in, The point is that a normal drive voltage output circuit 139 ₁ and a spare drive voltage output circuit 140 ₁ that are configured to output this are provided, and the other points are the same as those in the seventh embodiment.

These drive voltage output circuits 139₁And spare
Drive voltage output circuit 140₁In, 141₁, 1
42₁Is the D flip-flop 1 of the shift register 122
23 ₁Output SO₁Is controlled by the on / off
NMOS transistor for pulling, 143₁, 144
Is for holding the analog input voltage
Condenser, 145₁, 146 are buffers.

FIG. 23 is a waveform diagram showing the operation of the eighth embodiment. FIG. 23 (A) shows a horizontal synchronizing signal, and FIG.
23B is a start signal SI, FIG. 23C is a defect correction control signal R, FIG. 23D is a defect correction control signal E, and FIG.
23E shows the analog input voltage AIN, and FIG. 23F shows the defect correction control signal T.

Also in the eighth embodiment, the data line 12
As a representative description of the circuit portion that drives 1 ₁ ,
After the defect detection / correction period TX is provided and the defect correction control signal R is temporarily set to the H level, the RS flip-flop 13
In the state where 8 ₁ is reset and the defect correction control signal E is at H level, the reference voltage 5 [V] is supplied instead of the analog input voltage AIN, and the defect correction control signal T = 5 [V] is supplied during this period. ] (H level), the defect of the drive voltage output circuit 139 ₁ can be corrected.

Therefore, according to the eighth embodiment as well,
It is possible to easily repair the defect in the drive voltage output circuit section without repairing the wiring or welding the wire to repair the defect in the drive voltage output circuit.

Ninth Embodiment FIG. 24 is a diagram showing the principle of the ninth embodiment of the present invention.

DR1 and DR2 are normal drive circuits provided for each row (column) and output drive voltages QR1 and QR2.

DS1 is a preliminary drive circuit provided corresponding to every two outputs of the normal drive circuit, and outputs the drive voltage QS1. CNTL is a control circuit which outputs control signals CT1 and CT2 for selecting output voltages of the drive circuits DR1, DR2 and DS1 and instructing operation timing. SW11,
SW21 is a switch circuit that connects the outputs of DR1 and DR2 to the output nodes Q1 and Q2 corresponding to each row (column),
SW12 and SW22 are switch circuits that select the control signal CT1 or CT2 and give it to the preliminary drive circuit DS1, and SW13 and SW23 output the drive voltage QS1 to the output node Q.
It is a switch circuit connected to 1 or Q2. Also, D
D1 and DD2 are provided respectively corresponding to the normal drive circuits DR1 and DR2, detect and hold a defect of DR1 or DR2, and switch circuits SW11 and SW12.
And SW13, SW21 and SW22, SW23 are defect detection circuits for controlling.

In the ninth embodiment, after the defect detection circuits DD1 and DD2 are reset by the enable signal EN, the control signal CT is set so that the drive voltages QR1 and QR2 become the reference voltage T.
1 and CT2 control the normal drive circuits DR1 and DR2, compare the drive voltages QR1 and QR2 with the reference voltage T, and hold the results in the defect detection circuits DD1 and DD2. As a result of the comparison, if the normal drive circuit DR1 (DR2) is normal, SW
11 (SW21) is on, SW12, SW13 (SW2
2, SW23) is turned off, and the drive voltage QR1 (QR2) is output to the output node Q1 (Q2). On the other hand, for example, when the normal drive circuit DR2 is out of order, SW21 is turned off, SW22 and SW23 are turned on, the preliminary drive circuit DS1 operates instead of DR2, and the drive voltage QS1 is output to the output node Q2. Therefore, the defect of the drive circuit can be corrected by adding a relatively small-scale circuit, and the yield can be improved.

FIG. 25 is a block diagram showing the essential parts of the ninth embodiment of the present invention, in which the same components as those in FIG. 24 are designated by the same reference numerals.

In the configuration shown in FIG. 25, the control circuit CNTL
A shift register SREG composed of a D flip-flop D-FF and a bus B for supplying display data D2-D0
It is composed by US. In addition, transfer circuits using transistors include switch circuits SW11 and SW1.
2, SW13, SW21, SW22, and SW23 are configured.

Further, as shown in FIG. 26, each of the defect detection circuits DD1 and DD2 is connected to an XOR (exclusive OR) gate G1, an AND gate G2 and an RS type flip-flop F.
It is composed of F1. The XOR gate G1 performs a logical operation of XOR of the driving voltage QR1 (QR2) and the reference voltage T, and the AND gate G2 outputs this output and the enable signal E.
AND logic operation is applied to the set input S of the flip-flop FF1. The reset signal R is applied to the reset input R of the flip-flop FF1. Also,
The drive circuits DR1, DR2, DS1 are data input D2-D
It is composed of a digital data driver which selectively outputs any one of the drive voltages V7-V0 based on 0.

The operation of the circuit configured as described above is shown in FIG.
Will be explained. TN is a normal operation period, and
R, T0 to T2, ... Are defect detection periods.

In TN, the start signal SI is a pulsed signal, and the drive voltages V7 to V0 are generally 4.8.
It is a voltage obtained by equally dividing V to 2V into 8 levels, and the drive voltage QR
1, QR2 and QS1 have one level of D2 to D0
According to the selected output. At this time, the defect detection circuit DD
1 and DD2 are controlled by the enable signal E so that the stored contents do not change. TR is a defect detection circuit DD1,
This is the initialization period of DD2, and SI = H is input so that the display data D2 to D0 are always taken in by DR1 and DR2. Further, the reset signal R resets the defect detection circuits DD1 and DD2.

T0 is a period for confirming that the driving voltage V0 is correctly output, inputting the display data D2 to D0 so that V0 is selected, and V0 = 5V, V1.
V7 = 0V. If the normal drive circuits DR1 and DR2 are operating normally, 5V should be output to the drive voltages QR1 and QR2, so that the defect detection circuits DD1 and DD2 compare with T = 5V. If normal, the RS flip-flop FF1 maintains the reset state. Next, T1 is a period for confirming that the drive voltage V1 is correctly output, and reset / comparison is performed as in T0. Here, as shown by the broken line, when 5V is not output as the drive voltage QR1 (QR2), the RS flip-flop FF1 is set and is not reset thereafter.

As described above, the drive circuits DR1, DR
2. If the defect of DS1 is detected and held and the drive circuit is normal, the switch circuit SW11 (SW21) is turned on,
SW12 and SW13 (SW22 and S23) are turned off, and drive voltage QR1 (QR2) is applied to output node Q1 (Q2).
Is output. On the other hand, if the normal drive circuit DR2 is defective, for example, the switch circuits SW22 and SW23 are turned on and SW
21 is turned off, and the drive voltage QS1 is output to the output node Q2. Therefore, the drive circuit DR1,
If two or more of DR2 and DS1 do not become defective at the same time, normal operation can be expected and the circuit scale can be made relatively small.

FIG. 28 is a block diagram of the tenth embodiment of the present invention. The tenth embodiment differs from the ninth embodiment in that
The normal drive circuits DR1 and DR2, the control circuit 1 (shift register 1), the switch circuits SW11 and SW21, and the defect detection circuit 1 (DD11 and DD21) are connected to each row (column) electrode ELD.
Of the pre-driving circuit SD1, the control circuit 2 (shift register 2), and the switch circuits SW21 and SW.
22, the switch circuits SW31 and SW32, and the defect detection circuit 2 are provided at the other end of each row (column) electrode ELD.
The shift registers 1 and 2 and the defect detection circuits 1 and 2 have the same configuration.

In the tenth embodiment, the normal drive circuit DR1 (D
The defect of R2) is detected by the defect detection circuits DD11, DD12 (DD
21, DD22), and after detecting and holding, DD11 (D
D21) controls the switch circuit SW11 (SW21), and DD12 (DD22) controls the switch circuit SW.
12 and SW13 are controlled. As a result, defects can be repaired with a relatively small circuit scale as in the ninth embodiment.

Further, in the tenth embodiment, the row (column) electrode E is used.
Since the defect detection / correction is performed with the LD sandwiched therebetween, not only the drive circuit failure but also the disconnection defect of the row (column) electrode ELD can be corrected. That is, even if DR1 (DR2) is normal, if the row (column) electrode ELD is disconnected, normally no voltage is applied to the end of the line, resulting in a display defect. However, the defect detection circuit DD12 (DD22) detects it as a failure and applies a voltage from the other end of the row (column) electrode ELD, so that no display defect occurs.

In the ninth and tenth embodiments, the examples of the digital data drivers DR1, DR2, DS1 are shown, but the invention is also applied to a known analog data driver for inputting and holding and outputting display data in analog. it can. In this case as well, if 0 V and 5 V are input to the analog input data and the same voltage is applied to the reference voltage T, the same defect detection and correction can be performed, and thereafter, the same is applicable.

The methods of the ninth and tenth embodiments can also be applied to known scan drivers. Two voltages, a selection voltage and a non-selection voltage, are input to the scan driver, and either voltage is generally selected and output according to H or L of the shift register output. Therefore, SI = H is set as the selection voltage. Is output and SI =
By checking whether the non-selection voltage is output as L,
The same defect detection and correction are possible.

Eleventh Embodiment FIG. 29 is a diagram showing the principle of the eleventh embodiment of the present invention.

In the eleventh embodiment, more row (column) electrodes than the number of lines in the row (column) direction of the display image are provided. In addition, drive circuits DR1, DR2 for driving each row (column) respectively.
.., and at least one defect detection circuit DD1, DD2 provided for each output of the drive circuit, and outputs a control signal to control the operation of the drive circuit and control based on the output of the defect detection circuit A control circuit CNTL for changing the signal is provided, and when a defect of the drive circuit is detected,
It is controlled so that the display contents are sequentially shifted and given to the adjacent non-faulty drive circuits.

In the eleventh embodiment, by adding a circuit of a very small scale, the display contents are given only to the drive circuit which has not failed but cannot correct the occurrence of the defect, so that the defect of the drive circuit is given. It is possible to eliminate the loss of image information due to, and it is possible to obtain substantially the same effect as when the defect is corrected.

FIG. 30 is a block diagram showing the essential parts of the eleventh embodiment of the present invention.

In the eleventh embodiment, the control circuit CNTL is composed of a shift register, and one multiplexer (MUX2, MUX3) is provided for each bit of the shift register.
...) is provided and the output NG _n of the defect detection circuit at the n-th stage is
Is connected to the control input S of the multiplexer MUX _{n + 1} of the ( _{n + 1) th} stage, and the output of the (n + 1) th bit of the shift register is connected to the input selected when S = L,
The output of the nth bit of the shift register is connected to the input selected when S = H.

The operation of the above configuration is shown in FIG.
Shown in. FIG. 31 is an example showing the operation of the digital data driver, and outputs CT1, CT2 ...
The corresponding drive circuits DR1, DR2 ... Take in the display data D3 to D0 when H is H and generate an output voltage.

When there is no defect in the drive circuit (NG1 = L,
NG2 = L, NG3 = L, ...), the multiplexer MUX2 selects the output of the second bit of the shift register to be CT2, and the multiplexer MUX3 selects the output of the third bit to be CT3. CTn has a form in which the start signal SI is sequentially shifted as shown by the solid line,
The display data DX1, DX2, DX3 are sequentially taken into the drive circuits DR1, DR2, DR3, respectively. on the other hand,
For example, if the drive circuit DR1 is defective (NG1 = H,
NG2 = L, NG3 = L, ...), since the multiplexer MUX2 selects the output of the first bit of the shift register, the shift register output CT
2 outputs a pulse at the same timing as CT1, and thereafter, the pulse is output earlier by each timing. As a result, the drive circuits DR1, DR2, DR3 are
1 (not displayed correctly), DX1 and DX2 are sequentially captured. Therefore, the display data DX1 is the conventional drive circuit D.
Although not displayed due to the defect of R1, it is displayed by the adjacent drive circuit DR2 and the subsequent display contents are sequentially shifted and displayed. Therefore, by adding a circuit having a simple configuration, it is possible to realize a liquid crystal display device in which image information is not lost.

FIG. 32 is a diagram showing a display example according to the eleventh embodiment. FIG. 32 shows an example in which a defect has occurred in the drive circuit at the position indicated by the arrow. In the conventional FIG. 32 (b), vertical lines are not displayed and the characters in FIG. 32 (a) cannot be recognized. In FIG. 32 (c) according to the eleventh embodiment, the defective lines are avoided and displayed one after another, so that they can be sufficiently recognized. When the present method is applied to a display device having a fine pixel pitch, a particularly great effect can be obtained.

When the number of defects is small, a line without corresponding image information naturally occurs. (Fig. 32 (a)
Therefore, the display data generating circuit (not shown) must send dummy data (for example, white display data) in addition to the normal display data, at least as many times as necessary when there is no defect. When to send
When the present invention is applied to the data driver, it is every 1H (horizontal period), and when it is applied to the scan driver, every 1V (vertical period).

Twelfth Embodiment FIG. 33 is a block diagram showing the essential parts of the twelfth embodiment of the present invention. In the twelfth embodiment, through the switch circuits (SN1, SN2, ...) Provided for each bit of the shift register and controlled by each output of the shift register, the defect detection circuits DD1, DD2 ,. The output is sequentially transferred to the defect position storage circuit DPS. The defect position storage circuit DPS performs control for inserting dummy data at the defect position and dummy data according to the number of defects in one row (column) before and after display data (data driver → left and right of image, scan driver → up and down of image). A data array operation control signal DACS for controlling the array is generated, and the data array operation circuit DACC inserts dummy data into the display data to control the array.

FIG. 34 shows a specific operation example. When there are two defects, 2 at the timing corresponding to the defect position.
Dummy data is inserted in each place, and one dummy data is inserted before and after the 1H display data. When there is no defect, two dummy data are inserted before and after the 1H display data.

As a result of the above, a display as shown in FIG. 35 is obtained. In the display according to the eleventh embodiment in FIG. 35, the positions of the left edge of the image are aligned regardless of the number of defects.
In the display according to this embodiment, the central positions of the images are aligned. As a result, applications where you want to display an image near the center regardless of the number of panel defects (viewfinder, TV
And the like) can be realized.

The number of dummy data to be inserted depending on the number of defects may be equal left and right (up and down), or may be different depending on the application.

In the twelfth embodiment, the example of the digital data driver is shown, but the present invention can be applied to an analog data driver for inputting and holding and outputting display data in analog. Also in this case, for example, 0V, 5 for analog input data
If the same defect detection and correction are performed by inputting V and applying the same voltage to the reference voltage T, the same can be applied thereafter.

The method of the twelfth embodiment can also be applied to the scan driver. Two voltages, a selection voltage and a non-selection voltage, are input to the scan driver, and either voltage is generally selected and output according to H or L of the output of the shift register. Therefore, SI = H is selected. By inspecting whether the voltage is output and inspecting whether the non-selection voltage is output with SI = L, the same defect detection and repair can be performed.

Thirteenth Embodiment FIG. 36 is a diagram for explaining the principle of the present invention, showing only the structure of a functional block corresponding to one stage of a shift register in a drive circuit integrated on a liquid crystal panel. .

Reference numeral 201 is a functional block constituting a drive circuit, and is constituted by arranging (multiplexing) some (or all) of the internal components in parallel. Reference numeral 220 is a non-multiplexed component, and 221 to 22k are components (eg, flip-flops) in which k circuits having the same function are provided in parallel and multiplexed. Further, 203 is a majority decision processing means for obtaining an output value occupying the majority of the multiplexed outputs 221 to 22k and using this as the output value of the functional block 201.

As a result of the above construction, when there is no defect in the component parts, 221 to 22k all output the same value (correct value), so the majority processing means 203 selects the correct value as the majority. Output. On the other hand, even if some of the k component parts 220 to 22k provided in parallel do not output a correct value and output a correct value (the output is fixed to H or L, etc.), the defect is generated. If the number of component parts that caused the occurrence is less than k / 2, the normal component parts are majority, and therefore the majority decision processing means 203 selects and outputs the correct value.

Therefore, according to the thirteenth embodiment, it is not necessary to inspect a defect, and when a defect occurs, it can be automatically repaired and operated.

The number k of components provided in parallel is
It is desirable that the number is an odd number in consideration of the ease of taking a majority decision, but the present invention is not limited to this, and a failure of a component is k.
/ When a defect occurrence rate of less than 2 is obtained,
It may be an even number if k is increased in consideration of the defect occurrence rate.

According to the principle of the present invention, the functional block 20
Although a column including a component 220 that is not multiplexed is shown in FIG. 1, this may be omitted and all components may be multiplexed.

FIG. 37 (a) is a block diagram showing the essential parts of the thirteenth embodiment of the present invention, and shows an example (3 bits) applied to a shift register required for a drive circuit of a liquid crystal display device. . In the thirteenth embodiment, a circuit corresponding to one bit of the shift register corresponds to the component parts 221 to 22k in which the D-FF (D flip-flop) of the shift register is multiplexed in the functional block 201 shown in FIG.

Reference numerals 411, 412, and 413 are circuits for 1 bit of the shift register, and the signals (S
I, QX11, QX12) are latched and output in synchronization with the clock signal CK (QX11, QX12, QX1).
3).

Since the internal configurations of 441, 412, and 413 are the same, the internal configuration will be described by taking 411 as an example. Reference numerals 211, 221, 231 are D-FF circuits, which respectively input the input signal SI to input Q11, Q21, Q31.
Is output. The thirteenth embodiment shows an example in which three D-FF circuits are provided in parallel and multiplexed. Reference numeral 311 is a circuit for detecting a signal mismatch, and here, an exclusive OR (X
The OR circuit is used to compare Q11 and Q21 and output the non-coincidence signal NE1. A multiplexer 321 selects and outputs either the Sel = H input or the Sel = L input according to the value of the Sel input. As the configuration of the multiplexer, for example, FIG.
It may be composed of logic gates G3, G4 and G5 as shown in FIG. 37B, or may be an inverter INV as shown in FIG.
Alternatively, a transfer gate including the transistors TR1 and TR2 may be used. Although the circuit can be downsized in FIG. 37C, since a voltage higher than the voltage applied to the drain is required to drive the transfer gate,
An inverter circuit with a level shift function of another power supply is required.

The operation of the circuit configured as described above is shown in FIG.
Will be explained.

When there is no defect in the D-FF circuits 211, 221, and 231, Q11, Q21, and Q31 have pulse waveforms obtained by shifting the start signal SI by 1CK as indicated by the solid line, and Q11 = Q21. Always L
(Match). Therefore, the multiplexer 321 always selects and outputs Q11 and outputs a normal pulse waveform to QX11. On the other hand, for example, when a defect occurs in the D-FF circuit 211 and Q11 is always fixed to L (broken line), originally Q
Since Q11 ≠ Q21 during the period of 11 = H, NE
1 = H (mismatch) (broken line). Therefore, NE1 = L
The multiplexer 321 selects and outputs Q11 during the period of, and the output Q31 of the standby circuit is selectively output during the period of NE1 = H. As a result, Q31 (majority H) is output during the period when Q11 cannot output H, so QX1
A normal panel waveform is output at 1.

Further, for example, when a defect occurs in 222, Q22
Is always fixed to H (broken line), Q22 ≠ Q12 during the period when Q22 = L originally, so NE2 = H (mismatch) (broken line). Therefore, 322 selectively outputs Q12 during the period of NE2 = L, and selectively outputs the output Q32 of the standby circuit during the period of NE2 = H. As a result, Q22
Q32 (majority L) during the period when outputs the wrong value
Is output, the normal pulse waveform is output to the QX12 in this case as well.

Further, for example, when a defect occurs in the spare circuit 233 and Q33 is always fixed to L (broken line), Q1
Since 3 and Q23 output a normal waveform, NE3 is always L (match) and 323 always selects and outputs Q13 (majority waveform). Therefore, a normal pulse waveform is output to QX13.

As described above, if any one of the multiplexed components (less than 3/2) fails, a normal signal (majority) is selected and output. It is possible to realize a circuit configuration that is not necessary and that can be automatically repaired when a defect occurs.

Fourteenth Embodiment FIG. 39 is a block diagram of the fourteenth embodiment of the present invention.
The same parts as those in the third embodiment are designated by the same reference numerals.

Also in the fourteenth embodiment, 411, 41
Since the internal configurations of 2 and 413 are the same, the configuration will be described by taking 411 as an example. 331a, 331b, 331c are the first
ON / OFF control is performed by the control signal T1 of the above, and reference numerals 351a, 351b, and 351c are switch means that are ON / OFF controlled by the second control signal T2. Further, 341a, 341b and 341c are capacitive elements, one end of which is connected to the GND level. Further, 361 is an amplifying means having an input / output characteristic as shown in FIG. 39 (d). Here, VH is the H level voltage (for example, 5V) of the signal, and VL is the L level voltage (for example, 0V). The amplifying means 361 has, for example, a configuration using an operational amplifier (or a comparator) as shown in FIG. 39 (b) or an inverter having a threshold value set to (VH + VL) / 2 as shown in FIG. 39 (c). There is a configuration in which two stages are connected.

In the fourteenth embodiment, the D-FF circuit 211,
221 and 231 are respectively connected to one end of the switch means 1, the other end of the switch means 1, the other end of the capacitive element and one end of the switch means 2 are connected respectively, and the other ends of the switch means 2 are all connected. It is configured by short-circuiting and connecting to the input of the amplifying means.

The operation of the circuit configured as described above is shown in FIG.
Will be explained. When there is no defect in 211, 221, 231, Q11, Q21, Q31 have pulse waveforms obtained by shifting SI by 1CK as shown by the solid line, and the first control signal T1 is applied to the capacitive elements 341a, 341b, 341c.
The voltages of Q11, Q21, Q31 are latched in synchronization with (V41a, V41b, V41c). And T1 =
When L, T2 = H and one end of each capacitance element is short-circuited, the average voltage of V41a, V41b, V41c becomes IX11. In this case, the pulse waveforms of the levels of VL and VH are obtained, and the amplifier circuit 3 having the threshold value of (VH + VL) / 2
61 is a normal pulse waveform of the level of VL and VH QX1
Output as 1.

On the other hand, for example, when a defect occurs in the D-FF circuit 211 and Q11 is constantly fixed to L (broken line), the average voltage is originally maintained during the period of Q11 = H and T1 = L, T2 = H. As a result, IX11 becomes (2 · VH + VL) / 3. That is, the pulse waveform is VL and (2 · VH + VL) / 3. When this IX11 is input to the amplifier circuit 361, the input VL level is output as VL, and (2
Since VH + VL) / 3 is larger than (VH + VL) / 2, it is output as VH. Therefore, the D-FF circuit 21
Even when a defect occurs in 1 and Q11 is always fixed to L, a normal pulse waveform is output as QX11.

Further, for example, when a defect occurs in the D-FF circuit 222 and Q22 is constantly fixed to H (broken line), the average voltage is normally maintained during the period when Q22 = L and T1 = L and T2 = H. As a result, IX12 becomes (VH + 2 · VL) / 3. That is, a pulse waveform of (VH + 2 · VL) / 3 and VH is obtained. When this IX12 is input to the amplifier circuit, the input VH level is output as VH, and (VH +
Since 2 · VL) / 3 is smaller than (VH + VL) / 2, it is output as VL. Therefore, even when a defect occurs in the D-FF circuit 222 and Q22 is always fixed at H, a normal pulse waveform is output as QX12.

As described above, if any one of the multiplexed components (less than 3/2) fails, the average value with the normal signal level (majority) is taken and the By amplifying, a majority of signal levels are output, so that it is possible to realize a circuit configuration that does not require inspection of defects and that can automatically repair even when defects occur. . Also, in the fourteenth embodiment, the majority processing circuit can be made relatively small.

[0271]

According to the first aspect of the invention, the redundant configuration has a plurality of delay elements for each stage, and the output of each stage selectively outputs the plurality of delay elements by a selection signal common to each stage. Since it is used, the influence of the defect of the shift register can be easily avoided with a simple configuration.

According to the fourth aspect of the present invention, the defect detecting means is provided in each stage of the shift register to perform control for selecting any one of the plurality of delay elements having the redundant configuration. Therefore, there is a defect in the shift register. However, it is possible to automatically avoid the influence of defects and ensure normal operation.

According to the seventh aspect of the invention, the drive circuit for receiving the control signal from the control means and driving the signal line has a redundant structure, and if the normal drive circuit has a defect, it is automatically detected by the defect detection means. Since the pre-driving circuit is selected, normal operation can be ensured even if the normal driving circuit is defective.

According to the eighth aspect of the present invention, a pre-driving circuit is provided for each of the m normal driving circuits, and by the operation of the first, second and third switch means under the control of the defect detecting means, a defect is generated. Since one normal drive circuit with a normal drive circuit is automatically switched to the pre-drive circuit, compared to the invention of claim 7, a structure with a small degree of redundancy automatically avoids the influence of defects in the normal drive circuit and operates normally. The operation can be secured.

According to the tenth aspect of the invention, the display element is provided with redundancy in advance so that the display can be performed in a range larger than a predetermined display area in the row and / or column direction. Since the control means jumps over the defective signal line to display the data, it does not require the defect detection operation, and even when the display information is defective, the defective display element is skipped over the row or column where the defective display element is present. Also, it can be displayed in an identifiable state.

According to the thirteenth aspect of the present invention, since the output of each stage of the shift register is determined by the majority decision of its input signal, it is not necessary to inspect the defect, and when the defect occurs, it is affected by this defect. It is possible to continue the correct operation automatically without any action.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the first embodiment of the present invention.

FIG. 2 is a diagram illustrating the principle of the second embodiment of the present invention.

FIG. 3 is an explanatory view of a main part of a second embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of the second embodiment of the present invention.

FIG. 5 is an explanatory diagram of another configuration example of the main part of the second embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of the second embodiment shown in FIG. 5 of the present invention.

FIG. 7 is a diagram illustrating the principle of the third embodiment of the present invention.

FIG. 8 is an explanatory view of the principle of the fourth embodiment of the present invention.

FIG. 9 is an explanatory view of a main part of a fourth embodiment of the present invention.

FIG. 10 is an operation explanatory diagram of the fourth embodiment of the present invention.

FIG. 11 is an explanatory diagram of another configuration example of the main part of the fourth embodiment of the present invention.

FIG. 12 is a diagram illustrating the principle of the fifth embodiment of the present invention.

FIG. 13 is an explanatory view of a main part of a fifth embodiment of the present invention.

FIG. 14 is an operation explanatory diagram of the fifth embodiment of the present invention.

15 is a diagram showing a shift register formed by connecting the circuits shown in FIG. 12 in cascade.

16 is an explanatory diagram of the operation of the shift register shown in FIG.

FIG. 17 is an explanatory diagram of another configuration example of the fifth embodiment of the present invention.

FIG. 18 is a diagram illustrating the principle of the sixth embodiment of the present invention.

FIG. 19 is a diagram illustrating the principle of the seventh embodiment of the present invention.

FIG. 20 is an explanatory diagram of a main part of a seventh embodiment of the present invention.

FIG. 21 is an operation explanatory diagram of the seventh embodiment of the present invention.

FIG. 22 is an explanatory diagram of a main part of an eighth embodiment of the present invention.

FIG. 23 is an operation explanatory diagram of the eighth embodiment of the present invention.

FIG. 24 is a diagram illustrating the principle of the ninth embodiment of the present invention.

FIG. 25 is an explanatory view of a main part of a ninth embodiment of the present invention.

FIG. 26 is a diagram showing a configuration example of a defect detection circuit of a ninth embodiment.

FIG. 27 is an operation explanatory view of the ninth embodiment of the present invention.

FIG. 28 is a diagram illustrating the principle of the tenth embodiment of the present invention.

FIG. 29 is a diagram showing the principle of the eleventh embodiment of the present invention.

FIG. 30 is an explanatory view of essential parts of an eleventh embodiment of the present invention.

FIG. 31 is an operation explanatory diagram of the eleventh embodiment of the present invention.

FIG. 32 is a diagram showing a display example according to the eleventh embodiment of the present invention.

FIG. 33 is an explanatory view of the essential parts of the twelfth embodiment of the present invention.

FIG. 34 is an operation explanatory view of the twelfth embodiment of the present invention.

FIG. 35 is a diagram showing a display example according to the twelfth embodiment of the present invention.

FIG. 36 is a diagram illustrating the principle of the 13th embodiment of the present invention.

FIG. 37 is an explanatory view of the essential parts of the thirteenth embodiment of the present invention.

FIG. 38 is an operation explanatory diagram of the thirteenth embodiment of the present invention.

FIG. 39 is an explanatory view of essential parts of a fourteenth embodiment of the present invention.

FIG. 40 is an operation explanatory diagram of the 14th embodiment of the present invention.

FIG. 41 is a diagram showing a configuration example of a liquid crystal display device.

FIG. 42 is a diagram showing a configuration example of a conventional data line drive circuit.

FIG. 43 is a diagram showing an example of a shift register configured so that a defect in a register can be repaired.

[Explanation of symbols]

1 Liquid crystal display panel 9 _ij Delay element

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichi Nakabayashi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (14)

[Claims] 1. A drive circuit for driving a display element of a liquid crystal display device, comprising shift register means for outputting n control signals for driving n signal lines coupled to the display element, the shift circuit comprising: The circuit of each stage of the register means delays the input signal of the circuit by a unit time, and a plurality of delay elements (9 _ij ; 11 _ij ; 13 _ij : i =) connected in parallel.
1-n, j = 1-k) and a selecting means (10 _i ; 1) for selecting any one of the output signals of the plurality of delay elements as a control signal output from the circuit.
2 _i ; 14 _i ), and the selection means of the circuit of each stage has a selection signal (S;
A driving circuit for a liquid crystal display device, which operates according to SEL). 2. The means of each stage has two delay elements, and the selection means is a switch (9 _ij ) connected to one of the two delay elements. A drive circuit for the liquid crystal display device described. 3. The drive circuit for a liquid crystal display device according to claim 1, wherein the common selection signal is a signal for time-division controlling the selection means of the circuits in each stage. 4. A drive circuit for driving a display element of a liquid crystal display device, comprising shift register means for outputting n control signals for driving n signal lines coupled to the display element, the shift circuit comprising: The circuit of each stage of the register means delays the input signal of the circuit by a unit time and has a plurality of delay elements connected in parallel (15 _ij ; 18 _ij ; 22 _ij ).
Selecting means (16 _i ; 20; 25) for selecting one of the output signals of the plurality of delay elements as a control signal output from the circuit according to the selection signal, and at least one of the plurality of delay elements. Defect detecting means (17 _i ; 21;) for detecting one defect and generating the selection signal.
26) A driving circuit for a liquid crystal display device, comprising: 5. The circuit of each stage has first, second, third and fourth delay elements, and the drive circuit is responsive to states of output signals of the first and second delay elements. A first gate circuit (19 ₁ ) that outputs a first gate signal, and a second gate circuit (19 ₂ ) that outputs a second gate signal according to the output signals of the third and fourth delay elements. And selecting the first gate signal or the second gate signal based on the input signal and the first gate signal, and outputting the control signal. The drive circuit for the liquid crystal display device according to claim 4. 6. The circuit of each stage has first, second and third delay elements, and the drive circuit outputs a gate signal according to a state of output signals of the first and second delay elements. Output gate circuit (24)
Wherein the selection means selects either the gate signal or the output signal of the third delay element based on the input signal and the gate signal, and outputs the control signal. 4. The drive circuit of the liquid crystal display device according to 4. 7. A drive circuit for driving a display element of a liquid crystal display device, n normal drive circuits (29 _i ) for driving n signal lines coupled to the display element, and n normal drive circuits N pre-driving circuits (30 _i ), control means (28) for outputting control signals for controlling the operations of the n normal driving circuits, and defects of the n normal driving circuits, respectively. Defect detection means (32 _i ) for detecting and outputting n selection signals, and in each of the n signal lines, either the normal drive circuit or the preliminary drive circuit is connected to the signal line in accordance with the corresponding selection signal. And a selecting means (31 _i ) connected to the drive circuit of the liquid crystal display device. 8. In a drive circuit for driving a display element of a liquid crystal display device, n normal drive circuits (DR1, DR2) for driving n signal lines coupled to the display element and m (m <n ) A pre-driving circuit (DS1) provided for each regular driving circuit, control means (CNTL) for outputting control signals for controlling the operations of the n regular driving circuits, and n regular driving circuits, respectively. First switch means (SW11, SW21) connected to the corresponding n signal lines
And second switch means (S) for selectively supplying the control signals to the m normal drive circuits to the preliminary drive circuit.
W12, SW22) and third switch means (SW1) for selectively connecting the preliminary drive circuit to the signal lines relating to the m normal drive circuits.
3, SW23), and detecting defects of each of the m normal drive circuits,
When a defect is detected in any one of the m normal drive circuits, the first, second, and the first drive circuits are configured so that the preliminary drive circuit drives the signal line corresponding to the normal drive circuit in which the defect is detected. Defect detecting means (DD) for controlling the switch means of No. 3
1. DD2), and a drive circuit for a liquid crystal display device. 9. The liquid crystal according to claim 8, wherein the first switch means is provided at one end of the signal line, and the second and third switch means are provided at the other end of the signal line. Drive circuit of display device. 10. A drive circuit for driving a display element of a liquid crystal display device, n drive circuits (DR1-DR3) for driving n signal lines coupled to a display element including a redundant display element, n Defect detection means (DD1-DD3) for detecting defects of each of the driving circuits, and the operation of the n driving circuits so that display is performed only by a normal driving circuit other than the driving circuit in which the defect is detected. A control circuit (CNTL) for controlling the liquid crystal display device drive circuit. 11. If the drive circuit of the i-th stage is not defective, the control means gives the next operation timing of the drive circuit of the i-th stage as the operation timing of the drive circuit of the i + 1-th stage, 11. The drive circuit for a liquid crystal display device according to claim 10, further comprising means for giving the operation timing of the i-th stage drive circuit to the i + 1-th stage drive circuit when the eye drive circuit is defective. 12. The control means, for each scan, according to the ratio of the number of defective display elements and the number of redundant display elements detected by the defect detecting means, the n dummy data items. 12. The drive circuit for a liquid crystal display device according to claim 10, further comprising means (DPS, DACC) for sequentially applying the display position to the drive circuit according to claim 1. 13. A drive circuit for driving a display element of a liquid crystal display device, wherein shift register means (411, 4) for outputting n control signals for driving n signal lines coupled to the display element.
12, 413), and the circuit of each stage of the shift register means delays the input signal of the circuit by a unit time, and a plurality of delay elements (221, 222, 22k) connected in parallel are provided.
And a majority decision processing means (203) for taking a majority decision of the output signals of the plurality of delay elements and using it as a control signal output from the circuit, a drive circuit of a liquid crystal display device. 14. The liquid crystal display device according to claim 1, wherein the drive circuit is integrated in a liquid crystal display panel (1) on which the display element is formed. Drive circuit.