JP3136066B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display having a function of correcting a disconnection of a bus wiring.

[0002]

2. Description of the Related Art As conventional liquid crystal display devices having a function of correcting a disconnection of a bus wiring, Japanese Patent Application Laid-Open Nos.
-98023 and JP-A-3-259222. In these prior arts, a disconnection of the gate bus line or the source bus line is dealt with by providing a spare line connectable to the gate bus line or the source bus line.

FIG. 5 is a diagram showing the simplest case as an example of correction of disconnection due to the above-mentioned spare wiring. As shown in FIG. 5, a plurality of gate bus wirings 2 and source bus wirings 1a and 1b each having a pixel electrode connected to each intersection via an active element such as a switching transistor are provided so as to intersect with each other. At both ends of the wires 1a and 1b,
The spare wirings 3a and 3b are connected to the source bus wiring 1 via the insulating film.
a, 1b. One ends 4a and 4b of the spare wirings 3a and 3b are led out of the liquid crystal display panel and can be connected to each other.

In a liquid crystal display device provided with such spare lines 3a and 3b, as shown in FIG. 5, when a disconnection 5 occurs in the source bus line 1b, the source bus line 1b having the disconnection and the spare line 3a are disconnected. , 3b at connection position 5
a, 5b, which are connected via an insulating film,
One end portions 4a and 4b of a and 3b are connected to each other.
As a result, a signal voltage can be supplied to all the active elements connected to the source bus line 1b where the disconnection 5 has occurred.

[0005]

When a signal voltage is supplied to the source bus line 1b having the broken line 5 as described above via the spare lines 3a and 3b, the source bus line 1b having the broken line 5 is connected. In comparison with the other source bus lines 1a and 1b, the spare lines 3a and 3b and the lines connected thereto have longer wiring lengths and higher impedances, and as a result, output signals to the source bus lines 1a and 1b. The signal level of the signal voltage supplied to the source bus line 1b whose disconnection 5 has been corrected is lower than the signal level of the signal voltage supplied to the other source bus lines 1a and 1b due to the insufficient capacity of the drive circuit that performs the disconnection. Become. When the signal level is reduced in this way, for example, when a black achromatic single-color screen is displayed on the liquid crystal display panel whose disconnection has been corrected, the portion of the source bus line 1b whose disconnection has been corrected is, for example, brighter than other portions. It may look like a line, resulting in poor image quality.

An object of the present invention is to correct a voltage value of a signal voltage applied to a signal line having a higher impedance than other signal lines to a predetermined value, thereby improving image quality. It is to provide a liquid crystal display device.

[0007]

According to the present invention, there is provided a liquid crystal display panel comprising: (a1) a first substrate, on which a plurality of signal lines 20 and 21 are arranged in parallel. Are arranged, and these signal lines and a plurality of control signal lines 22 intersect to form an intersection,
Each of the intersections is provided with a pixel electrode and a drive element for connecting and disconnecting a signal line forming an intersection with the control signal line to and from the pixel electrode in response to a drive control signal from the drive signal line. A liquid crystal display panel including: a first substrate; (a2) a second substrate on which a counter electrode facing the entire surface of the first substrate is formed; and (a3) a liquid crystal layer interposed between the first and second substrates. (B) scanning and applying a signal voltage to the signal line;
In a liquid crystal display device provided with drive circuits 16 and 17 for applying a drive control signal to a control signal line in synchronization with a signal voltage and driving picture elements, (c) the voltage between adjacent signal lines is Detecting means for detecting that the impedance of one of the signal lines is higher than a predetermined threshold value due to being higher than the impedance of the other signal line; and (d) responding to the output of the detecting means. A liquid crystal display device comprising: voltage correction means for correcting a voltage value of a signal voltage applied to a signal line. Also, the present invention
In the liquid crystal display panel, a spare wire that intersects at least a part of the plurality of signal lines via an insulating film at both end portions of each signal line is formed, and the spare wire drawn out of the liquid crystal display panel is formed. One end is connectable to each other, the spare line is connected to the signal line in which the disconnection has occurred, and a signal voltage is applied through the spare line. Further, according to the present invention, a signal generating means for generating a uniform internal video signal for at least one horizontal scanning period, and a control signal based on the internal video signal for a predetermined period is output to the driving circuit. And a control unit that outputs a control signal based on an external video signal input from the outside to the drive circuit, and instructs the voltage correction unit to correct a voltage value in the predetermined period. Further, the present invention outputs a control signal to the drive circuit based on a video signal input from the outside,
Control means for instructing the voltage correction means to correct a voltage value at a timing when a signal of a uniform level is input during a blanking period between field periods of an input video signal. Features. The present invention also provides (a) a liquid crystal display panel, (a1) having a first substrate, in which the plurality of signal lines 20 and 21 are arranged in parallel, and these signal lines and , A plurality of control signal lines 22 intersect to form an intersection,
Each of the intersections is provided with a pixel electrode and a drive element for connecting and disconnecting a signal line forming an intersection with the control signal line to and from the pixel electrode in response to a drive control signal from the drive signal line. A liquid crystal display panel including: a first substrate; (a2) a second substrate on which a counter electrode facing the entire surface of the first substrate is formed; and (a3) a liquid crystal layer interposed between the first and second substrates. (B) scanning and applying a signal voltage to the signal line;
In a liquid crystal display device including drive circuits 16 and 17 for applying a drive control signal to a control signal line in synchronization with a signal voltage to drive picture elements, (c) the voltage between adjacent control signal lines is Detecting means for detecting that the impedance of one adjacent control signal line is higher than a predetermined threshold value due to the higher impedance of the other control signal line; and (d) detecting the output of the detecting means. A liquid crystal display device comprising: a voltage correction unit that responsively corrects a voltage value of a drive control signal voltage applied to a control signal line.

[0008]

According to the present invention, the voltage between adjacent signal lines is
Detecting means for detecting that the impedance of one of the adjacent signal lines is larger than a predetermined threshold value due to being higher than the impedance of the other signal line;
Voltage correction means for correcting the voltage value of the signal voltage applied to the signal line in response to the output of the detection means. This is the same for the control signal line.

As a result of detecting that the voltage between the signal lines is larger than a predetermined threshold value by the detecting means, one of the adjacent signal lines is changed due to a disconnection correction described later or a variation in the thickness of the signal lines caused in the manufacturing process. When the voltage between the adjacent signal lines is greater than a predetermined threshold value due to the line impedance being higher than the impedance of the other signal line, the voltage correction means Accordingly, the voltage value of the signal voltage applied to the signal line having the higher impedance is corrected. As a result, for example, when a signal voltage is applied to a signal line having a high impedance and the voltage value of the signal voltage is reduced from a predetermined value by an amount corresponding to the increase in the impedance, the voltage becomes a predetermined value. Is corrected to

Therefore, the voltage value of the signal voltage applied to the signal line having a higher impedance than other signal lines can be corrected to a predetermined value, and as a result, an image is displayed on the liquid crystal display device. Prevents a part corresponding to a high impedance signal line from being displayed brighter than a part corresponding to other signal lines, for example, due to a disconnection correction described later or a variation in a manufacturing process. And the image quality of the liquid crystal display device can be improved.

Further, since the voltage value of the signal voltage is corrected in accordance with the impedance of the signal line and the image quality is improved, the liquid crystal display device which has been conventionally discarded due to poor image quality can be replaced with a signal voltage value. By performing the correction, a non-defective product can be obtained. As a result, the yield of the liquid crystal display device can be improved, and the manufacturing cost can be reduced.

Further, according to the present invention, the liquid crystal display panel is provided with a spare line which intersects at least a part of the plurality of signal lines via the insulating film at both ends of each signal line, and Are connected to each other. In the liquid crystal display device configured as described above, when a disconnection occurs in a signal line, the disconnected signal line and spare wirings formed at both ends of the signal line are connected via an insulating film. Are connected to each other. As a result, the disconnection of the signal line is corrected, and the signal voltage can be supplied to the disconnected signal line.

The signal line to which the disconnection has been corrected and the spare line has been connected has a longer wiring length and a higher impedance than the signal line which has not been subjected to the disconnection correction. As described above, the voltage value of the signal voltage applied to the signal line is corrected by the voltage correction unit in accordance with the detection value of the detection unit, so that it is possible to prevent the image quality of the liquid crystal display device whose disconnection has been corrected from deteriorating. .

Further, according to the present invention, for example, when the power is turned on, a control signal based on a uniform internal video signal for at least one horizontal scanning period for a predetermined period is input from the control means to the drive circuit, and a uniform control signal is inputted. A signal voltage is applied to each signal line at a uniform output level corresponding to the video signal. At this time, the detecting means detects the impedance of each signal line by, for example, detecting the voltage value of the signal voltage actually applied to each signal line. From the voltage correction means,
The voltage corrector changes, for example, the output level of the drive circuit according to the detection value of the detector, whereby the voltage value of the signal voltage actually applied to each signal line is corrected to a predetermined value.

After the voltage value is corrected and the predetermined period elapses, an image based on an externally input external video signal is displayed in a state where the image quality is improved by the voltage value correction. Is performed.

Therefore, since the voltage value is corrected using the uniform internal video signal created by the signal creating means, the voltage value can be reliably corrected at a desired timing.

According to the present invention, the voltage value is corrected during the blanking period of the video signal input from the outside. Therefore, there is no need for a signal generating means for generating a uniform video signal, and the voltage value can be corrected at low cost.

[0018]

FIG. 1 shows a voltage correction unit 5 provided in driving circuits 16 and 17 of a liquid crystal display device 51 according to an embodiment of the present invention.
FIG. 3 is a block diagram showing an electrical configuration of the second embodiment. FIG. 2 is a plan view showing the configuration of the liquid crystal display device 51. Referring to FIG. 2, a liquid crystal display device 51 includes a liquid crystal display panel 15 and a resin film 1 on which drive circuits 16 and 17 are respectively mounted.
8 and 19 and a control circuit 61.

The liquid crystal display panel 15 has a plurality of source bus lines 20, 21 which are a plurality of signal lines parallel to each other, a plurality of gate signal lines 22 which are a plurality of control signal lines intersecting with the source bus lines 20, 21, and a source bus line. A first substrate in which picture element electrodes connected via driving elements such as switching transistors are formed at intersections between the gate bus lines 22 and 20, 21 and a second substrate in which a counter electrode is formed over the entire surface. It is configured by being laminated with a liquid crystal layer in between.

In the liquid crystal display panel 15, both ends of the source bus wirings 20, 21 (ie, upper and lower ends in FIG. 2) are provided via the insulating films on the source bus wirings 20, 21.
Are formed in parallel with the gate bus line 22.

The resin films 18 and 19 are respectively connected to the upper and lower ends of the liquid crystal display panel 15 in FIG.
The source bus wirings 20 and the source bus wirings 21 are alternately arranged, and the drive circuit 16 mounted on the upper resin film 18 in FIG. The drive circuit 17 mounted on the lower resin film 19 in FIG. 2 is similarly connected to the source bus wiring 21 through the corresponding lead line 41. 42.

The lead wires 25 and 26 provided on the resin films 18 and 19 are connected to the spare wires 23 and 24, respectively. The lead lines 25 and 26 can be electrically connected by lead lines provided on a control board (not shown).

The gate bus wiring 22 of the liquid crystal panel 15
Also, a drive circuit mounted on a resin film (not shown) is connected.

In the liquid crystal display device 51 thus configured, the driving circuit connected to the gate bus wiring 22 scans the gate bus wiring 22 based on the control signal output from the control circuit 61 to each driving circuit. Gate bus wiring 2
2 is supplied with a gate signal, which is a drive control signal, and the drive circuits 16 and 17 scan the source bus lines 20 and 21 in synchronization with the scanning of the gate bus line 22 while scanning the source bus lines 2 and 21.
By supplying the source signals to 0 and 21, the picture elements of the liquid crystal display panel 15 are driven, and an image is displayed.

In a manufacturing process of the liquid crystal display device 51 or the like, if a disconnection 28 occurs in the source bus line 29 included in the source bus line 20 of the liquid crystal display device 51, the source bus line 29 and the spare lines 23 and 24 are connected. , Intersection 30,3
1, a lead 25 connected to the spare wiring 23 and connected to the spare wiring 24 and a lead 26 connected to the spare wiring 23 are electrically connected to each other by a lead provided on a control board (not shown). Is done. 2, the active element connected to the source bus wiring 29 on the lower side of the disconnection 28 in FIG. 2, that is, on the side opposite to the drive circuit 16 side with respect to the disconnection 28, the spare wiring 23 and the lead-out line 25, not shown. The source signal from the drive circuit 16 is supplied via the lead line, the lead line 26 and the spare line 24 provided on the control board, and the disconnection 28 is corrected.

In the source bus lines 20 and 21 in which such disconnection correction has been performed, the drive circuit 16
Or source bus lines 20, 21 on the opposite side to 17
Is applied to the active elements connected through the auxiliary wires 23, 24 and the lead wires 25, 26, etc.
21 and the spare wires 23 and 24 and the lead wire 2
The wiring length becomes longer by 5, 26, etc., and the impedance becomes higher.

As shown in FIG. 1, it should be noted that in the present embodiment, the voltage correction unit 52 for correcting the voltage value of the signal voltage whose impedance has been increased due to the correction of the disconnection and whose voltage value has been reduced is provided by the drive circuit 16. , And 17 respectively. Here, the voltage correction unit 52 provided in the drive circuit 16 will be described.

The voltage correction unit 52 is connected to each source bus line 20
, A plurality of buffers B, a comparator C, a latch circuit R and a switch S
W.

Based on the input clock signal CK and data signal RGB, the sample and hold circuit 5
When a drive signal is input to each buffer B from 3, each buffer B is supplied with an input drive signal and a bias voltage V 1 or a bias line 56 supplied from a bias line 55 via each switch SW. A predetermined source signal is output to each corresponding source bus line 20 based on the bias voltage V2.

Here, the bias voltage V1 is set higher than the bias voltage V2, and the bias voltage V2 is applied to the buffer B which is electrically connected to the source bus line 20 on which the disconnection has not been corrected. Then, the bias voltage V1 is applied to the buffer B electrically connected to the source bus line 20 whose disconnection has been corrected. The switching of the bias voltages V1 and V2 is performed by a switch SW based on a latch signal from a latch circuit R as described later.
Done by The bias voltages V1 and V2 are for determining the output level of the buffer B. When the bias voltage V1 is applied to the buffer B, the buffer B has a higher source signal than when the bias voltage V2 is applied. At a high output.

Each comparator C has two comparators C
Two input bus lines 20 adjacent to each other
, Which is electrically connected to the liquid crystal display panel 15 side of the buffer B and is applied to two adjacent source bus lines 20. When the difference between the voltage values is larger than a predetermined threshold value, a high-level detection signal is output to the corresponding latch circuit R. When the difference between the voltage values is equal to or smaller than the predetermined threshold value, The level detection signal is output to the corresponding latch circuit R. Here, for example, when a black achromatic single-color screen is displayed on the liquid crystal display device 51, the threshold value corresponds to the portion corresponding to the source bus line 20 whose disconnection has been corrected and the source bus line 20 whose disconnection has not been corrected. Is set to the lowest value recognized by the eyes.

Each latch circuit R responds to the clock signal input from the control circuit 61 via the signal line 54 at the timing when the voltage value of the signal voltage is to be compared by the comparator C, and receives the input from the corresponding comparator C. The latched detection signal is latched, and a high-level latch signal is output to a corresponding switch SW when the latched detection signal is at a high level, and a low-level latch is output when the latched detection signal is at a low level. The signal is output to the corresponding switch SW.

Here, the latch circuit R outputs a low-level latch signal until the clock signal is input via the signal line 54, and after the clock signal is input and latched, the latch circuit R latches. The latch signal to be output is held at a high level or a low level depending on whether the detection signal is at a high level or a low level.

Each switch SW is connected to a corresponding latch circuit R
Is high, the bias voltage V1 from the bias line 55 is applied to the corresponding buffer B. When the latch signal is low, the bias voltage V2 from the bias line 56 is applied. Apply to buffer B.

In the voltage correction unit 52 thus configured, a clock signal is input to the latch circuit R via the signal line 54, and each switch SW is switched based on a detection signal output from the comparator C. When the buffer B is output from the sample and hold circuit 53,
Are supplied with drive signals having the same signal level. At this time, the bias voltage V2 is applied to each buffer B via the switch SW, and regardless of whether the source bus wiring 20 electrically connected to each buffer B is broken or not, Each buffer B
Outputs a source signal at an output level corresponding to the bias voltage V2.

When the source signal is output as described above, if all the source bus lines 20 have not been corrected for disconnection, the impedance of each source bus line 20 is equal. The signal voltages of the source signals to be output are all equal, and each comparator C outputs a low-level detection signal. When a clock signal is input to the latch circuits R via the signal line 54 at a predetermined timing, each latch circuit R outputs a low-level latch signal corresponding to the low-level detection signal to the switch SW.

Therefore, if the disconnection has not been corrected in all the source bus lines 20, each latch circuit R has to be compared with the timing of comparison of signal voltage values.
The latch signal is held at the low level both before and after the clock signal is input to the buffer B, and the bias voltage V2 is supplied to each buffer B via the switch SW.
Is kept applied.

On the other hand, for example, when the above-described disconnection correction is performed on the n-th source bus line 20, the n-th source bus line 20 is connected to another source line on which the disconnection correction is not performed. Since the impedance is higher than that of the bus line 20, it is necessary to switch the switch SWn corresponding to the nth source bus line 20 to apply the bias voltage V1 having a higher voltage value than the bias voltage V2 to the buffer Bn. is there.

When a drive signal having the same signal level is input to each buffer B and a source signal corresponding to the drive signal is output from each buffer B to the corresponding source bus line 20 at the same output level, the n-th signal is output. The source bus wiring 20 has a higher impedance than the other source bus wirings 20, so that the signal voltage of the source signal actually applied to the n-th source bus wiring 20 is lower than that of the other source bus wirings 20 due to insufficient capacity of the buffer B. The signal voltage is lower than the signal voltage of the source signal applied to the source bus line 20.

As described above, the (n-1) th source bus wiring 2
When a difference greater than a predetermined threshold value occurs between the voltage value of the signal voltage applied to 0 and the voltage value of the signal voltage applied to the n-th source bus line 20, the (n-1) -th Source bus line 20 and n-th source bus line 20
, The detection signal of the comparator Cn electrically connected to the high level becomes high level, whereby it is detected that the impedance of the n-th source bus line 20 is high due to the disconnection correction.

The high-level detection signal output from the comparator Cn is latched by the latch circuit Rn at the timing of the clock signal input via the signal line 54, and the latch signal output from the latch circuit Rn accordingly. Is switched from a low level to a high level. When the latch signal is switched from low level to high level, the switch SWn switches the bias voltage V2 to the buffer B.
n is switched to a state in which the bias voltage V1 is applied to the buffer Bn.

As a result, the output of the source signal in the buffer Bn is increased from a low output corresponding to the bias voltage V2 to a high output corresponding to the bias voltage V1,
As a result, when the achromatic single-color screen is to be displayed, the signal voltage actually applied to the n-th source bus line 20 having the high impedance due to the disconnection correction and the disconnection correction are not performed. The voltage value of the signal voltage supplied to the n-th source bus line 20 is corrected so that the signal voltage actually applied to the source bus line 20 of the first line becomes equal.

In order to perform such a voltage value correction,
After turning on the power of the liquid crystal display device 51, it is necessary to input a uniform data signal RGB for at least one horizontal scanning period to the sample and hold circuit 53. As a method of inputting a uniform data signal RGB for one horizontal scanning period to the sample-and-hold circuit 53, a first method in which a signal generating circuit for generating a uniform video signal is mounted on the liquid crystal display device 51; A second method using a signal having a uniform blanking period in a video signal externally input to the display device 51 can be considered.

FIG. 3 is a timing chart for explaining the operation of the liquid crystal display device 51 by the first method for correcting the voltage value. In the first method, the liquid crystal display device 51 includes a signal generation circuit that generates an internal video signal that is a uniform video signal in synchronization with a horizontal synchronization signal Hsync and a vertical synchronization signal (not shown) input to the liquid crystal display device 51. After the power supply of the liquid crystal display device 51 is turned on, a selection signal SL of a high level is output only for a predetermined period W1, and when the predetermined period W1 has elapsed, the selection signal SL is switched from a high level to a low level and output. An output circuit, and a signal selection circuit for selecting and outputting one of an external video signal VS, which is a video signal input from the outside, and an internal video signal generated by the signal generation circuit based on the selection signal SL And are provided. Here, the selection signal output circuit and the signal selection circuit are provided in the control circuit 61 of FIG.

In the liquid crystal display device 51 configured as described above, when the power is turned on at time t1, during the period W1 from time t1 to time t2, the selection signal output circuit selects the high-level selection signal SL from the selection signal output circuit. Output to the circuit. When the high-level selection signal SL is input, the signal selection circuit selects and outputs the internal video signal generated by the signal generation circuit during the period W1, and from the outside after time t2 when the period W1 has elapsed. Selects and outputs an input external video signal.

When one of the internal video signal and the external video signal VS is selected and output as described above, the data signal RGB input to the sample-and-hold circuit 53 as shown in FIG. In W1, the signal becomes a uniform signal corresponding to the internal video signal, and in the period after the period W1, the signal becomes a signal corresponding to the external video signal VS. Thus, in the period W1, a uniform drive signal is supplied to each buffer B.

The correction of the voltage value is performed by inputting a clock signal to the latch circuit R via the signal line 54 at the timing of the period W2 in one horizontal scanning period W2 immediately before the time t2.

The period W1 during which the selection signal SL is kept at a high level is set to a sufficient length until the influence of overshoot in which the voltage fluctuates when the power is turned on is eliminated.

In the first method, since the voltage value is corrected by using the uniform internal video signal generated by the signal generation circuit provided in the liquid crystal display device 51, the voltage value is reliably corrected at a desired timing. Can be corrected.

FIG. 4 is a timing chart for explaining the operation of the liquid crystal display device 51 according to the second method for correcting the voltage value. In the second method, a signal having a uniform blanking period included in the video signal VS input from the outside is used for correcting the voltage value.

In the second method, after the power supply is turned on, the control circuit 61 provided in the liquid crystal display device 51 stabilizes the externally input video signal VS. Blanking period W4
Is detected, and the blanking period W4 is set to the field period W
5 during one horizontal scanning period W3 immediately before the horizontal synchronizing signal H
A clock signal is output to each latch circuit R in synchronization with sync. Here, a uniform signal is inserted into the video signal VS, which is a grayscale signal, during a blanking period between field periods, which are display periods, for example, as shown in FIG. Synchronization signal Vsy
blanking period W4 near the input of the nc pulse
Is a uniform signal.

In the second method, since a signal having a uniform blanking period of the video signal VS input from the outside is used for correcting the voltage value, a signal generating circuit for generating a uniform video signal is used. Since the above is not necessary, the correction of the voltage value can be realized at low cost.

Therefore, in the liquid crystal display device 51, the source bus wiring 20, which has been subjected to the disconnection correction and has a higher impedance than the other source bus wirings 20, 21.
The voltage value of the signal voltage applied to 21 can be corrected to a predetermined value. As a result, the portion corresponding to the source bus lines 20 and 21 having high impedance corresponds to the other source bus lines 20 and 21. For example, it is possible to prevent an image from being displayed brighter than in a portion where the image is displayed, and it is possible to improve the image quality of the liquid crystal display device 51.

Further, in the related art, when a portion corresponding to a source bus line having a high impedance due to a wire break correction is displayed more visually than a portion corresponding to another source bus line, for example, it is displayed brighter. In such a case, the liquid crystal display device has been disposed of. However, in the present embodiment, the voltage value of the signal voltage applied to the source bus lines 20 and 21 having a high impedance is corrected. Thus, the liquid crystal display device which has been disposed can be made a usable non-defective product. As a result, the yield of the liquid crystal display device can be improved and the manufacturing cost can be reduced.

In this embodiment, the source bus wiring 2
0, 21 are provided with spare wirings 23, 24, and drive circuit 1 connected to source bus wirings 20, 21 respectively.
Although the voltage correction unit 52 is provided in each of the gate bus lines 22 and 17, a spare line for correcting the disconnection of the gate bus line 22 is provided so as to intersect with the gate bus line 22. A voltage correction unit similar to the voltage correction unit 52 of the above-described embodiment is provided in the connected driving circuit,
The drive control signal voltage applied to the gate bus wiring 22 may be corrected.

Further, in this embodiment, the voltage value of the signal voltage applied to the source bus lines 20 and 21 having a high impedance due to the correction of the disconnection is corrected. The voltage value of the signal voltage applied to the bus wiring having a high impedance due to variation in the voltage may be corrected.

[0057]

As described above, according to the present invention, the detection means causes the voltage between adjacent signal lines to be higher because the impedance of one adjacent signal line is higher than the impedance of the other signal line. Then, it is detected that the signal voltage is larger than a predetermined threshold value, whereby the voltage value of the signal voltage applied to the signal line having a higher impedance than other signal lines can be corrected to a predetermined value. As a result, when an image is displayed on the liquid crystal display device, a portion corresponding to a signal line having high impedance due to the above-described disconnection correction or variation in a manufacturing process is compared with a portion corresponding to another signal line. For example, a bright image can be prevented from being displayed, and the image quality of the liquid crystal display device can be improved. This is the same for the control signal line.

Also, since the voltage value of the signal voltage is corrected in accordance with the impedance of the signal line to improve the image quality, the liquid crystal display device, which was conventionally discarded due to poor image quality, is corrected by the voltage value of the signal voltage. By doing so, a non-defective product can be obtained, and as a result, the yield of the liquid crystal display device can be improved, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a voltage correction unit 52 provided in drive circuits 16 and 17 of a liquid crystal display device 51 according to one embodiment of the present invention.

FIG. 2 is a plan view showing a configuration of the liquid crystal display device 51.

FIG. 3 is a timing chart for explaining an operation of the liquid crystal display device 51 according to a first method for correcting a voltage value.

FIG. 4 is a timing chart for explaining an operation of the liquid crystal display device 51 according to a second method for correcting a voltage value.

FIG. 5 is a diagram showing an example of correction of disconnection of source bus lines 1a and 1b by spare lines 3a and 3b in the prior art.

[Explanation of symbols]

 16, 17 Drive circuit 18, 19 Resin film 20, 21 Source bus wiring 22 Gate bus wiring 23, 24 Spare wiring 25, 26 Leader wire 28 Disconnection 51 Liquid crystal display device 52 Voltage corrector B Buffer C Comparator R Latch circuit SW switch

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-180564 (JP, A) JP-A-5-150751 (JP, A) JP-A-2-170123 (JP, A) JP-A-2- 89028 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-535 G02F 1/133 545-580

Claims (5)

(57) [Claims] 1. A liquid crystal display panel comprising: (a1) a first substrate, wherein a plurality of signal lines 20 and 21 are arranged in parallel on the first substrate; , A plurality of control signal lines 22 intersect to form intersections, and each of the intersections has a pixel electrode and a signal forming an intersection with the control signal lines in response to a drive control signal from the drive signal lines. (A2) a second substrate provided with a counter electrode facing the entire surface of the first substrate, and (a3) a first substrate provided with a drive element for connecting and disconnecting the line to the pixel electrode. A liquid crystal display panel including a liquid crystal layer interposed between the second substrates; (b) scanning and applying a signal voltage to a signal line;
In a liquid crystal display device provided with drive circuits 16 and 17 for applying a drive control signal to a control signal line in synchronization with a signal voltage and driving picture elements, (c) the voltage between adjacent signal lines is Detecting means for detecting that the impedance of one of the signal lines is higher than a predetermined threshold value due to being higher than the impedance of the other signal line; and (d) responding to the output of the detecting means. A liquid crystal display device comprising: voltage correction means for correcting a voltage value of a signal voltage applied to a signal line. 2. The liquid crystal display panel is provided with a spare wiring which intersects at least a part of the plurality of signal lines via an insulating film at both ends of each signal line, and is drawn out of the liquid crystal display panel. 2. An end of the spare line thus formed is connectable to each other, the spare line is connected to a signal line having a disconnection, and a signal voltage is applied via the spare line. Liquid crystal display device. 3. A signal generating means for generating a uniform internal video signal for at least one horizontal scanning period, and outputting a control signal based on the internal video signal to the driving circuit for a predetermined period, and for a period other than the predetermined period Control means for outputting a control signal based on an external video signal input from the outside to the drive circuit, and instructing the voltage correction means to correct a voltage value in the predetermined period. Item 3. The liquid crystal display device according to item 1 or 2. 4. A control signal is output to the drive circuit based on a video signal input from the outside, and a uniform level of a control signal is output during a blanking period between field periods of the input video signal. 3. The liquid crystal display device according to claim 1, further comprising control means for instructing the voltage correction means to correct a voltage value at a timing at which a signal is input. 5. A liquid crystal display panel comprising: (a1) a first substrate, in which a plurality of signal lines 20, 21 are arranged in parallel; , A plurality of control signal lines 22 intersect to form intersections, and each of the intersections has a pixel electrode and a signal forming an intersection with the control signal lines in response to a drive control signal from the drive signal lines. (A2) a second substrate provided with a counter electrode facing the entire surface of the first substrate, and (a3) a first substrate provided with a drive element for connecting and disconnecting the line to the pixel electrode. A liquid crystal display panel including a liquid crystal layer interposed between the second substrates; (b) scanning and applying a signal voltage to a signal line;
In a liquid crystal display device including drive circuits 16 and 17 for applying a drive control signal to a control signal line in synchronization with a signal voltage to drive picture elements, (c) the voltage between adjacent control signal lines is Detecting means for detecting that the impedance of one adjacent control signal line is higher than a predetermined threshold value due to the higher impedance of the other control signal line; and (d) detecting the output of the detecting means. A liquid crystal display device comprising: a voltage correcting means for correcting a voltage value of a drive control signal voltage applied to the control signal line in response.