JPH07333577A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To realize a liquid crystal display device with high reliability by preventing the application of a DC voltage to a liquid crystal panel for an electrical indefinite period of immediately after power source is applied. CONSTITUTION:This device is provided with a scan drive circuit 2 provided with a control terminal making the whole output terminals an off voltage and a control circuit 2 provided with the control circuit 1 making the control terminal an off state for a period until the number of prescribed vertical synchronizing signals are inputted after power source is applied, and the display of the liquid crystal display panel 4 is stopped for the period until the number of prescribed vertical synchronizing signals are inputted after power source is applied. Thus, the application of the DC voltage linked with the deterioration in display performance is prevented, and the liquid crystal display device with high reliability is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device which is useful as a display for video equipment such as a television and information equipment such as a computer.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional liquid crystal display device using an active matrix liquid crystal display panel. In FIG. 3, 31 is a control circuit for generating a timing signal corresponding to a synchronization signal, 32 is a scanning drive circuit connected to a gate line 35 of the liquid crystal display panel 34, and 33 is connected to a source line 36 of the liquid crystal display panel 34. The signal drive circuit 37 is a switching element provided for each pixel, and is connected to the gate line 35, the source line 36, and the pixel electrode 38. Reference numeral 39 denotes a common electrode, and the voltage applied between this electrode and the pixel electrode 38 changes the optical transmittance of the liquid crystal display panel, thereby enabling display.

The operation of the conventional liquid crystal display device having the above structure will be described below. FIG. 4 is a timing chart showing the operation of the conventional liquid crystal display device. VDD and VSS are power supply voltages, VS is a vertical synchronizing signal, CLK is a clock signal, and HS is
Is a horizontal synchronizing signal, DATA is a display signal, SV, CPV
Is a vertical start signal and a vertical clock signal generated by the control circuit 31. The gate voltage is the output voltage of the scan drive circuit 32 applied to the gate line 35.

In FIG. 4, first, the power supplies VDD and VS.
S is applied, and after a while, the clock signal CLK, the synchronization signals HS and VS, and the display signal DATA are input. On the other hand, the internal states of the scan drive circuit and the signal drive circuit are indefinite immediately after power is applied, and the states are not fixed until various control signals are input. The control signal to be input to the drive circuit is output from the control circuit 31, but the control circuit 31 does not generate the control signal until the synchronizing signal and the clock signal are input from the outside. Therefore, until the control signals CPV and SV in FIG. 4 are output from the control circuit 31, the drive circuit is in an indefinite state, and as a result, the DC component is applied to the liquid crystal display panel. That is, the liquid crystal display panel is normally driven by alternating current, and applying direct current for a long time leads to deterioration of the liquid crystal display panel.

[0005]

As described above, in the conventional liquid crystal display device, an indefinite voltage is applied to the liquid crystal display panel immediately after the power is turned on. A short one may take a few milliseconds, and a long one may take a few hundred milliseconds to a few seconds. Therefore, when a DC voltage is applied to the liquid crystal display panel during the irregular period, the liquid crystal display panel is deteriorated, and the display quality and reliability of the liquid crystal display panel are deteriorated.

The present invention solves such a problem, minimizes the application of a DC voltage to the liquid crystal display panel immediately after power-on, prevents deterioration of the liquid crystal display panel, and provides a highly reliable liquid crystal display device. It is intended to be provided.

[0007]

According to the present invention, there is provided a liquid crystal display panel comprising a scan drive circuit for applying a predetermined voltage to a scan electrode and a signal electrode and a signal drive circuit, and the scan drive circuit for the liquid crystal panel. A control circuit is provided which is connected to the signal drive circuit and outputs a predetermined timing signal to the scan drive circuit and the signal drive circuit by inputting a synchronizing signal, and the control circuit is provided after power is turned on. A signal for stopping the display of the liquid crystal display panel is output until the synchronization signal is input.

Further, during the period from the power-on until a predetermined number of sync pulses of the vertical sync signal are input, all scan drive circuits output an off voltage at which all the switching elements of the active matrix liquid crystal display panel are cut off. The control circuit is configured to input a predetermined control signal as described above to the scan drive circuit.

[0009]

According to the present invention, the control circuit can output the signal for stopping the display of the liquid crystal panel during the period from the power is turned on to the input of the synchronizing signal.
The display is disclosed after the normal timing signal is output to the liquid crystal panel, the direct current voltage is not applied to the liquid crystal panel, and the reliability and display quality of the liquid crystal display device can be prevented from being degraded.

More specifically, an active matrix liquid crystal display panel is used, and all the output voltages of the scan drive circuit are turned off until the synchronizing pulse of the vertical synchronizing signal is input at least once. The control signal is output from the control circuit. Also, the scan drive circuit
The configuration described above can be easily realized by using the one provided with the control terminal for forcibly turning off all the output voltages.

[0011]

1 is a block diagram showing the configuration of a liquid crystal display device according to an embodiment of the present invention. In FIG. 1, 1 is a control circuit for generating a control signal from a vertical synchronizing signal VS, a horizontal synchronizing signal HS and a clock signal CLK, 2 is a scanning drive circuit for driving a gate line 5 of a liquid crystal panel 4, and 3 is a liquid crystal panel 4. A signal drive circuit for driving the source line 6, 7 is a thin film transistor (TFT) as a switching element connected to the gate line 5, the source line 6 and the pixel electrode 8, and 9 is a common electrode facing the pixel electrode. Liquid crystal is sandwiched between the common electrodes.

The operation of the liquid crystal display device of this embodiment having the above structure will be described below. In FIG. 1, the signal drive circuit 3 transfers the display signal DATA in synchronization with the horizontal clock signal CPH by the input of the horizontal start signal SH, and outputs the voltage to the source line 6 in synchronization with the scan drive circuit 2. The scanning drive circuit 2 starts scanning by the input of the vertical start signal SV and sequentially selects the gate lines 5 one by one in synchronization with the vertical clock signal CPV. The TFT 7 connected to the selected gate line becomes conductive, and the voltage of the source line output from the signal drive circuit 3 is written in the pixel electrode 8. The enable signal EN input to the scan driving circuit 2 is a signal for controlling the operation of the scan driving circuit 2, and all the output terminals of the scan driving circuit 2 can be forcibly turned off by the enable signal EN. Scan drive circuit 2
When all the output terminals of the liquid crystal display device are turned off, the TFTs 7 are all cut off, and voltage writing to all pixel electrodes of the liquid crystal display panel 4 is prohibited.

FIG. 2 is an operation timing chart of the liquid crystal display device of the present invention. In FIG. 2, VDD and VSS are power supply voltages, VS is a vertical synchronizing signal, CLK is a clock signal, and HS.
Is a horizontal synchronizing signal, DATA is a display signal, SV, CPV
Is a vertical start signal and a vertical clock signal generated by the control circuit 1. The gate voltage is the output voltage of the scan drive circuit 2 applied to the gate line 5.

In FIG. 2, power supplies VDD and VSS are first shown.
Is applied, and after a while, the clock signal CLK, the synchronization signals HS and VS, and the display signal DATA are input.
On the other hand, the internal states of the scan drive circuit 2 and the signal drive circuit 3 are indefinite immediately after power is applied, and the states are not fixed until various control signals are input. However, the enable signal EN of the control circuit 1 is the power supply VDD to the control circuit 1.
The output voltage of the scan drive circuit 2 is at a low level immediately after the input of, and all the output terminals of the scan drive circuit 2 are turned off. Therefore, the TFT 7 is in the cutoff state for a while immediately after the power is turned on,
No voltage writing to the pixel electrode 8 occurs. for that reason,
The liquid crystal display panel 4 is in a non-display state in which no voltage is applied.

On the other hand, when the synchronizing signals HS.VS, the clock signal CLK and the display signal DATA are input from the outside and the vertical synchronizing signal VS is input twice, the enable signal EN becomes high level and the scan driving circuit 2 Then, the all output off state is released, and the scanning is started from this point. When the vertical start signal SV is input, an on-gate voltage is output at the start of scanning, and the scanning is sequentially performed in synchronization with the vertical clock signal CPV, so that normal display can be performed.

In this embodiment, the vertical synchronizing signal VS
The output of the scan drive circuit 2 is all off-voltage until is input twice, but the present invention is not limited to this, and may be until the first VS input or three times or more.

Further, the gate voltage waveform is just an example, and the off-voltage waveform may be a voltage that changes in the horizontal synchronization cycle. Further, the power supply voltage is positive power supply VDD and negative power supply VS.
Although the S power source has a dual power source configuration, it may have a single power source or three or more types of power sources.

The signals input to the control circuit 1 are the horizontal synchronizing signal HS, the vertical synchronizing signal VS, and the clock signal CLK. In addition to this, a control signal such as a display position signal may be input. A signal may be generated inside the control circuit 1 without being input from the outside. Further, although the display signal DATA is directly input to the signal drive circuit 3, it may be configured so that it is taken into the control circuit 1 once, subjected to predetermined processing, and then transferred to the signal drive circuit 3 if necessary. Needless to say.

[0019]

As described above, according to the present invention,
The voltage is not written to the liquid crystal display panel during the period immediately after the power is turned on until a predetermined synchronization signal is input, so that an unnecessary DC voltage is not applied and the image quality of the liquid crystal display panel is deteriorated. It is possible to realize a highly reliable liquid crystal display device which has no deterioration in life.

Further, since the voltage is not applied to the liquid crystal display panel during the period from the power-on to the input of the synchronizing signal or the display signal, the time constraint of this period is relaxed, and the system using this liquid crystal display device is relaxed. The derived effect of facilitating design can also be obtained, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the liquid crystal display device of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional liquid crystal display device.

FIG. 4 is an operation timing chart of a conventional liquid crystal display device.

[Explanation of symbols]

 1 control circuit 2 scanning drive circuit 3 signal drive circuit 4 liquid crystal display panel 5 gate line 6 source line 7 TFT 8 pixel electrode 9 common electrode

Claims (3)

[Claims] 1. A liquid crystal display panel comprising a scan drive circuit for applying a predetermined voltage to a scan electrode and a signal electrode and a signal drive circuit, and a synchronizing signal connected to the scan drive circuit and the signal drive circuit of the liquid crystal panel. And a control circuit that outputs a predetermined timing signal to the scanning drive circuit and the signal drive circuit by inputting
A liquid crystal display device, which is configured to output a signal for stopping display on the liquid crystal display panel during a period from power-on to input of the synchronization signal. 2. An active matrix liquid crystal display panel using an active matrix liquid crystal display panel having a switching element in each pixel, and the control circuit, during the period from power-on until a predetermined number of vertical synchronizing signal synchronizing pulses are input. 2. The liquid crystal display according to claim 1, wherein a predetermined control signal output from all scan drive circuits is input to the scan drive circuits as an off-voltage for turning off all switching elements of the panel. apparatus. 3. The liquid crystal display device according to claim 2, wherein the scan drive circuit includes a control terminal for forcibly turning off all output voltages of the scan drive circuit.