JP2009271392A - Display device, driving circuit for display device, driving method for display device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for preventing unnecessary image disturbance, defect, etc., from being displayed when a power is turned on or turned off. <P>SOLUTION: The display device 1 includes: a driving element which drives for each pixel in a display area 10 according to a video signal; and a control circuit 11 which applies a signal for stopping the operation of the driving element for a period of time from an instruction to turn on a power for the display area 10 to the input of the video signal. Upon an instruction to turn off the power for the display area 10, the control circuit 11 applies a signal for stopping the operation of the driving element. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device that drives each pixel in a display area with a drive element, a display device drive circuit, a display device drive method, and an electronic apparatus.

  In a display device including an active matrix driving substrate, a gate wiring and a signal wiring form a matrix on a support substrate, and a pixel transistor (TFT: Thin Film Transistor) is formed at the intersection. The gate of the TFT is connected to the gate wiring, the source of the TFT is connected to the signal wiring, and the drain of the TFT is connected to the pixel electrode. In such a TFT, when the gate wiring is at the on potential, the pixel electrode charges the signal wiring potential.

  Generally, in a power supply / input signal sequence of a display device, a power supply system voltage is first input, and then a logic signal and a video signal are input, thereby starting a predetermined display operation. Since the logic circuit is indefinite when the power supply system voltage is input, image disturbance or a defect is displayed on the screen.

  For this reason, image disturbance and defects are prevented from being displayed by controlling the power supply sequence and signal input timing of the display device by various methods. For example, Patent Document 1 discloses a liquid crystal display device and method for providing a full black display by providing a mask period when the power is turned ON / OFF. Patent Document 2 discloses a semiconductor integrated circuit that detects an output of a power supply system and uses a level hold circuit to prevent an unnecessary display when the power is turned on / off.

  In addition, in a liquid crystal display device, there is a problem that when a DC (direct current) voltage is applied to the pixel cell, the display is burned in. Therefore, when the power supply system voltage is input and the logic circuit is indefinite, the power is turned on. There are some methods in which the DC applied to the pixel cell is removed by setting the counter electrode and the signal wiring to the same potential when OFF.

Japanese Patent Laid-Open No. 11-2125224 JP-A-6-19412

  As described above, there is a technique for making the defect invisible depending on the control device and control method of the display device by the external drive circuit, but the power supply sequence and control circuit are not installed depending on the product, and the power is turned on / off. There is a problem that the image disorder or defect at the time is displayed.

  An object of the present invention is to provide a technique that does not display unnecessary image disturbances, defects, etc. when power is turned on or stopped.

  The present invention provides a drive element that drives each pixel in the display area in accordance with a video signal, and a control that gives a signal for stopping the operation of the drive element from the power-on instruction to the display area to the input of the video signal A display device.

  In the present invention, since the operation of the drive element is stopped during the period from the power-on instruction to the display area to the input of the video signal, the drive element does not perform an unnecessary operation during this period.

  Here, the period during which the operation of the drive element is stopped when the power-on instruction is given may be the entire period from the power-on instruction to the input of the video signal or a part of the period. In other words, it is only necessary to prevent the operation of the driving element from becoming unstable until the video signal is input after the power-on instruction is given, thereby preventing the video from being disturbed.

  In the present invention, the control unit gives a signal for stopping the operation of the drive element when a power supply stop instruction is given to the display area. In the present invention, since the operation of the drive element is stopped when the power supply stop instruction is given to the display area, the drive element does not perform an unnecessary operation after the power supply stop instruction.

  In addition, the present invention stops the operation of the drive element that drives each pixel between the power supply to the display area, the video signal to each pixel of the display area, and the input of the power to the display area until the video signal is input. And a display device driving circuit for supplying a signal for causing the display device to display.

  In the present invention, since the control of stopping the operation of the drive element is performed from the power-on instruction to the display area to the input of the video signal, the drive element does not perform an unnecessary operation during this period.

  The present invention is also a drive circuit that provides a signal for stopping the operation of the drive element when a power supply stop instruction is given to the display area. In the present invention, since the control for stopping the operation of the drive element is performed at the stage when the power supply stop instruction is given to the display area, the drive element does not perform an unnecessary operation after the power supply stop instruction.

  Further, the present invention provides a signal for stopping the operation of the drive element between the power-on instruction to the display area and the input of the video signal when the drive element drives each pixel in the display area according to the video signal. Is a driving method of a display device that provides

  In the present invention, since the control of stopping the operation of the drive element is performed from the power-on instruction to the display area to the input of the video signal, the drive element does not perform an unnecessary operation during this period.

  The present invention is also a driving method for giving a signal for stopping the operation of the driving element when a power supply stop instruction is given to the display area. In the present invention, since the control for stopping the operation of the drive element is performed at the stage when the power supply stop instruction is given to the display area, the drive element does not perform an unnecessary operation after the power supply stop instruction.

  The present invention is also an electronic device in which the display device is attached to a main body casing. As a result, the drive element does not perform an unnecessary operation after a power-on instruction or a power-stop instruction is given to the display area.

  According to the present invention, since the drive element does not perform an unnecessary operation when the power is turned on or stopped, it is possible to prevent display of unnecessary image disturbances and defects.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Display device and drive circuit>
FIG. 1 is a schematic diagram illustrating a display device and a drive circuit according to this embodiment. The display device 1 according to the present embodiment includes a drive element that drives each pixel in the display area 10 according to a video signal. For example, a TFT (Thin Film Transistor) is used as the drive element. Yes. Examples of the drive target by the drive element include a liquid crystal and an organic EL (Electro-Luminescence) film.

  In the display area 10 of the display device 1, driving elements such as TFTs are provided in a matrix corresponding to each pixel. Each drive element is controlled by a video signal and a timing signal sent from the drive circuit 2, and performs driving according to the video signal for each pixel.

  The display device 1 according to the present embodiment is characterized in that unnecessary image disturbance, defect, and the like are not displayed when power is turned on (power is turned on) or power is turned off (power is turned off). is there.

  In order to obtain such a feature, the present embodiment includes a control circuit 11 that gives a signal for stopping the operation of the drive element from the power-on instruction to the display area 10 until the input of the video signal. Specifically, a control circuit 11 that controls, for example, the gate voltage of the TFT to an OFF potential by using a predetermined signal is provided in the display device 1.

  Here, the period during which the TFT gate voltage is turned off at the stage when the power-on instruction is given may be the whole period from the power-on instruction to the input of the video signal or a part of the period. That is, it is only necessary to prevent the operation of the TFT from becoming unstable until the video signal is input after the power-on instruction is given, thereby preventing the video from being disturbed.

  FIG. 2 is a diagram illustrating an example of a pixel circuit of a display device when a driving target is a liquid crystal.

  As shown in this figure, in the active matrix display device 1, a plurality of scanning lines 3 and a plurality of signal lines 5 are wired vertically and horizontally in the display region 10 set on the drive substrate 10a side. It is configured as a pixel array portion in which one pixel is provided corresponding to each intersection. A pixel circuit provided in each pixel includes, for example, a pixel electrode 17, a thin film transistor Tr that is a TFT, and a storage capacitor Cs.

  On the other hand, a scanning line driving circuit 7 that scans and drives the scanning line 3 and a signal line driving circuit 9 that supplies a video signal (that is, an input signal) corresponding to luminance information to the signal line 5 are arranged in the peripheral region 12. ing.

  In the panel configuration of the display device 1 as described above, the video signal written from the signal line 5 through the thin film transistor Tr is held in the holding capacitor Cs by driving by the scanning line driving circuit 7, and the held signal amount is obtained. A corresponding voltage is supplied to the pixel electrode 17. On the other hand, a common potential (a counter electrode voltage VCOM) is applied to the counter electrode as a common electrode connected to the other electrode of the storage capacitor Cs. As a result, the liquid crystal molecules constituting the liquid crystal layer change the direction at a predetermined angle within the substrate surface in accordance with the electric field generated by the voltage applied between the pixel electrode 17 and the counter electrode, and transmit light of the display light. Is controlled.

  Note that the configuration of the pixel circuit described above is merely an example, and if necessary, a capacitor element may be provided in the pixel circuit, or a plurality of transistors may be provided to configure the pixel circuit. In addition, a necessary drive circuit is added to the peripheral region 10b according to the change of the pixel circuit.

  The drive circuit 2 of this embodiment shown in FIG. 1 supplies various control signals to the display device 1 and the display device 1 having a circuit configuration as shown in FIG. The drive circuit 2 includes, for example, a video signal, a timing signal, a logic power supply, a signal generation circuit 21 that generates a counter electrode potential, and a gate voltage generation circuit 22 that generates a gate voltage for driving a TFT that is a drive element of the display device 1. I have. Note that the gate voltage for driving the TFT may be output from the signal generation circuit 21.

  The drive circuit 2 sends one of timing signals sent to the display device 1 to the control circuit 11 of the display device 1. This is used as a signal for controlling the operation of the drive element (TFT) by the control circuit 11. As a signal for driving element control sent from the driving circuit 2 to the control circuit 11, for example, a logic enable signal can be cited.

  In addition to the case where the drive circuit 2 is configured by one package or one integrated circuit, the gate voltage generation circuit 21 or the signal generation circuit 22 may be configured on the substrate. Moreover, it may be incorporated in the housing | casing which attaches the display apparatus 1.

<Driving method of display device>
Here, a general power supply sequence in the display device will be described with reference to the timing chart of FIG. 3, VDD is the power supply voltage of the analog unit, VCC is the power supply voltage of the logic unit, VCOM is the counter electrode voltage, SIG is the video signal, Vsc is the center voltage of the video signal, and the logic drive period is the valid period of the logic signal A change in the gate power supply voltage Vg of the driving element (TFT) according to the timing of each signal is shown as a signal change in the panel.

  First, the sequence at power-on will be described. First, an instruction to turn on the power (VCC and VDD) for the display area is received. At this time, the counter electrode potential VCOM is set to 0V. The logic signal is Low, and the video signal SIG is the signal center voltage Vsc.

  After the power supply is stabilized, the counter electrode potential VCOM rises to a predetermined potential while the logic signal is in a low state. Thereafter, the logic signal and the video signal SIG are input. This completes the power-on sequence, and the normal operation is performed thereafter.

  Next, a sequence when the power is stopped will be described. When an instruction to stop the power supply to the display area is received, the video signal SIG is set to the signal center voltage Vsc. Further, the logic signal becomes Low. Then, the counter electrode potential VCOM voltage is lowered to 0V. After the VCOM voltage drops to 0V, the power supplies (VCC and VDD) are dropped to 0V. This is the end of the power stop sequence.

  In such a general power supply sequence, the following problems occur. That is, in the display area, some point defects are generally allowed within a predetermined standard range. When such a point defect exists, the point defect may be displayed as a line defect until the power is turned on and the logic circuit and the video signal are input. This is because the gate power supply voltage (Vg) of the TFT as a driving element is affected by the power supply (VCC and VDD) when the power supply is turned on and off, and the TFT operates unnecessarily.

  In order to solve such a problem, when a power supply voltage is input and the logic circuit is in an indefinite state, DC (direct current voltage) is applied to the pixel cell by setting the counter electrode and the signal wiring to the same potential when the power is turned ON / OFF. The measures such as avoiding it are taken.

  However, among such point defects, regarding the defective part where the power supply and the pixel electrode are shorted, such as a short circuit between the pixel electrode and the gate line (power supply potential) or a short circuit between the pixel electrode and the ground, The following problems arise. That is, depending on the driving sequence at the time of power ON / OFF, the gate is turned on at the time of rising, and the signal line becomes the gate potential or the ground potential through the point defect pixel. As a result, in the case of normally black, the pixel along the signal wiring has a bright line defect, and in the case of normally white, the pixel along the signal wiring has a defective line defect.・ Unnecessary symptoms that are noticeable only when the camera is turned off.

  For example, as in the technique disclosed in Japanese Patent Application Laid-Open No. 2000-347627, there is a technique in which the DC of a pixel is released by a DCG (discharge) signal after the power supply is turned on. However, in this case, the line defect is visually recognized in a short period of time because the signal line becomes the gate potential or the ground potential through the point defect pixel at the timing before the DC of the pixel is removed by the DCG signal. End up.

  In the present embodiment, by controlling the driving voltage of the driving element inside the display device, it is possible to hide the unnecessary defect at the time of power ON / OFF that is visually recognized due to the presence of the above point defect. be able to.

<First Embodiment>
FIG. 4 is a diagram illustrating a circuit configuration example of a control circuit applied to the display device of the first embodiment. In the circuit configuration example of the first embodiment, when a driving voltage (for example, gate power supply voltage Vg) of a driving element such as a TFT is supplied from the power supply voltage VDD, it is turned ON / OFF by a logic enable signal input from the outside of the display device. In this configuration, a control circuit 11 for controlling the display is provided inside the display device.

  The control circuit 11 inputs a logic enable signal to the analog power supply (VDD) buffer 11b through the level shifter 11a, and controls whether or not the gate power supply voltage Vg is supplied by the logic enable signal.

  FIG. 5 is a timing chart illustrating a power supply sequence using the circuit configuration example of the first embodiment. 5, VDD is the power supply voltage of the analog unit, VCC is the power supply voltage of the logic unit, VCOM is the counter electrode voltage, SIG is the video signal, Vsc is the center voltage of the video signal, and the logic enable signal is the start of the logic signal. A signal indicating the end is shown, and a change in the gate power supply voltage Vg of the driving element (TFT) according to the timing of each signal is shown as a signal change in the panel.

  The power supply sequence using the circuit configuration of the first embodiment is basically the same as the sequence shown in FIG. 3 described above, but a logic enable indicating the start and end of a logic signal used for scanning the display device. A new signal is input from the outside.

  First, the sequence at power-on will be described. Turning on the power (VCC and VDD) for the display area accepts the instruction. At this time, the counter electrode potential VCOM is set to 0V. The logic enable signal is Low, and the video signal SIG is the signal center voltage Vsc.

  The logic enable signal is level-shifted to the analog power supply level by the control circuit 11 shown in FIG. 4 and connected to the gate power supply voltage (Vg) of the TFT which is the pixel transistor via the buffer 11b using the analog power supply as a power supply. As a result, the gate voltage becomes OFF potential while the logic enable signal is Low. Therefore, even when the power supply system (VDD, VCC, Vcom) is turned on, the gate voltage level of the pixel transistor is surely set to OFF potential. Will be maintained.

  After the power supply is stabilized, the logic enable signal is in a low state, and the counter electrode potential VCOM is raised to a predetermined potential. Thereafter, the logic enable signal is set to High and the video signal SIG is input. The gate power supply voltage (Vg) of the TFT becomes an ON potential by the logic enable signal High, and thereafter, normal operation is performed.

  Next, a sequence when the power is stopped will be described. When an instruction to stop the power supply to the display area is received, the video signal SIG is set to the signal center voltage Vsc. At the same time, the logic enable signal becomes Low, and the gate power supply voltage (Vg) of the TFT becomes OFF potential. Then, the counter electrode potential VCOM voltage is lowered to 0V. After the VCOM voltage drops to 0V, the power supplies (VCC and VDD) are dropped to 0V. This is the end of the power stop sequence.

  As described above, since the TFT is turned off and no voltage is applied to the pixel during a period in which the video signal is not input when the power is turned on / off, an effect that no image disturbance or defect is displayed when the power is turned on / off can be obtained.

Second Embodiment
FIG. 6 is a diagram illustrating a circuit configuration example of a control circuit applied to the display device of the second embodiment. In the circuit configuration example of the second embodiment, the control circuit 11 is configured by the exclusive OR circuit 11c and the buffer 11b. In this control circuit 11, when a driving voltage (for example, a gate power supply voltage Vg) of a driving element such as a TFT is supplied from the power supply voltage VDD, a logic enable signal input from the outside of the display device 1, a counter electrode voltage VCOM, Is input to the exclusive OR circuit 11c, and ON / OFF is controlled by the output. In the present embodiment, such a control circuit 11 is provided inside the display device 1 so that residual DC is not left in the pixels of the display device 1.

  FIG. 7 is a timing chart illustrating a power supply sequence using the circuit configuration example of the second embodiment. In FIG. 7, VDD is the power supply voltage of the analog unit, VCC is the power supply voltage of the logic unit, VCOM is the counter electrode voltage, SIG is the video signal, Vsc is the center voltage of the video signal, and the logic enable signal is the start of the logic signal. A signal indicating the end is shown, and a change in the gate power supply voltage Vg of the driving element (TFT) according to the timing of each signal is shown as a signal change in the panel.

  The power supply sequence using the circuit configuration of the second embodiment is basically the same as that of the first embodiment shown in FIG. 5 described above, but temporarily when a power supply stop instruction is given to the display area. Is supplied with a signal for stopping the operation of the TFT which is a drive element, and then a signal for turning on the gate of the TFT to discharge the video signal (residual DC) accumulated in the pixel.

  First, the sequence at power-on will be described. Turning on the power (VCC and VDD) for the display area accepts the instruction. At this time, the counter electrode potential VCOM is set to 0V. The logic enable signal is Low, and the video signal SIG is the signal center voltage Vsc.

  This logic enable signal and the counter electrode potential VCOM are input to the exclusive OR circuit 11c of the control circuit 11 shown in FIG. At this time, the counter electrode potential VCOM is level-shifted to the logic signal level. As the common electrode potential VCOM rises, the output from the exclusive OR circuit 11c becomes Low and the gate voltage becomes OFF potential while the logic enable signal is Low. The output of the exclusive OR circuit 11c is level-shifted to the analog power supply level by the level shifter 11b and input to the buffer 11b of the analog power supply (VDD), and the output becomes the gate power supply voltage (Vg) of the TFT which is the drive element. .

  By setting the gate voltage to the OFF potential, the gate voltage level of the pixel transistor is reliably maintained at the OFF potential even when the power supply system (VDD, VCC, Vcom) voltage is turned on.

  After the power supply is stabilized, the logic enable signal is in a low state, and the counter electrode potential VCOM is raised to a predetermined potential. Thereafter, the logic enable signal is set to High and the video signal SIG is input. The gate power supply voltage (Vg) of the TFT becomes an ON potential by the logic enable signal High, and thereafter, normal operation is performed.

  Next, a sequence when the power is stopped will be described. When an instruction to stop the power supply to the display area is received, the video signal SIG is set to the signal center voltage Vsc. At the same time, the logic enable signal becomes Low, the output from the exclusive OR circuit 11c becomes Low, and the gate power supply voltage (Vg) of the TFT becomes the OFF potential.

  At this time, when the counter electrode potential VCOM is Low and the logic enable signal is Low, the gate voltage is ON potential. By setting VCOM and the signal line to the same potential during this period, DC does not remain in the pixel cell. Can be. Here, as an example, a period from the reception of the power supply stop instruction to the start of DC removal is, for example, 8 ms or less, and a DC removal period, for example, about 100 ms is provided. Then, the power supplies (VCC and VDD) are reduced to 0V. This is the end of the power stop sequence.

  Even if the gate voltage of the TFT of the liquid crystal display device is not set to the ON potential during this period, it is necessary to make VCOM and the signal line have the same potential when the residual DC of the pixel cell is removed through the TFT array substrate or the liquid crystal. There is no.

<Third Embodiment>
FIG. 8 is a diagram illustrating a circuit configuration example of a control circuit applied to the display device of the third embodiment. In the circuit configuration example of the third embodiment, when a driving voltage (for example, gate power supply voltage Vg) of a driving element such as a TFT is supplied from the power supply voltage VDD, it is turned ON / OFF by a logic enable signal input from the outside of the display device. In this configuration, a control circuit 11 for controlling the display is provided inside the display device.

  The control circuit 11 inputs a logic enable signal to the analog power supply (VDD) buffer 11b through the level shifter 11a, and controls whether or not the gate power supply voltage Vg is supplied by the logic enable signal.

  FIG. 9 is a timing chart illustrating a power supply sequence using the circuit configuration example of the third embodiment. In FIG. 9, VDD is the power supply voltage of the analog unit, VCC is the power supply voltage of the logic unit, VCOM is the counter electrode voltage, SIG is the video signal, Vsc is the center voltage of the video signal, and the logic enable signal is the start of the logic signal. A signal indicating the end is shown, and a change in the gate power supply voltage Vg of the driving element (TFT) according to the timing of each signal is shown as a signal change in the panel.

  The power supply sequence using the circuit configuration of the third embodiment is basically the same as that of the first embodiment shown in FIG. 5 described above. However, when the instruction to stop the power supply to the display area is given, VCOM The video signal is set to Vsc while maintaining a predetermined period, and after the video signal accumulated in the pixel is discharged, a signal for stopping the gate power supply potential Vg of the driving element (TFT) is given.

  First, the sequence at power-on will be described. Turning on the power (VCC and VDD) for the display area accepts the instruction. At this time, the counter electrode potential VCOM is set to 0V. The logic enable signal is Low, and the video signal SIG is the signal center voltage Vsc.

  The logic enable signal is level-shifted to the analog power supply level by the control circuit 11 shown in FIG. 8, and is connected to the gate power supply voltage (Vg) of the TFT which is the pixel transistor via the buffer 11b using the analog power supply as a power supply. As a result, the gate voltage becomes OFF potential while the logic enable signal is Low. Therefore, even when the power supply system (VDD, VCC, Vcom) is turned on, the gate voltage level of the pixel transistor is surely set to OFF potential. Will be maintained.

  After the power supply is stabilized, the logic enable signal is in a low state, and the counter electrode potential VCOM is raised to a predetermined potential. Thereafter, the logic enable signal is set to High and the video signal SIG is input. The gate power supply voltage (Vg) of the TFT becomes an ON potential by the logic enable signal High, and thereafter, normal operation is performed.

  Next, a sequence when the power is stopped will be described. When an instruction to stop the power supply to the display area is received, the video signal SIG is set to the signal center voltage Vsc. On the other hand, the logic enable signal is kept high for a certain period after receiving the instruction to stop the power supply, and the gate power supply voltage (Vg) of the TFT is kept at the ON potential. Then, within this fixed period, VCOM and the signal line are set to the same potential state, and the residual DC of the pixel cell is removed. As an example of the fixed period, the residual DC can be removed, for example, about several tens of milliseconds. Then, after a certain period, the power supplies (VCC and VDD) are reduced to 0V. This is the end of the power stop sequence.

  Even if the gate voltage of the TFT of the liquid crystal display device is not set to the ON potential in this fixed period, if the residual DC of the pixel cell is removed through the TFT array substrate or the liquid crystal, VCOM and the signal line are set to the same potential. There is no need.

  In each of the embodiments described above, the logic enable signal does not necessarily have to be synchronized with the video signal SIG, and does not have to coincide with other logic signals. It is also possible to substitute a signal input from the outside for other purposes. For example, some liquid crystal display devices are supplied with a signal corresponding to a logic enable signal for the purpose of removing residual DC of the pixel, and this signal may be used instead of the logic enable signal.

  In this way, by controlling the power supply voltage for driving the drive element in accordance with a predetermined input signal, the display / non-display state can be easily controlled inside the display device, and the image is disturbed when the power is turned on / off. It is possible to prevent display of defects and defects.

<Effect of embodiment>
In the present embodiment, the display device 1 has an internal circuit that controls the gate voltage of the pixel transistor, which is a driving element, so as not to display image disturbances or defects when the power is turned ON / OFF. Even if it is done, the same effect can be easily obtained.

  In the present embodiment, the display device 1 is controlled so that the gate voltage of the pixel transistor is controlled to the OFF potential when the power is turned ON / OFF, so that image disturbance or defect at the time of the power ON / OFF is not displayed. Some display devices are not enough.

  In the case where it is necessary to remove the residual DC of the pixel cell as in some liquid crystal display devices, the gate voltage is controlled to the OFF potential when the power is turned on, but when the power is turned off, the control as in the second embodiment is performed. A period for removing the residual DC of the pixel cell can be provided. Thereby, it is possible to display no image disturbance or defect when the power is turned on, and to prevent residual DC from remaining in the pixel cell including the liquid crystal when the power is turned off.

  In this way, in the active matrix display device 1 of the drive element, the image transistor is easily disturbed even when mounted on various products by controlling the gate voltage of the pixel transistor suitable for the application in the display device. It is possible to prevent display of defects and defects.

  In addition, since image disturbances and defects are not displayed with an easy power supply sequence, cost reduction of products using the display device 1 can be expected. Furthermore, since it is possible to prevent an allowable point defect or the like from being visually recognized as a line defect when the power is turned ON / OFF, the yield of the non-defective display device 1 can be improved.

<Application examples to electronic devices>
The display device according to the present embodiment described above includes various electronic devices shown in FIGS. 10 to 14, such as a television, a projection device, a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, a video camera, and the like. The present invention can be applied to display devices of electronic devices in various fields that display video signals input to electronic devices or video signals generated in electronic devices as images or videos. Below, an example of the electronic device to which this embodiment is applied is demonstrated.

  FIG. 10 is a perspective view showing a television to which the present embodiment is applied. The television according to this application example includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like, and is created by using the display device according to this embodiment as the video display screen unit 101.

  FIG. 11 is a perspective view showing a digital camera to which the present embodiment is applied, in which (A) is a perspective view seen from the front side, and (B) is a perspective view seen from the back side. The digital camera according to this application example includes a light emitting unit 111 for flash, a display unit 112, a menu switch 113, a shutter button 114, and the like, and is manufactured by using the display device according to the present embodiment as the display unit 112. .

  FIG. 12 is a perspective view showing a notebook personal computer to which the present embodiment is applied. A notebook personal computer according to this application example includes a main body 121 including a keyboard 122 that is operated when characters or the like are input, a display unit 123 that displays an image, and the like, and the display unit 123 includes a display device according to the present embodiment. It is produced by using.

  FIG. 13 is a perspective view showing a video camera to which the present embodiment is applied. The video camera according to this application example includes a main body 131, a subject shooting lens 132 on a side facing forward, a start / stop switch 133 at the time of shooting, a display unit 134, and the like. It is manufactured by using the display device according to the above.

  FIG. 14 is a view showing a mobile terminal device to which the present embodiment is applied, for example, a mobile phone, in which (A) is a front view in an open state, (B) is a side view thereof, and (C) is closed. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. The mobile phone according to this application example includes an upper housing 141, a lower housing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub display 145, a picture light 146, a camera 147, and the like. In addition, the display device according to this embodiment is used as the sub display 145.

<Display imaging device>
The display device according to the present embodiment is applicable to the following display imaging device. In addition, the display imaging device can be applied to the various electronic devices described above. FIG. 15 illustrates the overall configuration of the display imaging apparatus. The display imaging apparatus includes an I / O display panel 2000, a backlight 1500, a display drive circuit 1200, a light receiving drive circuit 1300, an image processing unit 1400, and an application program execution unit 1100.

  The I / O display panel 2000 is composed of a liquid crystal panel in which a plurality of pixels are arranged in a matrix over the entire surface, and displays an image such as a predetermined figure or character based on display data while performing a line sequential operation ( In addition to having a display function, it also has a function (imaging function) for imaging an object in contact with or close to the I / O display 2000 as will be described later. The backlight 1500 is a light source of the I / O display panel 2000 in which a plurality of light emitting diodes are arranged, for example, and is turned on and off at a high speed at a predetermined timing synchronized with the operation timing of the I / O display 2000. Is supposed to do.

  The display drive circuit 1200 drives the I / O display panel 2000 (drives line-sequential operation) so that an image based on display data is displayed on the I / O display panel 2000 (so as to perform a display operation). Circuit).

  The light receiving drive circuit 1300 is a circuit that drives the I / O display panel 2000 (drives line-sequential operation) so that light reception data can be obtained in the I / O display panel 2000 (so as to image an object). It is. The light reception data at each pixel is accumulated in the frame memory 1300A, for example, in units of frames, and is output to the image processing unit 14 as a captured image.

  The image processing unit 1400 performs predetermined image processing (arithmetic processing) based on the captured image output from the light receiving drive circuit 1300, and information (position coordinate data, object of the object) that is in contact with or close to the I / O display 2000. Data on the shape and size, etc.) are detected and acquired. The details of the detection process will be described later.

  The application program execution unit 1100 executes processing according to predetermined application software based on the detection result of the image processing unit 1400. For example, the display data includes the position coordinates of the detected object, and the I / O What is displayed on the display panel 2000 is mentioned. The display data generated by the application program execution unit 1100 is supplied to the display drive circuit 1200.

  Next, a detailed configuration example of the I / O display panel 2000 will be described with reference to FIG. The I / O display panel 2000 includes a display area (sensor area) 2100, a display H driver 2200, a display V driver 2300, a sensor readout H driver 2500, and a sensor V driver 2400. Yes.

  The display area (sensor area) 2100 is an area that modulates light from the organic electroluminescent element to emit display light and images an object that is in contact with or close to the area, and is an organic light emitting element (display element). Electroluminescent elements and light receiving elements (imaging elements), which will be described later, are arranged in a matrix.

  The display H driver 2200 drives the organic electroluminescence element of each pixel in the display area 2100 together with the display V driver 2300 based on the display drive display signal and the control clock supplied from the display drive circuit 1200. It is.

  The sensor readout H driver 2500 drives the light receiving element of each pixel in the sensor area 2100 together with the sensor V driver 2400 to obtain a light reception signal.

  Next, a connection relationship between each pixel in the display area 2100 and the sensor readout H driver 2500 will be described with reference to FIG. In this display area 2100, a red (R) pixel 3100, a green (G) pixel 3200, and a blue (B) pixel 3300 are arranged side by side.

  The charges accumulated in the capacitors connected to the light receiving sensors 3100c, 3200c, and 3300c of each pixel are amplified by the respective buffer amplifiers 3100f, 3200f, and 3300f, and the signals are output at the timing when the readout switches 3100g, 3200g, and 3300g are turned on. It is supplied to the sensor reading H driver 2500 via the output electrode. Each signal output electrode is connected to a constant current source 4100a, 4100b, 4100c, and a signal corresponding to the amount of received light is detected with high sensitivity by the sensor reading H driver 2500.

It is a schematic diagram explaining the display apparatus and drive circuit which concern on this embodiment. It is a figure which shows an example of the pixel circuit of a display apparatus in case a drive object is a liquid crystal. It is a timing chart explaining the general power supply sequence in a display apparatus. It is a figure explaining the circuit structural example of the control circuit applied to the display apparatus of 1st Embodiment. It is a timing chart explaining the power supply sequence using the circuit structural example of 1st Embodiment. It is a figure explaining the circuit structural example of the control circuit applied to the display apparatus of 2nd Embodiment. It is a timing chart explaining the power supply sequence using the circuit structural example of 2nd Embodiment. It is a figure explaining the circuit structural example of the control circuit applied to the display apparatus of 3rd Embodiment. It is a timing chart explaining the power supply sequence using the circuit structural example of 3rd Embodiment. It is a perspective view which shows the television with which this embodiment is applied. It is a perspective view which shows the digital camera to which this embodiment is applied. It is a perspective view which shows the notebook type personal computer to which this embodiment is applied. It is a perspective view which shows the video camera to which this embodiment is applied. It is a figure which shows the portable terminal device to which this embodiment is applied, for example, a mobile telephone. It is a block diagram showing the structure of a display imaging device. It is a block diagram showing the structural example of an I / O display panel. It is a circuit diagram for demonstrating the connection relation of each pixel and the sensor reading H driver.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 2 ... Drive circuit, 10 ... Display area | region, 11 ... Control circuit, 21 ... Gate voltage generation circuit, 22 ... Signal generation circuit

Claims (12)

A driving element for driving each pixel in the display area according to a video signal;
And a control unit that provides a signal for stopping the operation of the drive element from a power-on instruction to the display area to the input of the video signal. The display device according to claim 1, wherein the control unit gives a signal for stopping the operation of the drive element when a power supply stop instruction is given to the display area. The control unit provides a signal for temporarily stopping the operation of the drive element when a power supply stop instruction is given to the display area, and then turns the drive element to discharge the video signal accumulated in the pixel. The display device according to claim 1, wherein a signal for operating is provided. In order to stop the operation of the driving element that drives each pixel between the power source to the display area, the video signal to each pixel of the display area, and the input of the video signal to the input of the video signal to the display area The display device drive circuit that gives the signal to the display device. The drive circuit of the display device according to claim 4, wherein a signal for stopping the operation of the drive element is given when a power supply stop instruction is given to the display area. A signal for temporarily stopping the operation of the drive element when a power supply stop instruction is given to the display area, and then operating the drive element to discharge the video signal accumulated in the pixel The drive circuit for the display device according to claim 4. When driving according to the video signal to each pixel in the display area by the drive element, a signal for stopping the operation of the drive element is given from the power-on instruction to the display area until the input of the video signal. Device driving method. The method for driving a display device according to claim 7, wherein a signal for stopping the operation of the drive element is given when a power supply stop instruction is given to the display area. A signal for temporarily stopping the operation of the driving element is given at a stage where a power supply stop instruction is given to the display area, and then a signal for operating the driving element to discharge the video signal accumulated in the pixel is given. The display device driving method according to claim 7. Having a display device attached to the main body housing;
The display device
A driving element for driving each pixel in the display area according to a video signal;
An electronic apparatus comprising: a control unit that provides a signal for stopping the operation of the drive element during a period from a power-on instruction to the display area until the video signal is input. The electronic device according to claim 10, wherein the control unit gives a signal for stopping the operation of the drive element when a power supply stop instruction is given to the display area. The control unit provides a signal for temporarily stopping the operation of the drive element when a power supply stop instruction is given to the display area, and then turns the drive element to discharge the video signal accumulated in the pixel. The electronic device according to claim 10, wherein a signal for operating is provided.

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