JP2001282163A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device in which the saving of power consumption as the whole display device is attached by reducing power consumption by stopping clock pulses to be supplied to drivers in a period when display is not performed. SOLUTION: In this display device, a gate driver 50 supplying the gate signal, connected to plural gate signal lines 51 and a drain driver 60 supplying the drain signal, connected to plural drain signal lines 61 are arranged on an insulating substrate 10 and power consumption of the device is reduced by making clock pulses CKH1, CKH2 to be supplied to respective drivers 50, 60 not to be outputted by fixing them at prescribed voltages in a horizontal fly-back period and a vertical fly-back period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display device having a shift register of a drain driver or a gate driver driven by a clock pulse.

[0002]

2. Description of the Related Art In recent years, a display device has a thin film transistor (TFT) in a display area around the display area.
r: Hereinafter, referred to as “TFT”. ) Is provided, and the peripheral drive circuit is provided with a shift register.

FIG. 2 shows an equivalent circuit diagram of a general liquid crystal display device.

[0004] As shown in FIG.
Are formed on the insulating substrate 10 by a plurality of gate signal lines 51 connected to a gate driver 50 for supplying a gate signal and sampling pulses SP1, SP2,..., SPn output from a drain driver 60 for supplying a drain signal. The sampling transistors SP1,
SPn are turned on, and a plurality of drain signal lines 61 to which the data signal of the data signal line 62 is supplied are arranged. In the vicinity of the intersection of the two signal lines 51 and 61, both of the drain signal lines 61 are arranged. TFT 7 connected to signal lines 51 and 61
0 and a display electrode 80 connected to the TFT 70.

A driver scan LSI 91 is provided on an external circuit board 90 separate from the insulating board 10.

A start signal is sent from the driver scan LSI 91 of the external circuit board 90 to the gate driver 50.
And the video signal is input to the data line 62.

The sampling transistor SP is turned on in response to the sampling signal based on the start signal, and the data signal on the data signal line 62 is supplied to the drain signal line 61. Further, a gate signal is input from the gate signal line 51 to the gate electrode 13, and the TFT 70 is turned on. As a result, a drain signal is applied to the display electrode 80 via the TFT 70. At the same time, a drain signal is also applied to the auxiliary capacitor 85 via the TFT 70 to hold the voltage applied to the display electrode 80 for one field period. One electrode 86 of the storage capacitor 85 is connected to the source 11 of the TFT 70.
s, and the other electrode 87 is connected to each display pixel 20.
0 is applied with a common potential Vcom.

When the gate of the TFT 70 is opened and a drain signal is applied to the liquid crystal 21, it must be held for one field period, but the voltage of the signal of the liquid crystal alone gradually decreases over time. Then, it appears as display unevenness, and good display cannot be obtained. Therefore, an auxiliary capacitor 85 is provided to hold the voltage for one field period.

The voltage applied to the display electrode 80 is
, The liquid crystal 21 is oriented according to the voltage to obtain a display.

Incidentally, in order to drive the gate driver 50 and the drain driver 60, a sampling pulse is generated according to a clock signal.

FIG. 3 is a block diagram of a driving circuit for driving a general liquid crystal display device.

As shown in FIG. 1, a timing controller to which a video signal is input and various timing signals from the timing controller, for example, clock pulses CKH1 and CKH2, start pulses STH1 and STH
The shift register is driven based on various level-shifted timing signals, and a liquid crystal display panel displays each pixel with a video signal sampled by the shift register.

Here, generation of a clock pulse will be described.

FIG. 5 is a timing chart showing a conventional clock pulse and its generation period.

As shown in FIG. 1, one supplied video signal comprises a video signal in a display period and a horizontal blanking period in a non-display period. The other clock pulse CKH
1, CKH2 is output throughout the display period and the non-display period of the video signal, and is supplied to each driver.

The start pulses STH1 and STH2 are
The video signal is a pulse for starting sampling, and is a signal whose phase is inverted with respect to each other.

[0017]

As described above, the clock pulse is continuously supplied to each driver during the period when the liquid crystal display device is on.

For this reason, power is consumed even during the period of supplying the clock pulse. Therefore, when the liquid crystal display device is used as a display of a mobile phone, for example, the battery capacity of the mobile phone decreases. There is a drawback that the use time becomes extremely short.

Accordingly, the present invention has been made in view of the above-mentioned conventional disadvantages, and the power consumption is reduced by stopping the clock pulse supplied to the driver during the non-display period, so that the entire display device is saved. It is an object to provide a display device with low power consumption.

[0020]

According to the present invention, there is provided a display device having a shift register of a drain driver or a shift register of a gate driver, wherein a clock pulse for driving the shift register of the drain driver during a non-display period. Is to fix the clock pulse to a predetermined level and stop outputting the clock pulse to the display device.

Further, in the above display device, the non-display period is a non-display period in a horizontal direction.

Further, in the above display device, the non-display period is a horizontal retrace period or a vertical retrace period.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A display device according to the present invention will be described below.

FIG. 1 shows a clock pulse supplied to a driver of a liquid crystal display device, and FIG. 2 shows an equivalent circuit diagram when the display device of the present invention is applied to a liquid crystal display device.

As shown in FIG. 2, the liquid crystal display panel 100
The liquid crystal display panel 100 is driven based on each signal of the external substrate 90 separate from the above.

In the liquid crystal display panel 100, a plurality of gate signal lines 51 connected to a gate driver 50 for supplying a gate signal are arranged in a row direction (horizontal direction) and connected to a drain driver 60 for supplying a drain signal. A plurality of drain signal lines 61 are arranged in the column direction (vertical direction). In the vicinity of the intersection of both signal lines 51 and 61, TF
T70 is arranged. The rise and fall of the liquid crystal 21 are controlled by the voltage applied to the display electrode 80 connected to the TFT 70.

Each driver 5 is provided on an external circuit board 90.
LSI that supplies signals for scanning 0 and 60
91 are provided.

A block diagram of a driving circuit for driving the liquid crystal display device is the same as that shown in FIG.
A timing controller to which a video signal is input, various timing signals from the timing controller,
For example, a level shifter that converts the levels of the clock pulses CKH1 and CKH2 and the start pulses STH1 and STH2, a shift register that is driven based on various level-shifted timing signals, and a video signal that is sampled by the shift register to each display pixel. And a liquid crystal display panel for display.

Here, the clock pulse of the display device of the present invention will be described.

As shown in FIG. 1, the clock pulse CKH
1, CKH2 is a signal whose one cycle is 330 nsec (nanosecond) and has a frequency of about 3 MHz, and whose phases are inverted. The video signal is composed of a video signal period of a display period and a horizontal blanking period of a non-display period.

Here, the clock pulses CKH1, CKH
No. 2 is fixed to a constant potential in the horizontal blanking period of the non-display period in the video signal. That is, when the clock pulses CKH1 and CKH2 have a low level of 0V and a high level of 3V, for example, one of the clock pulses CKH1 is set to 0 during the non-display period.
V, and the other clock pulse CKH2 is fixed at 3V. By doing so, a clock pulse is not generated during the non-display period, and no clock pulse is supplied to each driver. That is, in the block diagram of FIG. 3, since the output of the clock pulse from the timing controller is not performed, the clock pulse is not supplied to the level shifter, the shift register, and the liquid crystal display device. Therefore, since the level shifter and the shift register are not driven, power consumption can be reduced.

Since one horizontal scanning period (1H) is about 63 μS (microseconds) and a horizontal blanking period is about 9 μS, about 14.3% of 1H can eliminate the clock pulse oscillation. Thus, approximately 14% of the power consumed by the clock pulse can be saved. <Second Embodiment> In the above-described first embodiment, the case where the supply of the clock pulse to each driver during the horizontal retrace period is stopped has been described. Indicates that the supply of the clock pulse to each driver is stopped during the vertical flyback period.

FIG. 4 shows clock pulses supplied to the driver of the liquid crystal display device.

FIG. 3A shows a conventional oscillation state of a clock pulse, and FIG. 3B shows a state in which the clock pulse of the present invention is fixed at a constant potential during the vertical retrace period and is not output. .

As shown in the figure, the video signal is composed of a video signal period which is a display period, and a horizontal retrace period and a vertical retrace period which are non-display periods.

The clock pulse signals CKH1, CK
H2 has a frequency of about 3 MHz, as in the first embodiment.
And the phases of the clock pulses CKH1 and CKH2 are opposite to each other.

As shown in FIG. 4B, in the vertical blanking period, 42 out of 262 scanning lines in one screen are other than the effective display, so that 42 lines / 262 lines (= 16%)
Power consumption of the clock pulse can be saved. That is, as shown in FIG. 4A, the power consumption of the clock pulse is reduced by about 16% compared to the case where the clock pulse is oscillated during the horizontal and vertical blanking periods.

Further, in both the retrace period of the horizontal retrace period and the vertical retrace period, the power consumption for the fixed period can be saved by fixing the clock pulse to a predetermined potential so as not to oscillate. Therefore, by using the display device of the present invention for a display device having a limited power supply (battery) such as a mobile phone, the battery can be used effectively, and long-time use is possible.

As described above, according to the present invention, the clock pulse is fixed at a constant potential in the horizontal and vertical blanking periods, so that the power consumption can be reduced without outputting to a display device, for example, a liquid crystal display panel. it can.

Since the drain driver requires a higher frequency than the gate driver, it is necessary to stop the output by fixing the clock pulse supplied to the drain driver, particularly the shift register of the drain driver, to a predetermined potential. Thereby, power consumption can be further reduced.

In each of the above-described embodiments, the case where the non-display period is a horizontal or vertical blanking period has been described. However, the present invention is not limited to this. , A non-display period in which display is not substantially performed in the drain direction, and a non-display period in which display is not substantially performed in the gate direction.

[0042]

According to the display device of the present invention, the clock pulse is fixed to a constant potential during the horizontal or vertical retrace period and is not supplied to the driver, so that a display device with reduced power consumption can be obtained. .

[Brief description of the drawings]

FIG. 1 is a clock pulse showing a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a general liquid crystal display device.

FIG. 3 is a block diagram of the liquid crystal display device of the present invention.

FIG. 4 is a clock pulse showing a second embodiment of the present invention.

FIG. 5 shows a conventional clock pulse.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 insulating substrate 13 gate 21 liquid crystal 50 gate driver 51 gate signal line 60 drain driver 61 drain signal line 70 TFT 80 display electrode 91 external LSI 100 liquid crystal display panel 200 display pixel

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA31 NA41 NC07 NC22 ND39 5C006 AF69 AF73 BB16 BF03 FA47 5C080 AA10 BB05 DD26 FF11 JJ02 JJ04

Claims (3)

[Claims] In a display device including a shift register of a drain driver or a shift register of a gate driver, a clock pulse for driving the shift register of the drain driver is fixed to a predetermined level during a non-display period, and A display device, which stops outputting pulses to the display device. 2. The display device according to claim 1, wherein the non-display period is a horizontal non-display period. 3. The display device according to claim 1, wherein the non-display period is a horizontal retrace period or a vertical retrace period.