KR100807586B1 - A driving circuit of liquid crystal display device having buffer - Google Patents

Abstract

In the driving circuit of the liquid crystal display according to the present invention, a buffer unit is provided at the front end of the control unit, and when the vertical synchronizing signal is not input, the irregular internal oscillation vertical synchronizing signal generated by the control unit is grounded by the enable signal, which is data when unstable power is supplied. This is to prevent the gate start signal from being output from the controller by buffering the buffer. The buffer unit is turned off when the base is connected to the vertical synchronous signal input terminal and the high of the vertical synchronous signal is input. A first transistor Q1 and a base connected to the collector of the first transistor Q1 and turned off when the vertical synchronization signal is high input and turned on when the vertical synchronization signal is not input. The base is connected to the collector of the second transistor Q2 so that the high of the vertical synchronization signal is input. When turned on and the vertical synchronization signal is not input, the third transistor Q3, which is turned off, the base is connected to the collector of the second transistor Q2, and the emitter is connected to the emitter of the third transistor Q3 and the input terminal of the controller. A fourth transistor (Q4) which is turned on as the high of the vertical synchronization signal is input, and is turned on when the signal is input to the input terminal of the controller and is turned on when the vertical synchronization signal is not input. It consists of.

LCD, vertical sync signal, data enable, gate start signal, buffer, ground

Description

A liquid crystal display device driving circuit having a buffer {A DRIVING CIRCUIT OF LIQUID CRYSTAL DISPLAY DEVICE HAVING BUFFER}

1 is a view showing the structure of a conventional liquid crystal display device.

2A is a waveform diagram illustrating a vertical synchronization signal input to a control unit of a conventional liquid crystal display device.

2B is a waveform diagram illustrating a gate start signal output from a control unit of a conventional liquid crystal display device.

3A is a waveform diagram illustrating a state in which a vertical synchronization signal is not applied to a control unit of a conventional liquid crystal display device.

Figure 3 (b) is a waveform diagram showing an irregular internal oscillation vertical synchronization signal generated by the control unit by the data enable signal when the unstable power supply when the vertical synchronization signal is not input.

FIG. 3C is a waveform diagram showing a gate start signal generated by the internal oscillation vertical synchronization signal of FIG.

4 is a view showing the structure of a liquid crystal display device according to the present invention;

FIG. 5 is a circuit diagram illustrating a structure of a buffer unit of FIG. 4. FIG.

Fig. 6 is a waveform diagram showing a signal generated by the buffer section when the vertical synchronization signal is input to the buffer section.

Fig. 7 is a waveform diagram showing a signal generated by the buffer section when the vertical synchronization signal is not input to the buffer section.

** Explanation of symbols for main parts of drawings **

101: liquid crystal panel 110: gate driver IC

112: data driver IC 120: interface unit

121: buffer unit 122: control unit

124: DC / DC converter 126: gate drive interface unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and in particular, a buffer is provided so that when the vertical synchronous signal is not applied to the controller, the internal oscillation vertical synchronous signal generated by the controller is removed by the data enable signal. A driving circuit of a liquid crystal display device capable of preventing the / DC converter from becoming inoperable.

Liquid crystal display devices are transmissive flat panel displays, and are widely applied to various electronic devices such as mobile phones, PDAs, and notebook computers. Such LCDs are currently being practically used in comparison with other flat panel displays in that they can be made light and small and have high image quality. Moreover, as the demand for digital TVs, high-definition TVs, and wall-mounted TVs increases, studies on large-area LCDs applicable to TVs are being actively conducted.

In general, LCDs can be divided into several methods depending on how the liquid crystal molecules are operated. However, active matrix thin film transistor LCDs are mainly used in terms of fast reaction speed and low afterimage. It is used.

The TFT-LCD described above is shown in FIG. As shown in the figure, in the TFT-LCD, data, a clock signal, a horizontal sync signal (H _sync ), a vertical sync signal (V _sync ) and an enable from an external host, for example, a CPU of a computer. An interface unit 20 into which various signals such as signals are input, a controller 22 connected to the interface unit 20 to process data input through the interface unit 20, and generate and output a control signal; A DC / DC converter 24 connected to the interface unit 20 to convert a level of a power supply voltage supplied through the interface unit 20 to a voltage required for the LCD, and a controller 20. A gate driver integrated circuit (10) and a data driver IC (12) connected to each other and driven according to a signal input from the controller 20 to output a gate signal and a data signal, respectively; Gate driver IC (10) and data port A signal is applied from the same IC 12 to constitute an actual image.

Although not shown in the figure, the liquid crystal panel 1 includes a TFT array substrate on which a TFT array is formed and a color filter substrate on which a color filter is formed, and a liquid crystal layer is formed between the TFT array substrate and the color filter substrate. As shown in the figure, in the TFT array substrate of the liquid crystal panel 1, a plurality of pixels are defined by the gate lines 3 and the data lines 5 arranged vertically and horizontally. Is formed. The gate electrode of the TFT 7 is connected to the gate line 3 and the drain electrode is connected to the data line 5 so that a scan signal is applied from the gate driver IC 10 to the gate electrode through the gate line 3. If the semiconductor layer of the TFT (not shown) is activated, the data signal supplied from the data driver IC 12 to the data line 5 is applied to the pixel electrode formed in the pixel through the source / drain electrodes, thereby liquid crystal molecules. Will be activated.

Meanwhile, a DC voltage, for example, a DC voltage of about 3.3 V is input to the controller 22 and the DC / DC converter 24 through the interface unit 20, and in the DC / DC converter 24, The level of the input DC voltage is converted to output DC voltages of, for example, about -5V, 8.7V, and 16V. In this case, the DC voltage level converted by the DC / DC converter 24 and output is used to operate the gate driver IC 10 and the data driver IC 12. DC voltages of 5 V (V _gl ) and 16 V (V _gh ) are applied, and a DC voltage of 8.7 V is applied to the data driver IC 12.

The controller 22 generates and outputs a signal for driving the liquid crystal display device. The output signal is a sync signal (H _sync , V _sync ) and a data enable signal input through the interface unit 20. Is generated by the clock signal. In general, a case in which an output signal is generated by the synchronization signals H _sync and V _sync is called a synchronization mode, and a case in which an output signal is generated by the data enable signal DE is called a data enable mode. ) Selects and executes the two modes according to the input synchronization signals H _sync and V _sync .

The signal generated by the controller 22 is input to the gate driver IC 10 and the data driver IC 12 to drive the liquid crystal panel 1. Meanwhile, in order to operate the gate driver IC 10, the controller 22 outputs a gate start signal S _GSP , which is a reference signal indicating the start point of the gate, to the gate driver interface unit 26. 2 (a) and 2 (b) show the vertical synchronization signal V _sync inputted to the controller 22 and the gate start signal S _GSP outputted from the controller 22, respectively. As the V _sync is input, it can be seen that a gate start signal S _GSP corresponding thereto is generated. At this time, the vertical synchronization signal (V _sync ) is a signal of 60Hz.

On the other hand, when the vertical sync signal V _sync is not input, the controller 22 operating in two modes of the synchronous mode and the data enable mode directly generates an internal oscillating vertical synchronous signal by the input data enable signal. To generate the gate start signal S _GSP . However, when the internal oscillation vertical synchronization signal is generated by the data enable signal as described above, a problem occurs during the initial operation. That is, the control unit 22 is supplied with very unstable power during initial driving. Since the unstable power supply causes irregular oscillation to the control unit 22, the controller 22 is irregular to the control unit 22 due to the irregular internal oscillation vertical synchronization signal. The gate start signal S _GSP is generated and output.

3 is a view illustrating a signal waveform of the gate start signal S _GSP generated when the vertical synchronization signal V _sync is not applied to the controller 22. FIG. 3 (a) illustrates the vertical synchronization signal V _sync . 3 (b) is generated by unstable power supply during initial operation of the internal oscillation vertical synchronization signal generated in the controller by the data enable signal DE applied to the controller 22. FIG. FIG. 3C is a diagram illustrating a gate start signal S _GSP generated by the internal vertical synchronization signal. As shown in the figure, the gate start that is generated by an internal oscillation vertical synchronizing signal signal (S _GSP) to Figure 2 (b) the external vertical synchronizing signal (V _sync) the gate start signal (S _GSP generated by shown in ), It can be seen that not only the pulses are irregular but also the amount of pulses applied is greatly increased. Therefore, the gate start signal S _GSP is applied to the gate driving interface 26 at a very short period compared to the normal operation (operation corresponding to the external vertical synchronization signal V _sync ).

The gate driving interface 26 is supplied with a DC voltage V _gl of about −5 V and a DC voltage V _gh of 16 V from the DC / DC converter 24. Therefore, when the gate start signal S _GSP having a short period is applied to the gate driving interface 26, a relatively large DC voltage V _gh is output in a short period (almost simultaneously), such as 16V. The DC / DC converter 24 is subjected to an excessive load. As a result, the DC / DC converter 24 has become inoperable, and there is a problem that the liquid crystal display element becomes inoperable.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. When the vertical synchronization signal is not input by installing a buffer unit in front of the control unit operating in the synchronization signal mode and the data enable mode, the data enable signal is unstable due to unstable power supply. Drive circuit of the liquid crystal display device which can prevent the DC / DC converter from becoming inoperable due to excessive load by buffering irregular internal oscillation vertical synchronization signal generated from the controller to ground to prevent the gate start signal from being output from the controller. The purpose is to provide a furnace.

In order to achieve the above object, the driving circuit of the liquid crystal display device according to the present invention comprises a gate driving means and data driving means for applying a gate signal and a data signal to a gate line and a data line formed in the liquid crystal panel, respectively, and data from the outside. The interface unit to which a signal, a power supply voltage, a vertical synchronization signal, and a data enable signal are input, and a data signal input through the interface unit are processed and output to the gate driving means and the data driving means, and the input vertical synchronization signal and data are inputted. A controller for generating and outputting a gate start signal by an enable signal, a DC / DC converter for converting a level of a power supply voltage input through the interface unit, and supplying the gate and data driving means to the gate driver and the data driver; Connected to the DC converter and the controller, the gate start signal is input from the controller. The gate drive interface unit for transferring the level voltage of the DC voltage converted by the DC / DC converter to the gate driving means, and the control unit by the data enable signal when the unstable power supply is located in the front of the control unit when the vertical synchronization signal is not input And a buffer unit configured to buffer an irregular oscillation signal generated by the ground to prevent the gate start signal generated by the irregular oscillation signal from being output from the controller.

When a 3.3V power supply voltage is input to the DC / DC converter, the input power supply voltage level is converted to -5V, 8.7V, or 16V, and the 8.7V power supply voltage is supplied to the data driving means. Supply to the gate driving means through the gate driving interface unit.

The buffer unit is for buffering the irregular internal oscillation vertical synchronization signal generated by the controller to ground. When the base is connected to the vertical synchronization signal input terminal, the buffer unit is turned off as the high of the vertical synchronization signal is input and the vertical synchronization signal is not input. The first transistor Q1 to be turned on and the second transistor Q2 to be turned on when the base is connected to the collector of the first transistor Q1 and turned off when the vertical synchronization signal is high input and the vertical synchronization signal is not input. And a third transistor Q3 that is turned on when the base is connected to the collector of the second transistor Q2 and the high of the vertical synchronous signal is input, and is turned off when the vertical synchronous signal is not input. The emitter is connected to the collector of transistor Q2 and the emitter is connected to the emitter of the third transistor Q3 and the input terminal of the controller. If power is turned off as the signal is inputted to the input terminal of the controller is not the vertical synchronizing signal is inputted is composed of a fourth transistor (Q4) for buffering the signal is turned to be oscillated by the controller to ground.

According to the present invention, a buffer unit is provided in front of a control unit of a liquid crystal display driver driving unit operating simultaneously in a synchronous mode and a data enable mode to buffer an oscillation signal generated by the control unit in the data enable mode to ground. The oscillation signal of the control unit means an internal vertical synchronizing signal generated by the data enable signal. When the vertical synchronizing signal is buffered to the ground as described above, the vertical synchronizing signal is not input to the control unit from the outside. By not outputting the gate start signal, the DC / DC converter is prevented from falling into a malfunction state.

4 shows a TFT-LCD according to the present invention. As shown in the figure, the TFT-LCD of the present invention has a structure substantially similar to the conventional TFT-LCD shown in FIG. The difference between the TFT-LCD of the present invention and the conventional TFT-LCD is that in the TFT-LCD of the present invention, a buffer unit 121 is provided between the interface unit 120 and the control unit 122. Therefore, hereinafter, a detailed description of the same configuration as in the prior art will be omitted.

As shown in the figure, the horizontal synchronization signal (H _sync ) and the vertical synchronization signal (V _sync ) input from an external host or the like through the interface unit 120 are input to the controller 122 through the buffer unit 121. do. In addition, the controller 122 receives a data signal, a clock signal, and a data enable signal through the interface unit 120. The data enable signal is to generate an output signal by the data enable mode when the horizontal sync signal H _sync and the vertical sync signal V _sync are not input to the controller 122.

The controller 122 generates and outputs a signal according to a synchronization mode and a data enable mode. If via the interface unit 120, a synchronization signal (H _sync, V _sync) is input, the synchronization signal (H _sync, V _sync) is input to the controller 122 via the buffer unit 121, a synchronization signal ( When H _sync and V _sync are not input, an internal oscillation synchronization signal (especially a vertical synchronization signal) generated in the controller 122 by the data enable signal DE is buffered to the ground through the buffer unit 121. do.

As described above, when the data enable signal DE is input to the controller 122 to generate an internally generated irregular vertical synchronization signal (especially, in the case of a vertical synchronization signal generated during unstable power supply of initial driving) Since the vertical synchronizing signal is buffered to ground through the buffer unit 121, the internal oscillating vertical synchronizing signal (that is, irregular oscillation signal) generated by the control unit 122 is not input to the gate driving interface unit 126 so that DC The / DC converter 124 is prevented from becoming inoperable due to excessive load.

5 is a circuit diagram illustrating the buffer unit 121. As shown in the figure, the buffer unit 121 includes four transistors Q1 to Q4. The base of the first transistor Q1 is connected to the vertical synchronization signal input terminal, the power supply Vcc is connected to the emitter, and the collector is grounded. In addition, the base of the second transistor Q2 is connected to the collector of the first transistor Q1, the emitter is grounded, and the collector is connected to the power supply Vcc.

The base of the third transistor Q3 and the fourth transistor Q4 is connected to the collector of the second transistor Q2. In addition, the collector of the third transistor Q3 is connected to a power source, and the emitter is connected to the vertical synchronous signal input terminal of the controller 122 and the emitter of the fourth transistor Q4. The collector is grounded.

The operation of the buffer unit 121 configured as described above will be described in detail according to the vertical synchronization signal shown in FIG. 6.

First, when the vertical synchronous signal V _sync shown in FIG. 6 (a) is input through the vertical synchronous signal input terminal, the first transistor Q1 inputs a high (H) signal of the vertical synchronous signal V _sync . The voltage Va, which is turned off at the time of turn-off and is turned on when the low signal is input, is applied to the collector of the first transistor Q1 to have a waveform as shown in FIG. 6 (b), and the voltage Va This base is applied to the base of the second transistor Q2. On the other hand, the second transistor Q2 is operated by the voltage Va applied to the base. When the voltage Va of the high H is applied to the base of the second transistor Q2 (corresponding to the low of the vertical synchronization signal V _sync ), the second transistor Q2 is turned on so that the second transistor Q2 is turned on. The third transistor Q3 connected to the collector of < RTI ID = 0.0 > 1) < / RTI > is turned off and the fourth transistor Q4 is turned on, so that the voltage across the emitter of the third transistor Q3 as shown in FIG. Vb) goes low. When the voltage Va of the low L is applied to the base of the second transistor Q2 (corresponding to the high of the vertical synchronization signal V _sync ), the second transistor Q2 is turned off so that the third transistor is turned off. Q3 is turned on and the fourth transistor Q4 is turned off so that the voltage Vb across the emitter of the third transistor Q3 becomes high. Accordingly, the voltage Vb applied to the emitter of the third transistor Q3 becomes a waveform as shown in FIG. 6C and is input to the vertical synchronous signal input terminal of the controller 122.

As described above, when the vertical synchronization signal V _sync is input, as shown in FIG. 6, the voltage Vb input to the controller 122 is the vertical synchronization signal V _sync input to the buffer unit 121. Since the same waveform as in FIG. 3 is obtained, the control unit 122 outputs a signal having the same waveform as that of the conventional gate start signal shown in FIG.

On the other hand, as shown in FIG. 7A, when the vertical synchronization signal is not input to the buffer unit 121, the first transistor Q1 of the buffer unit 121 is turned on so that the first transistor Q1 is turned on. The waveform of the voltage Va across the collector is Vcc as shown in Fig. 7B. Accordingly, the second transistor Q2 to which the voltage Va is applied is always turned on so that the third transistor Q3 connected to the collector of the second transistor Q2 is turned off and the fourth transistor Q4 is turned on. In this state, since no signal is input to the control unit 122 as shown in FIG. 7C, the control unit 122 is internally oscillated by an enable signal, which is data input through the interface unit 120. It generates a vertical synchronization signal.

However, as shown in the figure, since the third transistor Q3 is turned off and the fourth transistor Q4 is turned on, the vertical synchronization signal V _sync input terminal of the controller 122 is buffered to ground. . Therefore, when an irregular internal oscillation vertical synchronization signal is generated in the control unit 122 by unstable power supply, the generated internal oscillation synchronization signal is not output to the gate driving interface unit 126 and the fourth transistor Q4 is closed. Buffered to ground.

Therefore, the gate start signal S _GSP of the short period generated by the irregular internal oscillation vertical synchronization signal is not output to the gate driving interface unit 126, and as a result, excessive load is applied to the DC / DC converter 124. Is not applied to prevent the DC / DC converter 124 from becoming inoperable.

As described above, the liquid crystal display device driving circuit of the present invention includes a buffer unit in front of a control unit for inputting a signal through an interface unit, so that when the vertical synchronization signal is not inputted, the data enable signal is unstable during power supply. By buffering the irregular internal oscillation signal generated by the control unit to the ground through the buffer. Therefore, the simultaneous multiple gate start signal generated by the irregular internal oscillation signal is not output from the controller, thereby effectively preventing the DC / DC converter from becoming inoperable due to excessive load.

Claims (5)

Gate driving means and data driving means for applying a gate signal and a data signal to gate lines and data lines formed on the liquid crystal panel, respectively; An interface unit to which a data signal, a power supply voltage, a vertical synchronization signal, and a data enable signal are input from the outside; A controller which processes a data signal input through the interface unit and outputs the data signal to the gate driving means and the data driving means, and generates and outputs a gate start signal by the input vertical synchronization signal and the data enable signal; A DC / DC converter converting a level of a power supply voltage input through the interface unit and supplying the level to the gate driver and the data driver; And If the vertical synchronization signal is not located at the front end of the controller, an unstable oscillation signal generated by the controller is buffered to ground by the data enable signal when the power supply is unstable and the gate start signal generated by the irregular oscillation signal is controlled. A driving circuit for a liquid crystal display element, comprising a buffer portion for preventing output from the display. The driving circuit of claim 1, wherein the controller executes a synchronization signal mode and a data enable mode. The gate driving interface unit of claim 1, further comprising a gate driving interface unit connected to the DC / DC converting unit and the control unit and transferring a DC voltage level converted by the DC / DC converting unit to a gate driving unit as a gate start signal is input from the control unit. The driving circuit of the liquid crystal display device comprising a. The method of claim 1, wherein the buffer unit, A first transistor Q1 that is turned off when the base is connected to the vertical synchronous signal input terminal and is turned on as the high of the vertical synchronous signal is input, and is not inputted; A second transistor Q2 connected to a collector of the first transistor Q1 to be turned off when the vertical synchronization signal is high input and turned on when the vertical synchronization signal is not input; A third transistor Q3 connected to a collector of the second transistor Q2 and turned on when the high of the vertical synchronization signal is input, and turned off when the vertical synchronization signal is not input; And The base is connected to the collector of the second transistor Q2 and the emitter is connected to the emitter of the third transistor Q3 and the input of the controller. The signal is turned off as the high of the vertical synchronization signal is input. And a fourth transistor (Q4) which is turned on and buffers the signal oscillated by the controller to ground when the vertical synchronization signal is not input. The driving circuit of claim 1, wherein the signal input to the input terminal of the controller as the vertical synchronization signal is the same waveform as the vertical synchronization signal.

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