JPH06337655A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption of a driving circuit of a liquid crystal display device by cutting off a current flowing in a buffer circuit in a vertical flyback period and a horizontal flyback period. CONSTITUTION:An output line of a buffer circuit is connected to a drain line of a liquid crystal display device through a resistor 18. And an N channel MOS 19 for controlling operation of a buffer circuit is connected between the buffer circuit and the ground potential, the MOS 19 is controlled by a control signal HE. Therefore, when the control signal HE is in an H level, the buffer circuit is operated, but when the control signal HE is in an L level, a current flowing in the buffer circuit is cut off. The control signal HE is made an L level in a period excluding a horizontal scanning period displayed in an effective display line of dot lines located from the uppermost section of the liquid crystal display device to the lowermost, that is, a vertical flyback period, and a period in which the liquid crystal display device is shifted from a line to a next line, that is, a horizontal flyback period, and the control signal HE is made an H level in a period in which a video signal of one horizontal scanning period is displayed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit, and more particularly to a drive circuit for displaying a TV image on a liquid crystal display device in which thin film transistors (TFTs) and pixel electrodes are arranged in a matrix.

[0002]

2. Description of the Related Art Generally, a driving circuit for displaying a TV image on a liquid crystal display device in which TFTs and pixel electrodes are arranged in a matrix at intersections of a plurality of gate electrode lines and a plurality of drain electrode lines is a horizontal pixel. A video signal for one horizontal period is sampled and held by a sampling clock according to the number (that is, the number of drain electrode lines), and an output voltage corresponding to the held signal voltage is supplied to each drain electrode line. ing.

Conventionally, a drive circuit for supplying a voltage to a drain electrode line holds two video signals which carry out a sampling operation alternately every horizontal period and a video signal after the sampling for one horizontal period is completed. It is composed of a buffer circuit which selects the output of the sampling circuit and supplies a voltage corresponding to the output voltage to the drain electrode line. In addition, this buffer circuit is a differentially connected MOS.
It is mainly composed of a transistor differential amplifier and its output MOS transistor.

[0004]

However, in the conventional liquid crystal drive circuit, the sampling of the video signal in one horizontal period is completed and the sampling in the next horizontal period is started, that is, during the horizontal blanking period, and Since the operation of the buffer circuit is continued during the period in which the display of one field ends and the display of the next field starts, that is, the vertical blanking period,
There was a drawback that there was a lot of unnecessary power consumption.

[0005]

The present invention has been made in view of the above points, and a liquid crystal in which a TFT and a pixel electrode are provided at each intersection of a plurality of gate electrode lines and a plurality of drain electrode lines. In a drive circuit that supplies a drive signal to a display panel, a sampling circuit that holds a video signal voltage to be applied to the pixel electrode, a buffer circuit that outputs a voltage according to the output of the sampling circuit to the drain electrode line, A switching element for operation control is provided between the buffer circuit and a power supply line or a ground line, and the switching element is turned off during a vertical blanking period and a horizontal blanking period of a video signal to reduce power consumption. It will be reduced.

[0006]

According to the above-mentioned means, the switching element is turned on and the buffer circuit operates only during the horizontal scanning line displayed on the liquid crystal display device and the timing of the video signal displayed on the horizontal scanning line. Then, during the horizontal blanking period and the vertical blanking period which are not displayed on the liquid crystal display device, the switching element is turned off, so that the current flowing through the buffer circuit is cut off. Therefore, unnecessary current flowing through the buffer circuit is eliminated, and power consumption is reduced.

[0007]

1 is a circuit diagram showing an embodiment of the present invention. In FIG. 1, the sampling circuit 1 is composed of two sampling circuits. The first sampling circuit includes an AND gate 1 to which a timing signal TQ and a sampling control pulse SR are applied, a transmission gate 2 that is controlled by the output of the AND gate 1 and that passes and blocks the video signal VIDEO, and a transmission gate 2. The second sampling circuit is also composed of a capacitor 3 that is charged by the passed video signal.
The AND gate 4 to which the timing signal BQ and the sampling control pulse SR are applied, the transmission gate 5, and the capacitor 6. Here, the timing signals TQ and BQ are signals that are inverted every horizontal scanning period, and have a relationship of inverted signals with each other. Therefore, A
Sampling control pulses SR corresponding to dots in the horizontal period are alternately output from the ND gates 1 and 4 every horizontal period, and the sampling operations of the first sampling circuit and the second sampling circuit are alternately performed.

The transmission gates 7 and 8 are circuits that select the sampling results of the first sampling circuit and the second sampling circuit according to the control signals K and M. For example, the first sampling circuit performs sampling operation. In the horizontal scanning period, the output of the second sampling circuit is selected. The buffer circuit is a differentially connected P
Channel MOS 9 and 10 and N channel M connected to the MOS 9 and 10 and connected in current mirror
OSs 11 and 12, a P-channel MOS 13 that supplies a constant current to the MOSs 9 and 10, a P-channel output transistor MOS14 whose gate is connected to the drain of the MOS 10, and a P-channel MOS15 that supplies a constant current to the MOS 14, MOS 16 that charges the capacitance of the differential input to the initial value, and M that charges the capacitance of the output line to the initial value
It is composed of the OS 17. The output line of the buffer circuit is connected to the drain line of the liquid crystal display device via the resistor 18. An N channel MOS 19 for controlling the operation of the buffer circuit is provided between the buffer circuit and the ground potential.
Are connected, and the MOS 19 is controlled by the control signal HE. Therefore, when the control signal HE is at H level, the buffer circuit operates, but when it is at L level, the current flowing through the buffer circuit is cut off.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. Without using the transmission gates 7 and 8 shown in FIG. 1, the output of the first sampling circuit and the second
It uses a circuit that selects the output of the sampling circuit. The same parts as those in FIG. 1 are designated by the same reference numerals. Capacitor 3 which is the output of the first sampling circuit
Is connected to the gate of the P-channel MOS 20, and the capacitor 6 which is the output of the second sampling circuit.
Is connected to the gate of the P-channel MOS 21. N-channel MOSs 22 and 23 are connected in series to the MOSs 20 and 21, respectively, and these series circuits are connected between the MOS 13 and the MOS 11. That is, the MOSs 20 and 21 are selectively differentially connected to the MOS 10 by the MOSs 22 and 23 controlled by the control signals K and M, respectively. According to the configuration of FIG. 2, the charges charged in the capacitors 3 and 6 do not flow out when the MOSs 22 and 23 are turned on, and the loss of the sampled video signal can be prevented.

The operation of the circuit shown in FIGS. 1 and 2 will be briefly described below with reference to the timing chart shown in FIG. The timing signals TQ and BQ are signals that are inverted every horizontal scanning period, and have a relationship of inverted signals. Further, the control signal K is a signal which is at the H level during the period in which the video signal during the horizontal scanning period is displayed when the timing signal BQ is at the H level and the second sampling circuit performs sampling. At this time, the output of the first sampling circuit is selectively output to the buffer circuit. On the other hand, the control signal M is the timing signal TQ.
Is at the H level, and when the sampling of the first sampling circuit is performed, the signal is at the H level during the period in which the video signal is displayed. At this time, the output of the second sampling circuit is output to the buffer circuit. It

The control signal HE is in a period other than the horizontal scanning period displayed on the effective display line of the dot lines from the uppermost dot line to the lowermost dot line of the liquid crystal display device, that is, in the vertical blanking period. Sometimes it becomes L level, and further becomes L level during the period from the line of the liquid crystal display device to the next line, that is, the horizontal retrace line period, and 1
It becomes H level during the period during which the video signal is displayed during the horizontal scanning period.

Therefore, while the control signal HE is at the L level, the MOS 19 is turned off and the current flowing in the buffer circuit is cut off, and the MOS 16 and MOS 17 are turned on so that the output line of the buffer has the power supply voltage V _DD. , And in FIG. 1, the input of the buffer is precharged to the predetermined potential V _BIS .

[0013]

As described above, according to the present invention, during the vertical blanking period and the horizontal blanking period, since the current flowing through the buffer circuit is cut off, unnecessary power consumption is eliminated, and liquid crystal of low power consumption is achieved. A drive circuit of a display device can be obtained. Particularly, in a liquid crystal TV receiver driven by a battery, a great effect of extending the battery life is produced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a timing diagram showing an operation of the circuit shown in FIGS. 1 and 2.

[Explanation of symbols]

1, 4 AND gates 2, 5, 7, 8 Transmission gates 3, 6 Capacitors 9, 10 13, 14, 15, 16, 17, 20, 21
P channel MOS 11, 12, 19, 22, 23 N channel MOS

Claims (1)

[Claims] 1. A video signal for applying to a pixel electrode in a drive circuit for supplying a drive signal to a liquid crystal display panel in which a TFT and a pixel electrode are provided at each intersection of a plurality of gate electrode lines and a plurality of drain electrode lines. A sampling circuit that holds a voltage, a buffer circuit that outputs a voltage according to the output of the sampling circuit to the drain electrode line, and a switching element for operation control between the buffer circuit and a power supply line or a ground line A liquid crystal drive circuit, wherein the switching element is turned off during a vertical blanking period and a horizontal blanking period of a video signal.