JPH07199872A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To realize a liquid crystal display device with a testing circuit whose power source is capable of being cut at the time of a normal display. CONSTITUTION:A built-in testing circuit 21 of a liquid crystal display device is driven by a power source VDD-T other than a power source VDD supplied to a gate driver 6 and a drain driver 7 and is constituted of inverters 22 receiving signals of respective gate lines, CMOS transfer gates 9 connected with respective gate lines via inverters 22, inverters 10 driving CMOS transfer gates 9, a shift register 11 allowing inverters 10 to operate successively and an output line 12 outputting gate lines outputted via transfer gates 9 at the time of a testing as a testing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used for a liquid crystal projector, a liquid crystal television, etc., and more particularly to a liquid crystal display device having a test circuit formed on an active matrix panel integrated with a drive circuit.

[0002]

2. Description of the Related Art Active matrix display (active m
In the atrix display method, by arranging a nonlinear active element in each pixel, extra signal interference can be eliminated and high image quality can be realized.

Conventionally, a display device, particularly a display device using a liquid crystal display panel, has a gate line (scanning line) 1 and data arranged in m rows and n columns, as shown in a display device with a test circuit in FIG. The switching elements 3, the pixel capacitors 4 and the common electrodes 5 are arranged in a matrix at each intersection of the lines 2, each gate line 1 is connected to a gate driver 6 including a buffer and a scan side shift register, and each data line 2 is connected. A drain driver 7 including a transfer gate circuit and a data side shift register
Are connected to each.

In this active matrix display system,
A matrix electrode, a plurality of pixel capacitors (pixel electrodes) 4 and a common electrode 5 are provided on the inner surface of one of the electrode substrates, and a switching element such as a TFT (thin
film transistor) elements are arranged, the switching elements are matrix-driven, and each pixel capacitance 4 is switched via the switching element 3.

The shift register constituting the gate driver 6 sequentially outputs scanning signals G1 to G4 to each gate line 1 via a buffer (not shown), and the scanning signals G1 to G4 are sequentially output.
G4 is 1 horizontal scanning period (63.5 μs), that is, 1
During the H period, the switching element 3 connected to each gate line 1 is turned on by sequentially becoming high level, and the pixels connected to the gate line 1 are sequentially selected and driven.

Further, the shift register constituting the drain driver 7 outputs a drive signal to the transfer gate circuit connected to each data line 2 to sequentially turn on the transfer gate circuit to transfer the video signal to the turned-on transfer. The data line 2 connected to the gate circuit is supplied and the data line 2 is charged. Then, this video signal passes through the switching element 3 connected to the gate line 1 selected at that time,
It is applied to the pixel capacitor 4 connected to the gate line 1.

On the other hand, the drive circuit integrated type liquid crystal display device has a built-in test circuit 8 (see a broken line in FIG. 3) for performing an operation test of the liquid crystal display panel.

The built-in test circuit 8 includes a CMOS transfer gate 9 connected to each gate line 1 and a CMOS transfer gate 9.
An inverter 10 for driving the transfer gate 9, a shift register 11 for sequentially operating the inverter 10,
In the test, the gate line 1 output through the CMOS transfer gate 9 is output as a test signal.

The operation of the liquid crystal display device integrated with the drive circuit is as follows.

First, one of the gate lines G1 to G4 is boosted to the H level by the gate driver 6, and all the pixel transistors (switching elements 3) connected to the gate line 1 are turned on. At that time, the drain driver 7 The output display signal is applied to the pixel capacitor 4,
The pixels of one horizontal line are displayed. Then, the next one of the gate lines is boosted and the same operation is repeated.

The operation of the built-in test circuit 8 is as follows.

During the test, the output of the shift register 11 and the output of the inverter 10 based on the output are CMOS.
The signal is input to the gate of the transfer gate 9, and the signal of the gate line 1, that is, the output signal of the gate driver 6 is sequentially output to the output line 12.

Here, for example, if there is a defect in the output line of the gate driver 6, that is, the gate line 1, the output signal of the gate driver 6 cannot be correctly transmitted to the test output line 12. For example, an example of a defect in the gate line 1 is shown in FIG.
3a, 3b and 3c and the timing chart of FIG. 4, the gate line shown in FIG. 3a is opened (broken), the high potential side power supply VDD is shorted shown in FIG. 3b, and c of FIG. If there is a GND short defect, the output signal of the gate driver 6 is not correctly transmitted to the test output line 12.

Therefore, as shown in the operation timing chart of FIG. 4, if there is no defect, the test output line 12
Results in an incorrect output for a defective gate line although the H level is constant. Here, the output signal in the defect of the VDD line short becomes the same as the normal output, but it can be detected by switching the output of the gate driver 6 to the opposite L level selection signal.

The built-in test circuit 8 is for detecting a defect in the gate line, but the same structure as the built-in test circuit 8 can be formed for the drain driver 7 and the drain line 2 as well. Operations can be performed to detect defects in the drain driver.

[0016]

However, in the liquid crystal display device in which the conventional test circuit 8 is formed, the power is supplied to the test circuit 8 even when the test operation is not performed. However, there is a problem in that the current consumption increases and the display quality deteriorates.

That is, in the test circuit 8, when the power is not supplied to the inverter 10 during the normal display, the output of the inverter 10 is turned off even if the input of the inverter 10 is turned off, and as a result, the CMOS transfer gate 9 is opened. Therefore, in order to keep all the CMOS transfer gates 9 off, it is necessary to supply power to the test circuit 8 as well, leading to an increase in current consumption.
Further, at that time, there is a problem in that channel leakage of the CMOS transfer gate 9 causes interference between gate line signals, resulting in deterioration of display quality.

Therefore, an object of the present invention is to provide a liquid crystal display device with a test circuit, which can be turned off during normal display.

[0019]

The invention according to claim 1 is
To achieve the above object, switching elements and pixel capacitors are arranged in a matrix at each intersection of a scanning line and a data line formed on a substrate, and a predetermined voltage level is supplied to the scanning line to output an output signal of the scanning line. In a liquid crystal display device having a test circuit for testing, the test circuit is configured to be driven by a power source different from circuits other than the test circuit.

According to a second aspect of the present invention, switching elements and pixel capacitors are arranged in a matrix at each intersection of the scanning line and the data line formed on the substrate, and a predetermined voltage level is supplied to the data line. In a liquid crystal display device having a test circuit for testing an output signal of a data line, the test circuit is configured to be driven by a power source different from circuits other than the test circuit.

For example, as described in claim 3, the test circuit is driven by the separate power supply during the test, and the supply of the separate power supply is stopped during the normal display operation to reduce the current consumption of the test circuit. It may be configured to be zero.

The test circuit may include, for example, an inverter that receives a signal of each scan or data line, a transfer gate that outputs the inverter output to a test output line during a test, and A shift register that sequentially turns on the transfer gates,
It may be composed of

[0023]

According to this structure, at the time of testing, the test circuit is driven by a power source different from circuits other than the test circuit, and the output of the shift register and the output of the inverter based on the output are fed to the gate of the transfer gate. An output signal that is input and supplied to a test line such as a scan line or a data line is inverted by an inverter and sequentially output to an output line. Further, during the normal display operation, the supply of the separate power source is stopped. Therefore, the power can be turned off during normal display, and the current consumption of the test circuit can be reduced to zero.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

1 and 2 are views showing an embodiment of a liquid crystal display device according to the present invention. This embodiment is applied to a display device in which a test circuit is formed on an active matrix panel integrated with a drive circuit. It was done.

FIG. 1 is a circuit diagram of a liquid crystal display device in which a test circuit of the present invention is formed, which has a built-in test circuit for detecting a defect in a gate line.

In FIG. 1, reference numeral 20 is a liquid crystal display device,
Reference numeral 21 is a built-in test circuit for detecting a defect in the gate line. The configuration of the liquid crystal display device 20 is similar to that of the liquid crystal display device of FIG. 3, and the same components are designated by the same reference numerals.

That is, as shown in the display device with a test circuit in the liquid crystal display device 20, the switching element 3 is provided at each intersection of the gate line (scan line) 1 and the data line 2 arranged in m rows and n columns. And pixel capacitors 4 and common electrodes 5 are arranged in a matrix, each gate line 1 is connected to a gate driver 6 which is composed of a buffer and a scan side shift register, and each data line 2 is connected to a transfer gate circuit and a data side shift register. And the like are connected to the drain drivers 7, respectively.

In this active matrix display system,
A matrix electrode, a plurality of pixel capacitors (pixel electrodes) 4 and a common electrode 5 are provided on the inner surface of one of the electrode substrates, and a switching element such as a TFT (thin
film transistor) elements are arranged, the switching elements are matrix-driven, and each pixel capacitance 4 is switched via the switching element 3.

The built-in test circuit 21 includes a gate driver 6
And an inverter 22 driven by a power supply VDD-T which is different from the power supply VDD supplied to the drain driver 7 and receiving a signal of each gate line 1, and a CMOS transfer gate 9 connected to each gate line 1 via the inverter 22.
An inverter 10 that drives the CMOS transfer gate 9, a shift register 11 that sequentially operates the inverter 10, and a CMOS transfer gate 9 during a test.
And an output line 12 for outputting the signal supplied to the gate line 1 as a test signal.

That is, the built-in test circuit 21 of the present embodiment.
Is a conventional test circuit 8 and each gate line 1 shown in FIG.
An inverter 22 is inserted between the power source VDD and the power source VDD supplied to the gate driver 6 and the drain driver 7 and a power source VDD different from the power source VDD.
Driven by -T.

Next, the operation of this embodiment will be described.

The operation of the liquid crystal display device 20 is as follows.

First, one of the gate lines G1 to G4 is boosted to the H level by the gate driver 6, and all the pixel transistors (switching elements 3) connected to the gate line 1 are turned on. At that time, the drain driver 7 The output display signal is applied to the pixel capacitor 4,
The pixels of one horizontal line are displayed. Then, the next one of the gate lines is boosted and the same operation is repeated.

The operation of the built-in test circuit 21 is as follows.
It looks like this:

During the test, the output of the shift register 11 and the output of the inverter 10 based on the output are CMOS
Input signals are input to the gate of the transfer gate 9, and the inverted signal of the inverter 22 of the gate line 1, that is, the inverted signal of the output signal of the gate driver 6 is sequentially output line 1.
2 is output.

Here, similarly to the conventional example, if there is a defect in the output line of the gate driver 6, that is, the gate line 1, the output signal of the gate driver 6 cannot be correctly transmitted to the test output line 12. For example, as shown in a, b, c of FIG. 1 and the timing chart of FIG. 2, examples of defects of the gate line 1 are shown as open lines (breakage) of the gate line shown in a of FIG. 2 and b in FIG. When there is no short circuit of the high-potential-side power supply VDD or short circuit defect of GND shown in FIG. 2C, the test signal line 12 is opposite to the test circuit 8 of FIG.
Is constant at the L level, but if the above defect exists, the result of FIG.
As shown in, the output is incorrect corresponding to the defective gate line.

Here, as in the case of the test circuit 8 of FIG. 3, the output signal in the defect of the VDD line short becomes the same as the normal output, but the output of the gate driver 6 is selected at the opposite L level. Switching to signal enables detection.

The built-in test circuit 8 is for detecting a defect in the gate line, but the drain driver 7 and the drain line 2 can be the same as the built-in test circuit 8 and can be formed. Operations can be performed to detect defects in the drain driver.

As described above, the built-in test circuit 21 of the liquid crystal display device 20 of this embodiment is driven by the power source VDD-T which is different from the power source VDD supplied to the gate driver 6 and the drain driver 7, and each gate is driven. An inverter 22 that receives a signal on line 1 and a CMOS transfer gate 9 connected to each gate line 1 via the inverter 22
An inverter 10 that drives the CMOS transfer gate 9, a shift register 11 that sequentially operates the inverter 10, and a CMOS transfer gate 9 during a test.
The gate line 1 output via the output line 12 for outputting as a test signal, the power supply VDD-T of the test circuit 21 can be turned off during the normal display operation. The current consumption can be reduced to zero. Further, since the channel leak of the CMOS transfer gate 9 becomes zero, the interference between the gate line signals is eliminated and the display quality can be improved.

In the present embodiment, the built-in test circuit 21
Is applied to a test circuit for detecting a defect in the gate line. However, the same structure as the built-in test circuit 21 can be formed for the drain driver 7 and the drain line 2, and the same operation is performed to perform the drain operation. It goes without saying that defects in the driver can be detected.

Further, although the liquid crystal display device is applied to the TFT active matrix in this embodiment, the present invention is not limited to this, and the kind, the number and the arrangement of the liquid crystal panels are arbitrary. For example, MIM (Metal). Insulator Metal)
LC driven by active matrix using diodes
It goes without saying that D can be similarly changed.

Further, it goes without saying that the circuits, matrixes, the number of gates, and the types of the liquid crystal display device and the test circuit are not limited to those in the above-described embodiments.

[0044]

According to the present invention, since the gate line test circuit is configured to be driven by a power supply different from circuits other than the test circuit, it is possible to turn off the power during normal display. Therefore, the current consumption of the test circuit can be reduced to zero. In addition, the display quality can be improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a timing chart at the time of testing the liquid crystal display device of the same example.

FIG. 3 is a circuit configuration diagram of a conventional liquid crystal display device.

FIG. 4 is a timing chart when testing a conventional liquid crystal display device.

[Explanation of symbols]

 1 gate line 2 drain line (data line) 3 switching element 4 pixel capacitance 5 common electrode 6 gate driver 7 drain driver 9 CMOS transfer gate 10, 22 inverter 11 shift register 20 liquid crystal display device 21 built-in test circuit

Claims (4)

[Claims] 1. A switching element and a pixel capacitance are arranged in a matrix at each intersection of a scanning line and a data line formed on a substrate, and a predetermined voltage level is supplied to the scanning line to output an output signal of the scanning line. A liquid crystal display device having a test circuit for testing, wherein the test circuit is configured to be driven by a power source different from circuits other than the test circuit. 2. A switching element and a pixel capacitance are arranged in a matrix at each intersection of a scanning line and a data line formed on a substrate, and a predetermined voltage level is supplied to the data line to output an output signal of the data line. A liquid crystal display device having a test circuit for testing, wherein the test circuit is configured to be driven by a power source different from circuits other than the test circuit. 3. The test circuit is configured to be driven by the separate power supply during a test, and to stop the supply of the separate power supply during normal display operation to reduce the current consumption of the test circuit to zero. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device. 4. The test circuit includes an inverter that receives a signal of each scan or data line, a transfer gate that outputs the inverter output to a test output line during a test, and a shift register that sequentially turns on the transfer gate. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is formed of: