JP2019113710A - Electro-optical apparatus - Google Patents

Abstract

To provide a detecting method of a defect of a scanning signal or its drive circuit output in drive timing of a display unit during actual use in an electro-optical apparatus.SOLUTION: A TFT substrate, in which a gate line and a data line are arranged in a matrix, that comprises a TFT 102 and a display area 100, in which a pixel electrode is formed, respectively in a crossing position of these signal lines, a gate line driving circuit 200 that drives the gate line at a peripheral part on the TFT substrate, and a gate signal abnormality detection circuit 400 are formed, and the gate signal abnormality detection circuit is arranged at an opposite side relative to the gate line driving circuit by sandwiching the display area, and further the gate signal abnormality detection circuit is driven by the gate signal GL output from the gate line driving circuit to the gate line, and the gate signal is input to the gate signal abnormality detection circuit through the gate line.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electro-optical device and can be suitably used for an electro-optical device having an abnormality detection function during display operation.

  Nowadays, in addition to conventional navigation devices, display for automotive use in applications such as an instrument panel which is an instrument panel such as a speedometer and a warning lamp to be assembled to a dashboard, and a back monitor for displaying an image behind a vehicle. The application of the device is expanding. Therefore, information on display operations when the driver drives the vehicle is becoming more important.

  In particular, ISO26262, which is an international standard for functional safety related to electricity / electronics of automobiles, has also been formulated, and the function of detecting an abnormality in display operation is important.

Further, in recent years, development has been advanced as a transistor in which an oxide semiconductor capable of easily achieving higher field effect mobility than amorphous silicon is incorporated as a driver circuit on a panel.

Patent Document 1 discloses a drive circuit output unit in a display device and a method of detecting a defect in a scanning line.

Japanese Patent Application Laid-Open No. 10-97203

  This is used to detect defects in the manufacturing process, and it is necessary to charge and discharge the voltage of the detection terminal within one horizontal drive period at the display drive timing in actual use, so a particularly large panel or high It could not be applied in the resolution panel. The technology disclosed in the present specification has been made to solve the problems as described above, and in actual use of the display device, the scanning signal line or the signal An electro-optical device capable of detecting a defect in a drive circuit output.

  According to an aspect of the electro-optical device according to the present invention, a TFT substrate provided with a display area in which scanning signal lines and image signal lines are arranged in a matrix, and thin film transistors and pixel electrodes are formed at intersections of these signal lines. In an electro-optical device having an electro-optical layer corresponding to the display area, a scanning signal line drive circuit for driving the scanning signal line around the display area on the TFT substrate, and a scanning signal abnormality detection circuit. The scan signal abnormality detection circuit is disposed on the opposite side of the display area with respect to the scan signal line drive circuit, and the scan signal abnormality detection circuit is configured to receive the scan signal from the scan signal line drive circuit. The scanning signal is driven by a scanning signal output to a line, and the scanning signal is input to the scanning signal abnormality detection circuit via the scanning signal line.

  The electro-optical device according to the present invention makes it possible to detect defects in the scanning signal and the output of the drive circuit at the drive timing of the display unit in actual use.

FIG. 1 is a schematic block diagram showing a configuration of a liquid crystal display device according to Embodiment 1. It is a figure which shows the structure of the gate line drive circuit shown in FIG. FIG. 5 is a diagram showing timings of a gate line drive circuit and a scanning signal abnormality detection circuit according to the first embodiment. It is a figure which shows the structure of the scanning signal abnormality detection circuit shown in FIG. It is a figure which shows the concrete circuit structure of unit shift register circuit SFD in the scanning signal abnormality detection circuit shown in FIG. It is a modification which shows the specific circuit structure of unit shift resist circuit SFD which comprises the scanning signal abnormality detection circuit shown in FIG. It is another Example which shows the concrete circuit structure of unit shift resister circuit SFD which comprises the scanning signal abnormality detection circuit shown in FIG. It is a specific circuit example of the abnormality determination circuit shown in FIG. FIG. 6 is a schematic block diagram showing a configuration of a liquid crystal display device according to Embodiment 2. It is a figure which shows the structure of the gate line drive circuit shown in FIG. It is a figure which shows the structure of the scanning signal abnormality detection circuit shown in FIG. FIG. 7 is a diagram showing timings of a gate line drive circuit and a scanning signal abnormality detection circuit according to a second embodiment.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings.

  Note that the drawings are schematically illustrated, and omission of the configuration or simplification of the configuration may be made as appropriate for the convenience of description. In addition, the interrelationships among sizes and positions of configurations and the like shown in different drawings are not necessarily accurately described, and may be changed as appropriate.

  Moreover, in the description shown below, the same code | symbol is attached | subjected and shown to the same code | symbol, and suppose that it is the same also about those names and functions. Accordingly, detailed descriptions about them may be omitted to avoid duplication.

  FIG. 1 is a schematic block diagram showing the configuration of a display device according to the present invention, and shows the configuration of a liquid crystal display device 10 as a representative example of the display device. As shown in FIG. 1, the display device according to the present embodiment includes a display panel 500, a timing controller 600, a voltage generation circuit 700, and an abnormality determination circuit 800, and the display panel 500 indicated by an alternate long and short dash line in FIG. The liquid crystal display unit 100 includes a gate line drive circuit 200 (scan signal line drive circuit), a source driver 300, and a scan signal abnormality detection circuit 400 (gate line signal abnormality detection circuit).

The liquid crystal display unit 100 indicated by a broken line in FIG. 1 includes a plurality of pixels 101 arranged in a matrix. Gate lines GL ₁ , GL ₂ ... GL _n are respectively provided for each row of pixels (hereinafter also referred to as “pixel line”), and data lines DL ₁ and DL ₂ are respectively provided for each column of pixels. ... DL _m are provided respectively. That is, the pixel 101 indicated by the broken line in the liquid crystal display unit 100 is formed in the vicinity of each intersection of the gate line GL and the data line DL orthogonal thereto. Here, it is also referred to as "pixel row" hereinafter. Further, the number "n" is the total number of pixel lines, that is, the number of gate lines, and the number "m" is the total number of data lines. In this embodiment, for convenience of explanation, the respective gate lines _{GL 1,} GL 2 · · · GL _n "gate lines GL", also the respective data lines _{DL 1, DL} 2 ··· _{DL m} ' Collectively referred to as "data line DL". For example, if the display panel 500 has an XGA resolution: 768 × 1024 R, G, B pixel configuration, the number n of gate lines is 768 and the number m of data lines is 3072.

  Each pixel 101 includes a pixel switch element 102 provided between the corresponding data line DL and the pixel node Np, a capacitor 103 (auxiliary capacitance) connected in parallel between the pixel node Np and the common electrode node Nc, and liquid crystal And a display element 104. The orientation in the liquid crystal display element 104 changes in accordance with the voltage difference between the pixel node Np and the common electrode node Nc, and in response to this, the display luminance of the liquid crystal display element 104 changes. Thus, the luminance of each pixel can be controlled by the display voltage transmitted to the pixel node Np via the data line DL and the pixel switch element 102. That is, by applying an intermediate voltage difference between the voltage difference corresponding to the maximum brightness and the voltage difference corresponding to the minimum brightness between the pixel node Np and the common electrode Nc, an intermediate brightness can be obtained. it can. Therefore, stepwise setting of the display voltage can provide stepwise brightness.

  On the lower substrate (not shown) provided with the liquid crystal display unit 100, an upper substrate (not shown) provided with a black matrix and a color filter (and a common electrode depending on the liquid crystal display mode) is provided. A liquid crystal (not shown) is sandwiched between the substrate and the lower substrate.

  A driving circuit for supplying a signal for driving the liquid crystal display unit 100 is provided outside the liquid crystal display unit 100 having the above-described structure. The drive circuit includes a gate line drive circuit 200 and a source driver 300. Furthermore, an abnormality detection circuit unit for detecting an abnormality in a gate signal which is a scanning signal is provided, and the abnormality detection circuit unit is configured of a scanning signal abnormality detection circuit 400 and an abnormality determination circuit 800. Further, a timing controller 600 for controlling the gate line drive circuit 200, the source driver 300, and the abnormality detection circuit unit, a voltage generation circuit 700 for supplying a potential to the gate line drive circuit 200, the source driver 300, and the abnormality detection circuit unit. Equipped with

  First, the timing controller 600 receives an external control signal including an image signal from an external graphic controller (not shown), a vertical synchronization signal which is a frame distinction signal, a horizontal synchronization signal, and an external clock signal, and receives a gate line. It generates and outputs control signals for controlling the operation of the drive circuit 200 and the source driver 300. The control signal is level shifted through the level shift circuit as necessary.

  The voltage generation circuit 700 generates various drive voltages required to drive the display device. A voltage generation unit (not shown) in the voltage generation circuit 700 generates a source driver power supply, a gate high voltage and a gate low voltage, and a common voltage, and further generates a voltage necessary for scanning signal abnormality detection. The voltage generation circuit 700 applies the gate high voltage and the gate low voltage to the gate line driving circuit 200 and supplies data line output circuit power to the source driver 300. Here, the data line output circuit power source is used as a basic voltage for generating a gray scale voltage (gray scale signal) for driving the liquid crystal.

The source driver 300, control signals and pixel data signals of the timing controller 600 and generates a tone signal using the data line output circuit power supply voltage generation circuit 700, the gradation signal of each data line DL ₁ through DL, _Apply to _m . That is, the source driver 300 converts the digital pixel data signal input to the display device into an analog grayscale signal using the data line output circuit power supply. Then, the source driver 300 supplies the converted grayscale signal to the plurality of data lines DL _{1 to} DL _m . The source driver 300 generally uses an integrated circuit (IC) compatible with a mounting method called COG (Chip On Glass).

  The timing controller 600 generates a vertical synchronization start signal (hereinafter referred to as a “start signal”) STV and a drive clock signal, and supplies the vertical synchronization start signal STV and a drive clock signal to the gate line drive circuit 200. At this time, the driving clock signal includes the gated clock signal CKV and / or the inverted gated clock signal CKVB. The following description is based on the case where both the gate clock signal CKV and the inverted gate clock signal CKVB are used as the drive clock signal.

The gate line driving circuit 200 applies the gate high signal VGH and the gate low signal VGL to the plurality of gate lines GL _{1 to} GL _n based on the start signal STV, the gate clock signal CKV, and the inverted gate clock signal CKVB. The gate high signal VGH is sequentially supplied to the plurality of gate lines GL _{1 to} GL _n . The gate high signal VGH is a single pulse signal. The gate high signal VGH is supplied to the gate lines GL _{1 to} GL _n in one horizontal clock cycle (1 H). At this time, the gate high signal VGH is supplied to the gate lines GL _{1 to} GL _n during a logic high period of the gate clock signal CKV or the inverted gate clock signal CKVB. As a result, the pixel switch elements 102 connected to the gate lines GL _{1 to} GL _n are turned on to display an image.

The scanning signal abnormality detection circuit 400 shifts the start signal STV input to the first stage by inputting sequentially supplied gate signals GLs _{1 to} GLs _n through the plurality of gate lines GL _{1 to} GL _n . . When the gate signals GLs _{1 to} GLs _n are sequentially supplied, the shifted pulses are sent to the abnormality determination circuit 800. In the following, for the convenience of description, each of the gate signals GLs ₁ , GLs ₂ ... GLs _n will be collectively referred to as “gate signal GLs”.

  The abnormality determination circuit 800 latches the shift pulse output from the scanning signal abnormality detection circuit based on the data latch signal LAT output from the timing controller 600 at a predetermined timing. Based on the latch data output, the external device (not shown) which has input the latch data determines whether there is an abnormality or not.

FIG. 2 is a diagram showing the configuration of the gate line drive circuit 200 according to the first embodiment. (A) of FIG. 3 is a diagram showing timing of the gate line driving circuit 200 according to the first embodiment. In FIG. 2, gate line drive circuit 200 includes a shift register circuit formed of a plurality of unit shift register circuits SR ₁ , SR ₂ , SR ₃ , SR ₄ ... SR _n connected in cascade (cascade connection). (For convenience of description, each of the shift register circuits SR ₁ , SR _2, SR ₃ , SR ₄ ... SR _n is generically referred to as “a unit shift register circuit SR”). The unit shift register circuit SR is provided for each pixel line, that is, for each gate line GL.

  Also, two-phase clock signals CKV and CKVB having different phases (the activation periods do not overlap) shown in FIGS. 2 and 3A are input to the unit shift register circuit SR of the gate line driving circuit 200. The clock signals CKV and CKVB are controlled by the timing controller 600 so as to be alternately activated at timings synchronized with the scanning cycle of the display device.

As shown in FIG. 2, each unit shift register circuit SR has an input terminal IN, an output terminal OUT, a clock terminal CK, and a reset terminal RST. One of the clock signals CKV and CKVB is supplied to the clock terminal CK of each unit shift register circuit SR. Specifically, the clock signal CKV is supplied to the unit shift register circuits SR ₁ , SR ₃ , SR ₅ ... SR _{n -1} of the odd numbered stages, and the clock signal CKVB is applied to the unit shift register circuits SR ₂ and SRd of the even numbered stages. ₄ , SR ₆ ... SR _n are supplied. In the example of FIG. 2 n-th stage (hereinafter, referred to the stage with the stage) is the last stage is a unit shift register SR _n is even-numbered, the unit shift register circuit SR _n, the clock signal CKVB It is supplied. Also, more next stage unit shift register SR _n of the final stage, the dummy stage SRD is connected a dummy shift register circuit connected to the gate line GL _d dummy without driving the pixel. The unit shift register SR ₁ to SR _n for driving the gate lines except for the dummy stage SRD, also referred to as "gate line drive stage".

Signal start signal STV for starting a shift operation of the input to the first stage shift register SR ₁ of the unit shift register SR connected in cascade to the gate line driving circuit 200. As illustrated in FIG. 3A, in the present embodiment, the start signal STV is a signal that is activated (becomes H level) at a timing corresponding to the beginning of each frame period of the image signal.

Start signal STV is input to the input terminal IN of the unit shift register SR ₁ is a first stage (first stage). In each unit shift register circuit SR of the second and subsequent stages, the input terminal IN is connected to the output terminal OUT of the unit shift register circuit SR of the preceding stage.

The reset terminal RST of each unit shift register circuit SR is connected to the output terminal OUT of the unit shift register circuit SR of the next stage. However, the reset terminal RST of the unit shift register SR _n of the last stage, is connected to the output terminal of the dummy stage SRD. The start signal STV is input to the RST terminal of the dummy stage SRD.

  That is, the output signal G output from the output terminal OUT of each unit shift register circuit SR is supplied to the corresponding gate line GL as a vertical (or horizontal) scan pulse, and the input terminal IN of its own next stage and It is supplied to the reset terminal RST of its own previous stage.

In the gate line drive circuit 200 of FIG. 2, each of the unit shift register circuits SR outputs a signal (the start signal STV or an output signal of its own preceding stage) input to the input terminal IN in synchronization with the clock signals CKV and CKVB. While shifting in time, the signal is transmitted to the corresponding gate line GL and the unit shift register SR of the subsequent stage of itself. As a result, the series of unit shift register circuits SR function as a so-called gate line driving unit that sequentially activates the gate lines GL at timing based on a predetermined scanning cycle. The output timing of each stage of the gate line drive circuit 200 is shown in FIG. 3A as the gate signals GLs _{1 to} GLs _n .

  Various circuits can be applied to the specific circuit of the gate line driving circuit 200 according to this embodiment.

FIG. 4 is a diagram showing the configuration of the scanning signal abnormality detection circuit 400 according to the first embodiment. (B) of FIG. 3 is a diagram showing the timing of the scanning signal abnormality detection circuit 400 according to the first embodiment. Scanning signal abnormality detection circuit 400 includes a shift register circuit configured of a plurality of unit shift register circuits SFD ₁ , SFD ₂ , SFD ₃ , SFD ₄ ... SFD _n connected in cascade (cascade connection) (Explanation For the sake of convenience, each of the shift register circuits SFD ₁ , SFD ₂ ... SFD _n is generically referred to as “a unit shift register circuit SFD”). The unit shift register circuit SFD is provided for each pixel line, that is, for each gate line GL.

  Further, the gate signal GLs (gate high signal VGH or gate low signal VGL) is input to the unit shift register circuit SFD of the scanning signal abnormality detection circuit 400 via the gate line GL shown in FIG.

Each unit shift register circuit SFD has an input terminal IN, an output terminal OUT, a gate signal input terminal GP, and a reset terminal RST. As shown in FIG. 4, gate signals GLs _{1 to} GLs _n (gate high signal VGH or gate low signal VGL) are sequentially supplied to the gate signal input terminal GP and the reset terminal RST of each unit shift register circuit SFD. Specifically, in the first stage SFD ₁ in FIG. 4, is supplied gate signals GLs ₁ to the gate signal input terminal GP, gate signal GLs ₂ is supplied to the reset terminal RST. In the second stage SFD _2, is supplied gate signals GLs ₂ to the gate signal input terminal GP, the gate signal GLs ₃ is supplied to the reset terminal RST. In the third stage SFD _3, is supplied gate signals GLs ₃ to the gate signal input terminal GP, gate signal GLs ₄ is supplied to the reset terminal RST. In the example of FIG. 4, the last stage the n-th stage is the gate signal GLs _n to the gate signal input terminal GP unit shift register SFD _n of (n-th stage) is supplied, a dummy gate signal to the reset terminal RST GLsd Is supplied.

  A start signal STV for causing the scanning signal abnormality detection circuit 400 to start the signal shift operation is input to the first stage of the unit shift register circuit SFD connected in cascade. In the present embodiment, the start signal STV is a signal activated (becomes H level) at a timing corresponding to the beginning of each frame period of the image signal.

  The start signal STV is input to the input terminal IN of the unit shift register circuit SFD1 which is the first stage (first stage). In each unit shift register circuit SFD in the second and subsequent stages, the input terminal IN is connected to the output terminal OUT of the unit shift register circuit SFD in the previous stage.

In the scanning signal abnormality detection circuit 400 of FIG. 4, each of the unit shift register SFD, in synchronization with the gate signal GLs, the signal inputted to the input terminal IN (start signal STV or its preceding stage of the output signal FD ₁ ~ It transmits to the unit shift register circuit SFD of the latter stage of self, shifting FD _n-1 ) in time.

  FIG. 5 is a diagram showing a specific circuit configuration of the unit shift register circuit SFD of the scanning signal abnormality detection circuit 400 according to the present embodiment.

  In scan signal abnormality detection circuit 400, the configurations of each cascaded unit shift register circuit SFD are substantially the same, and therefore, only the configuration of one unit shift register circuit SFD will be representatively described below. . The transistors constituting the unit shift register circuit SFD are all field effect transistors formed of oxide semiconductors of the same conductivity type, and in the present embodiment, they are all N-type TFTs (thin film transistors).

  As shown in FIG. 5, in the unit shift register circuit SFD, the low potential side power supply potential Vss is supplied in addition to the input terminal IN, the output terminal OUT, the gate signal input terminal GP and the reset terminal RST shown in FIG. It has a power supply terminal S1. In the following description, the low potential side power supply potential Vss is the reference potential of the circuit, but in actual use, the reference potential is set based on the gate low voltage VGL. For example, the low potential side power supply potential is the same as the gate low voltage VGL- It is set as 6V and so on.

  The output stage of the unit shift register circuit SFD is composed of a transistor Q1 (first transistor) connected between the output terminal OUT and the gate signal input terminal GP. Hereinafter, the gate node N1 (first node) of the transistor Q1 constituting the output stage of the unit shift register circuit SFD and the gate node N2 (second node) of the transistor Q3 are defined.

  The transistor Q2 is connected between the node N1 and the input terminal IN, the gate electrode is connected to the input terminal IN, and the transistor Q2 is diode-connected. A transistor Q3 is connected between the node N1 and the first power supply terminal S1. The gate electrode of the transistor Q3 is connected to the reset terminal RST.

The specific operation of the unit shift register circuit SFD of FIG. 5 will be described. Since the operation of each unit shift register SFD constituting the scanning signal abnormality detection circuit 400 is the same: essentially, in the n unit shift register circuit SFD ₁ ～SFD _n shown in FIG. 4, one The operation of one unit shift register circuit SFD will be described as a representative. For simplicity, the input gate signal _{GLs n-1} to the gate signal input terminal GP unit shift register _{SFD n-1} shown in FIG. 5, the described as the gate signal GLs _n is input to the reset terminal RST Do. The unit shift register circuit SFD _n-1 in FIG. 4 corresponds to this. The Figure 5 as shown in, the unit shift register circuits _{SFD n-1} output terminal an output signal _{FD n-1} to be output to OUT, the output signal _{FD n-2} of the single shift register circuit _{SFD n-2} of the preceding stage Define as

First, it is assumed that node N1 of unit shift register circuit SFD _n-1 shown in FIG. 5 is at L (Low) level (Vss) and node N2 is at L (Low) level (Vss) (hereinafter, this state is Called "Reset State"). Further, it is assumed that the gate signal input terminal GP (gate signal GLs _n-1 ), the reset terminal RST (gate signal GLs _n ), and the input terminal IN (output signal FD _{n-2 of the} previous stage) are all at the L level. In the reset state, since the transistor Q1 is off (shut off state), the output terminal OUT (output signal FD _n-1 ) is in the previous frame regardless of the level of the gate signal input terminal GP (gate signal GLs _n-1 ). It is maintained at L level, which is the state of

From that state, when the output signal FD _n-2 of the unit shift register circuit SFD _n-2 of the previous stage becomes H level (gate high signal VGH), that unit shift register circuit SFD _n-1 is also input to the input terminal IN. The transistor Q2 is turned on. At this time, since the node N2 is at L level, the transistor Q3 is off, and the level of the node N1 rises. Since the transistor Q2 is diode-connected, the level of the node 1 becomes VGH-Vth (Vth: threshold voltage of transistor).

As described above, in the state where the node N1 is at H level and the node N2 is at L level (hereinafter, this state is referred to as “set state”), the transistor Q1 is turned on. Even if the output signal FDn _{-2 at the} previous stage returns to L level and the transistor Q2 is turned off, the node N1 is in a floating state, and this set state is maintained thereafter.

In the set state, since the transistor Q1 is on, when the gate signal GLs _{n-1 of} the gate signal input terminal GP becomes H level (gate high signal VGH), the level of the output terminal OUT rises. At this time, the level of the node N1 is boosted by a specific voltage (hereinafter referred to as “step-up amount ΔV”) by capacitive coupling by the gate-channel capacitance (gate capacitance) of the transistor Q1. Therefore, even if the level of the output terminal OUT rises, the gate-source voltage of the transistor Q1 is kept larger than the threshold voltage (Vth), and the transistor Q1 maintains a low impedance. Therefore, the level of the output signal FD _n varies following the level of the gate signal input terminal GP. In particular, when the voltage between the gate and the source of the transistor Q1 is sufficiently large, the transistor Q1 operates non-saturating, so there is no loss for the threshold voltage and the output terminal OUT has the same level as the gate signal GLs _n-1 . Therefore, while the gate signal GLs _n-1 input to the gate signal input terminal GP is at the H level, the output signal FD _n-1 is also at the H level. Thereafter, when the gate signal GLs _n-1 returns to L level, the output signal FD _n-1 also becomes L level.

Thereafter, when the gate signal GLs _n of the reset terminal RST becomes the H level, the node N1 and the transistor Q3 is turned on becomes L level, the transistor Q1 is turned off accordingly. That is, the transistor Q1 returns to the off reset state. After that, the output signal FD _n-1 maintains the L level due to the parasitic capacitance.

  In summary, in the unit shift resister circuit SFD, while the signal (start pulse) is not input to the input terminal IN, the unit shift resister SFD is in the reset state, and the output terminal OUT is maintained at L level (Vss) from the previous frame. . Then, when a signal is input to the input terminal IN, the node N1 is charged to the H level (VGH-Vth) to be in the set state. In the set state, when the gate signal input terminal GP goes to H level, the potential of the node N1 rises by the boosting amount ΔV, and the output terminal OUT goes to H level while the gate signal input terminal GP is at H level. N1 may also be referred to as a "boost node"). After that, when a signal (gate signal of the next stage) is input to the reset terminal RST, the node N1 returns to L level (Vss), and the node N2 returns to L level (Vss), resulting in the original reset state (for this reason) Node N2 may also be referred to as a "reset node").

Thus a plurality of unit shift registers SFD that operates cascaded as shown in FIG. 4, to constitute scanning signal abnormality detection circuit 400 is input to the first stage input terminal IN of the unit shift register circuit SFD ₁ of input signal (start signal STV), as the timing chart shown in FIG. 3, gate signals _{GLs 1,} GLs 2, the output signal _FD 1 _{~FD n} unit shift register SFD at a timing synchronized with the GLs ₃ sequentially The unit shift register circuits SFD ₂ , SFD _3, ... Are sequentially transmitted while being shifted. Accordingly, the scanning signal abnormality detection circuit 400 transmits the transmitted pulse to the abnormality determination circuit 800.

  Next, an operation when an abnormality occurs in a certain gate line will be described. When a part of the gate line is disconnected and becomes open, the gate signal GLs of the gate line where the abnormality has occurred always becomes L level. Therefore, at the timing when the gate signal GLs becomes H to the gate signal input terminal GP of the unit shift register circuit SFD in the set state, the output terminal OUT does not become H level but remains L level. Therefore, unit shift register circuit SFD can not transmit H level, and abnormality determination circuit 800 outputs L level.

When a gate line is shorted with the gate high potential VGH, the gate signal GLs (GLs _n in the unit shift register circuit SFD _n-1 illustrated in FIG. 5) is always at the H level. In this case, since the input terminal RST is at the H level, the transistor Q3 is in the ON state, and the output signal of the unit shift register circuit SFD of the previous stage (FD _n in the unit shift register circuit SFD _n-1 illustrated in FIG. _{Even if} the H level (gate high signal VGH) of _-2 ) is input, the level of the node N1 does not become H. As a result, the transistor Q1 is not turned on, and the output terminal OUT is at the timing when the gate signal GLs (the unit shift register circuit SFD _n-1 illustrated in FIG. 5 is GLs _n-1 illustrated in FIG. It does not go to the H level but remains at the L level. Therefore, unit shift register circuit SFD can not transmit H level, and abnormality determination circuit 800 outputs L level.

Although the unit shift register circuit SFD _n-1 in FIG. 4 has been described as an example of the occurrence of an abnormality in the gate line, the same operation can be performed with any of the unit shift register circuits SFD _{1 to} SFD _n. In the case where abnormality occurs in at least one of lines GL _{1 to} GLd and gate signal GLs is always at L level or H level, if output terminal OUT of connected unit shift register circuit SFD is at H level Finally, the H level pulse can not be finally transmitted to the abnormality determination circuit 800.

  By using the oxide semiconductor with high field effect mobility for the scanning signal abnormality detection circuit 400, this function can be realized without increasing the frame size. In addition, by using the same manufacturing process as the display element and the gate line driver circuit on the display panel 500, an increase in manufacturing cost can be suppressed and the present function can be realized.

  In the present embodiment, the potential of the first power supply terminal S1 is set to -6 V, which is the same as the gate low voltage VGL, but may be set to a voltage (for example, -4 V) higher than the gate low voltage VGL. When the threshold voltage Vth of the oxide semiconductor is generally low, and the potential of the first power supply terminal S1 is -6 V equal to the gate low voltage VGL, Vgs (potential between gate and source) of the transistor Q3 becomes 0 V, and Ids ( This is because when the node N1 is at H level (set state), a large amount of current flows between the drain and the source, and a leak current flows through the transistor Q3, and the node N1 does not become high enough. By setting the first power supply terminal S1 potential to -4V higher than the gate low voltage VGL (-6V), Vgs (gate-source potential) of the transistor Q3 becomes -2V, and the transistor Q3 can be fully turned off it can.

<Modification>
FIG. 6 is a modification showing a specific circuit configuration of the unit shift resister circuit SFD constituting the scanning signal abnormality detection circuit 400 according to the present embodiment.

  As shown in FIG. 6, in the unit shift register circuit SFD, the low potential side power supply potential Vss is supplied in addition to the input terminal IN, the output terminal OUT, the gate signal input terminal GP and the reset terminal RST shown in FIG. A power supply terminal S1 and a second power supply terminal S2 are provided. In the following description, the low potential side power supply potential Vss is the reference potential of the circuit, but in actual use, the reference potential is set on the basis of the voltage of data written to the pixel. For example, the low potential side power supply potential is -6V And so on.

  The output stage of the unit shift register circuit SFD includes a transistor Q1 (first transistor) connected between the output terminal OUT and the gate signal input terminal GP, and a transistor connected between the output terminal OUT and the second power supply terminal S2. It is comprised by Q4 (4th transistor). Hereinafter, the gate node N1 (first node) of the transistor Q1 and the gate nodes of the transistor Q3 and the transistor Q4 constituting the output stage of the unit shift register circuit SFD are defined as a node N2 (second node).

  The transistor Q2 is connected between the node N1 and the input terminal IN, the gate electrode is connected to the input terminal IN, and the transistor Q2 is diode-connected. A transistor Q3 is connected between the node N1 and the first source terminal S1. The gate electrode of the transistor Q3 is connected to the reset terminal RST. The node N2 is connected to the reset terminal RST.

The specific operation of the unit shift register circuit SFD of FIG. 6 will be described. Since the operations of the unit shift register circuits SFD constituting the scanning signal abnormality detection circuit 400 are substantially the same, the operation of one unit shift register circuit SFD _n-1 will be representatively described. For simplicity, the gate signal _{GLs n-1} to the gate signal input terminal GP of the shift register circuit _{SFD n-1} is inputted, it will be described assuming that the gate signal GLs _n is input to the reset terminal RST. The unit shift register circuit SFD _n-1 in FIG. 3 corresponds to this. Further, an output signal output from the unit shift register circuit SFD _n-1 to the output terminal OUT is defined as FD _n-1 , and an output signal of the single shift register circuit SFD _{n-2 at} the preceding stage is defined as FD _n-2 .

First, it is assumed that the node N1 is at L (Low) level (Vss) and the node N2 is at L (Low) level (Vss) (hereinafter, this state is referred to as "reset state"). Further, it is assumed that the gate signal input terminal GP (gate signal GLs _n-1 ), the reset terminal RST (gate signal GLs _n ), and the input terminal IN (output signal FD _{n-1 of the} previous stage) are all at the L level. In the reset state, the transistor Q1 is off (shut off state) and the transistor Q4 is off (shut off state), so the output terminal OUT (output signal is output regardless of the level of the gate signal input terminal GP (gate signal GLs _n-1 ) FD _n-1 ) is maintained at L level which is the state of the previous frame.

From that state, when the output signal FD _n-2 of the unit shift register circuit SFD _n-2 of the previous stage becomes H level, that unit shift register circuit SFD _n-2 is also input to the input terminal IN, and the transistor Q2 turns on. Become. At this time, since the node N2 is at L level, the transistor Q3 is off, and the level of the node N1 rises.

As described above, in the state where the node N1 is at the H level and the node N2 is at the L level (hereinafter, this state is referred to as "set state"), the transistor Q1 is turned on and the transistor Q4 is turned off. Even if the output signal FDn _{-2 at the} previous stage returns to L level and the transistor Q2 is turned off, the node N1 is in a floating state, and this set state is maintained thereafter.

In the set state, since the transistor Q1 is on and the transistor Q4 is off, when the gate signal GLs _{n-1 of} the gate signal input terminal GP becomes H level, the level of the output terminal OUT rises. At this time, the level of the node N1 is boosted by a specific voltage (hereinafter referred to as “step-up amount ΔV”) by capacitive coupling by the gate-channel capacitance (gate capacitance) of the transistor Q1. Therefore, even if the level of the output terminal OUT rises, the gate-source voltage of the transistor Q1 is kept larger than the threshold voltage (Vth), and the transistor Q1 maintains a low impedance. Therefore, the level of the output signal FD _n-1 changes following the level of the gate signal input terminal GP. In particular, when the voltage between the gate and the source of the transistor Q1 is sufficiently large, the transistor Q1 operates non-saturating, so there is no loss for the threshold voltage and the output terminal OUT has the same level as the gate signal GLs _n-1 . Therefore, while the gate signal GLs _n-1 input to the gate signal input terminal GP is at the H level, the output signal FD _n-1 is also at the H level. Thereafter, when the gate signal GLs _n-1 returns to L level, the output signal FD _n-1 also becomes L level.

Thereafter, when the gate signal GLs _n of the reset terminal RST becomes H level, the transistor Q4 is turned ON. Along with this, the output signal FD _n-1 becomes sufficiently L level. At the same time, since the transistor Q3 is turned on, the node N1 becomes L level, and the transistor Q1 is turned off accordingly. That is, the transistor Q1 is turned off, and the transistor Q4 is reset to the on state. The output signal FD _n-1 maintains the L level due to parasitic capacitance.

  To summarize the above operation, in the unit shift resister SFD, while the signal (start signal) is not input to the input terminal IN, the unit shift resister SFD is in the reset state, and the output terminal OUT is maintained at L level (Vss) from the previous frame. Then, when a signal is input to the input terminal IN, the node N1 is charged to the H level (VDD1-Vth) to be in the set state. In the set state, when the gate signal input terminal GP goes to H level, the potential of the node N1 rises by the boosting amount ΔV, and the output terminal OUT goes to H level while the gate signal input terminal GP is at H level. Thereafter, when a signal (gate signal of the next stage) is input to the reset terminal RST, the node N1 returns to L level (Vss), and the node N2 returns to L level (Vss), and the original reset state is established.

Thus a plurality of unit shift registers SFD that operates cascaded as shown in FIG. 3, to constitute the scanning signal abnormality detection circuit 400 is input to the first stage input terminal IN of the unit shift register circuit SFD ₁ of The input signal (start signal STV) is shifted at timings synchronized with the gate signals GLs ₁ , GLs ₂ , and GLs ₃ as shown in the timing chart of FIG. 5, while unit shift register circuits SFD ₂ , SFD _3.・ ・ ・ And transmitted in order. Accordingly, the scanning signal abnormality detection circuit 400 transmits the transmitted pulse to the abnormality determination circuit 800.

In the present embodiment, the potentials of the first power supply terminal S1 and the second power supply terminal S2 are set to -6 V which is the same as the gate low voltage VGL, but may be set to a voltage (for example -4 V) higher than the gate low voltage VGL . When the threshold voltage Vth of the oxide semiconductor is generally low, and the potentials of the first power supply terminal S1 and the second power supply terminal S2 are -6 V equal to the gate low voltage VGL, Vgs (gate-source potential) of the transistor Q3 = 0 V Under this condition, many Ids (current between drain and source) flows, and when node N1 is H level (set state), a leak current flows through transistor Q3 and node N1 does not become high level sufficiently. is there. Similarly, even if the transistor Q1 is fully on, if the gate signal GLs2 of the gate signal input terminal GP becomes H level (gate high signal VGH), the level of the output terminal OUT becomes H level by the leak current of the transistor Q4. It will not be. If the potential of the first power supply terminal S1 is set to -4V higher than the gate low voltage VGL (-6V), Vgs (potential between gate and source) of the transistor Q3 and the transistor Q4 becomes -2V, and the transistor Q3 and the transistor Q4 are sufficiently It can be turned off. In this case, a slight through current flows between the second power supply terminal S2 and the gate signal VGL while the transistor Q4 is on, but there is no particular problem in operation.

  A specific circuit example of the unit shift register circuit SFD is not limited to the above embodiment, and for example, a boosting capacitance may be provided between the output terminal OUT and the node N1. Further, an output buffer circuit may be provided in parallel with the output circuit, and a signal may be output from the output buffer circuit according to the output load (FIG. 7).

  Further, the transistor Q2 may not be diode-connected, and only the gate may be connected to the input terminal IN, and the drain of the transistor Q2 may be a high potential power supply.

  The input to the reset terminal RST of the final stage may be the start signal STV. In this case, the dummy gate line GLd is formed.

  A specific circuit example of the abnormality determination circuit 800 in the present embodiment is shown in FIG. The abnormality determination circuit 800 includes a comparator 810, transfer gates 801 and 802, and inverters 803, 804, 805, and 806. When one of the transfer gates is in the ON state, the other transfer gate is in the OFF state, and the transfer gates 801 and 802 and the inverters 803 and 804 form a latch circuit (FIG. 8 in FIG. 8). Circuit part surrounded by a dashed dotted line). The inverter 805 inverts the output of the latch circuit. The comparator 810 has a function of comparing the output value of the scanning signal abnormality detection circuit with a predetermined reference voltage value Vref, converting it into a logical value according to the magnitude relationship, and outputting it. For example, when the output value of the scanning signal abnormality detection circuit is equal to or higher than the reference voltage value Vref, the comparator outputs logic "1". When the output value of the scanning signal abnormality detection circuit is less than the reference voltage value Vref, the comparator Output 0 ". The latch signal LAT is output from the timing controller 600, and is connected to the N channel transistor of the transfer gate 801 and the P channel transistor of the transfer gate 802.

  The latch signal LAT is logically inverted by the inverter 806, and the output of the inverter 806 is connected to the P channel transistor of the transfer gate 801 and the N channel transistor of the transfer gate 802.

  For setting of the reference voltage Vref, for example, when detecting only the state where the gate line potential is not completely output, the state where the gate line potential is slightly lowered is set to the reference voltage Vref at almost Low level. It should be set. When detecting a state in which the gate line potential is slightly lowered, the reference voltage Vref may be set to a level close to High. Also, even when detecting an abnormality that delays the rise / fall time of the gate line, detection is possible by appropriately setting the latch timing by the latch signal LAT, and H level is determined when normal and L level is abnormal when abnormal. It can be configured to output from the circuit 800.

  Note that, by providing two abnormality determination circuits 800 in parallel and performing data latch at different timings, for example, even when an abnormality occurs such that the scanning signal abnormality detection circuit 400 constantly outputs the H level, an abnormality occurs. It is possible to detect something.

In addition, the scanning signal abnormality detection circuit 400 may be provided with a dummy stage. When the level of the pulse to be shifted decreases in the unit shift register circuit SFD, the level of the pulse to be shifted further decreases while shifting to the next stage and to the next stage. Therefore, by providing the dummy stage in the next stage of the unit shift register circuit SFD _n , it becomes possible to more surely detect the abnormality of the gate line. In the case of providing a dummy stage in the scanning signal abnormality detection circuit, it is also necessary to increase the number of dummy stages of the gate line driving circuit.

  As described above, since the external device (not shown) constantly monitors the output level of the abnormality determination circuit 800, it is possible to easily detect a defect in the scanning signal or the drive circuit output during display operation of the electro-optical device. It becomes.

Second Embodiment
FIG. 9 is a schematic block diagram showing the configuration of the display device according to the present invention, and shows the overall configuration of the liquid crystal display device 10 as a representative example of the display device. (A) of FIG. 12 is a diagram showing timing of the gate line driving circuit 200 according to the second embodiment. Gate line driving circuit 200a, the output timing of each stage of the 200b, shown as a gate signal _GLs 1 _{~GLs n.}

The gate line drive circuit 200 includes an odd gate line drive circuit 200 a for driving the gate lines GL ₁ , GL ₃ , GL ₅ ,..., GL _n−1 in odd lines, and gate lines GL ₂ , GL ₄ , GL _6, are composed of the even gate line driving circuit 200b for driving the · · · GL _n, thereby selecting and activating gate lines GL in the order based on a predetermined scanning cycle.

The scanning signal abnormality detection circuit 400 includes an odd scanning signal abnormality detection circuit 400 a driven by the gate lines GL ₁ , GL ₃ , GL ₅ ,... GL _n−1 in odd rows, and gate lines GL ₂ , GL in even rows. ₄ , GL ₆ ,..., And even-numbered scan signal abnormality detection circuit 400 b driven by GL _n, and shifts the start pulse based on a predetermined scanning cycle.

FIG. 10 is a diagram showing the configuration of a gate line drive circuit according to the present invention. As described above, the gate line drive circuit is composed of the odd gate line drive circuit 200a and the even gate line drive circuit 200b. Odd gate line driving circuit 200a, the gate lines in the odd-numbered rows _{GL 1, GL 3, GL 5} , ··· GL unit shift register _SR 1 _{of n-1} and respectively _{driving, SR 3, SR 5, ···} SR _n-1 is formed by cascade connection (cascade connection). Even gate line driving circuit 200b, the gate line _GL 2 of the even _{row, GL 4, GL 6, ···} GL n unit shift register respectively driving circuits _{SR 2, SR 4, SR 6} , is · · · SR _n It consists of cascade connection (cascade connection). That is, in each of the odd gate line drive circuit 200a and the even gate line drive circuit 200b, the “previous stage” corresponds to the unit shift register circuit SR _k− of the second row before “ _k ” in the unit shift register circuit _{SRk. 2} and “next stage” is a unit shift register circuit SR _{k + 2} after two rows (k is a natural number of 1 to n).

The odd-numbered gate line drive circuit 200a according to the present embodiment is a dummy unit shift connected to a dummy gate line GLd ₁ which does not drive a pixel in a stage subsequent to the unit shift register circuit SR _n-1 which is the last stage. Register circuit SRD ₁ (hereinafter referred to as “first dummy stage”) is provided. On the other hand, the even gate line driving circuit 200b, the last stage in which the unit shift register SRD 2 _(hereinafter "second dummy stage") is provided, likewise connected to the gate line GLd ₂ dummy without driving the pixel There is. Basically, the first and second dummy stages SRD ₁ and SRD ₂ also have the same circuit configuration as the other unit shift register circuits SR.

  The timing controller 600 shown in FIG. 9 generates clock signals CKVO and CKVOB of two phases different in phase to the unit shift register SR of the odd gate line drive circuit 200a, and even clocks the clock signals CKVE and CKVEB of two phases different in phase to each other. It is supplied to the unit shift register circuit SR of the gate line drive circuit 200b. The clock signals CKVO and CKVOB and the clock signals CKVE and CKVEB do not overlap each other, and the CKVO, CKVOB, CKVO, CKVOB,. It is controlled to be repeatedly activated in the order of CKVEB...

  The configuration of each unit shift register circuit SR is the same as that of the first embodiment described above. One of the clock signals CKVO and CKVOB output from the timing controller 600 is supplied to the clock terminal CK of the unit shift register circuit SR of the odd gate line drive circuit 200a. One of the clock signals CKVE and CKVEB output from the timing controller 600 is supplied to the clock terminal CK of the unit shift register circuit SR of the even gate line drive circuit 200b.

Specifically, the clock signal CKVO drives the unit shift register circuits SR ₁ , SR ₅ , SR ₉ ... For driving the gate line GL _4x-3 of the [4x-3] th row (x is a natural number, hereinafter the same).・ Supplied to The clock signal CKVOB is supplied to unit shift register circuits SR ₃ , SR ₇ , SR ₁₁ ... For driving the gate line GL _4x-1 on the [4x-1] th row (x is a natural number, hereinafter the same). . The clock signal CKVE is supplied to unit shift register circuits SR ₂ , SR ₆ , SR ₁₀ ... For driving the gate line GL _4x-2 of the [4x-2] th row (x is a natural number, hereinafter the same). . The clock signal CKVEB is supplied to unit shift register circuits SR ₄ , SR ₈ , SR ₁₂ ... Which drive the gate line GL _4x-1 of the [4x] th row (x is a natural number, hereinafter the same). Also, x = 4 / n.

Since clock signals CKVO and CKVOB and clock signals CKVE and CKVEB are repeatedly activated in this order, clock terminals of shift register circuits SR ₁ , SR ₂ , SR ₃ , SR ₄ ... Are activated in that order. It will be.

Note that since the number of scanning lines in a general display device is a multiple of four, in the shift register circuit controlled by two sets of two-phase clock signals CKVO, CKVOB, CKVE, and CKVEB, the nth row from the end is the second row. The clock signal supplied to the clock terminal CK of the unit shift register circuit SR _n-1 (the final stage of the odd gate line drive circuit 200a) of the -1st row is supplied with CKVOB, and the unit of the nth row which is the final row. A clock signal CKVEB is supplied to the clock terminal CK of the shift register circuit SR _n (the final stage of the even gate line drive circuit 200 b).

The odd-stage start signal STVO is input to the input terminal IN of the first-row unit shift register circuit SR ₁ (the first stage of the odd-numbered gate line drive circuit 200a), and the second-row unit shift register circuit SR 1 is input. _A start signal STVE for an even-numbered stage is input to an input terminal IN of (the first stage of the even-numbered gate line drive circuit 200b). In the present embodiment, both start signals STVO and STVE are signals activated (become H level) at a timing corresponding to the beginning of each frame period of the image signal, but the start signal STVE for even stages is for odd stages The phase is delayed from the start signal STVO by one horizontal period (1 H), that is, by a scanning period of one pixel line.

In unit shift register SR _k of the third line onward, the unit shift register SR of the input terminal IN 2 rows before that (one stage before the odd gate line driver circuit 200a within or even gate line driver circuit 200b) It is connected to the output terminal OUT of _k-2 .

The same applies to the first and second dummy stage _SRD 1, SRD _2, the first input terminal IN of the dummy stage SRD _1, the output signal GL of the unit shift register _{SR n-1} corresponding to the second line before _n-1 is input. Also in the second input terminal IN of the dummy stage SRD _2, the output signal GLs _n unit shift register SR _n corresponding to the two rows before is input.

The reset terminal RST of each unit shift register circuit SR _k is connected to the output terminal OUT of the unit shift register circuit SR _{k + 2} after two rows (one stage after in the odd gate line drive circuit 200 a or in the even gate line drive circuit 200 b). Connected

The reset terminal RST of the unit shift register circuit SR _n-1 (the last stage of the odd gate line drive circuit 200a) in the second row from the end is connected to the output terminal OUT of the first dummy stage SRD ₁ corresponding to the second row later. Ru. The reset terminal RST of the last row unit shift register SR _n (the final stage of the even gate line driving circuit 200b) is connected to the second output terminal OUT of the dummy stage SRD _2.

Note that the first reset terminal RST of the dummy stage SRD _1, a start pulse STVO the odd stage is entered. The reset terminal RST of the second dummy stage SRD _2, a start pulse STVE for even stages are input.

As described above, the output signal GLs _k output from the output terminal OUT of the unit shift register SR _k is supplied respectively as a selection signal (a vertical scanning pulse) to the corresponding gate line GL _k, 2 It is also supplied to the input terminal IN of the unit shift register circuit SR _{k + 2} after the row and the reset terminal RST of the unit shift register circuit SR _k-2 two rows before.

FIG. 11 is a diagram showing the configuration of a scanning signal abnormality detection circuit 400 according to the present invention. (B) of FIG. 12 is a diagram showing the timing of the scanning signal abnormality detection circuit 400 according to the second embodiment. As described above, the scanning signal abnormality detection circuit 400 includes the odd scanning signal abnormality detection circuit 400a and the even scanning signal abnormality detection circuit 400b. Odd-number scan signal abnormality detecting circuit 400a, the gate lines in the odd-numbered rows _{GL 1, GL 3, GL 5} , the unit shift register circuit _SD 1 driven from _{···, SFD 3, SFD 5,} ··· are connected in cascade (Cascade Connection) is made. In the even scan signal abnormality detection circuit 400b, unit shift register circuits SFD ₂ , SFD ₄ , SFD ₆ ,... Driven from the gate lines GL ₂ , GL ₄ , GL ₆ ,. Connection) is made. That is, in each of the odd-number scan signal abnormality detecting circuit 400a and the even-number scan signal abnormality detection circuit 400b, as viewed from the unit shift register SFD _k of the _k-th stage, "front" is 2 lines before the unit shift register SFD _k-2 , and the "next stage" is a unit shift register circuit SFD _{k + 2} after two rows (k is a natural number of 1 to n).

Each unit shift register circuit SFD has an input terminal IN, an output terminal OUT, a gate signal input terminal GP, and a reset terminal RST. As shown in FIG. 9, gate signal GLs _2y-1 is sequentially supplied to gate signal input terminal GP and reset terminal RST of each unit shift register circuit SFD in odd scan signal abnormality detection circuit 400a (where y is 1). The signal level is a gate high signal VGH or a gate low signal VGL.). Specifically, in the first stage SFD ₁ odd-number scan signal abnormality detecting circuit 400a, it is supplied the gate signal GLs ₁ to the gate signal input terminal GP, the gate signal GLs ₃ is supplied to the reset terminal RST. In the second stage SFD ₃ of the odd scan signal abnormality detection circuit 400 a, the gate signal GLs ₃ is supplied to the gate signal input terminal GP, and the gate signal GLs ₅ is supplied to the reset terminal RST. In the third stage SFD ₅ odd-number scan signal abnormality detecting circuit 400a, is supplied the gate signal GLs ₅ to the gate signal input terminal GP, gate signal GLs ₇ is supplied to the reset terminal RST. In the example of FIG. 9, the gate line GLs is connected to the gate signal input terminal GP of the unit shift register circuit SFD _n-1 of the _n-1st stage (the n / 2th stage of the odd scan signal abnormality detection circuit 400a) which is the last stage. _{The n−1} signal is supplied, and the dummy gate signal GLsd ₁ is supplied to the reset terminal RST.

Gate signal GLs 2 _y is sequentially supplied to gate signal input terminal GP and reset terminal RST of each unit shift register circuit SFD in even scan signal abnormality detection circuit 400 b (where y is a natural number of 1 to n / 2). Also, the signal level is the gate high signal VGH or the gate low signal VGL.). Also, the signal level is the gate high signal VGH or the gate low signal VGL). Specifically, in the first stage SFD ₂ even-number scan signal abnormality detection circuit 400b, it is supplied gate signals GLs ₂ to the gate signal input terminal GP, gate signal GLs ₄ is supplied to the reset terminal RST. In the second stage SFD ₄ of the even scanning signal abnormality detection circuit 400 b, the gate signal GLs ₄ is supplied to the gate signal input terminal GP, and the gate signal GLs ₆ is supplied to the reset terminal RST. In the third stage SFD ₆ of the even scanning signal abnormality detection circuit 400 b, the gate signal GLs ₆ is supplied to the gate signal input terminal GP, and the gate signal GLs ₈ is supplied to the reset terminal RST. In the example of FIG. 9, the gate line GLs _n signal is applied to the gate signal input terminal GP of the unit shift register circuit SFD _n of the nth stage (the n / 2 th stage of the even scan signal abnormality detection circuit 400b) which is the last stage. is supplied, the dummy gate signal GLsd ₂ is supplied to the reset terminal RST.

  The start pulse STV for causing the scanning signal abnormality detection circuit 400 to start the signal shift operation is input to the first stage of the unit shift register circuit SFD connected in cascade. In the present embodiment, the start signal STV is a signal activated (becomes H level) at a timing corresponding to the beginning of each frame period of the image signal.

Odd-start signal STVO is input to the input terminal IN of the odd-number scan signal abnormality detection circuit first stage 400a unit shift register circuit SFD ₁ is (first stage). In each unit shift register circuit SFD in the second and subsequent stages, the input terminal IN is connected to the output terminal OUT of the unit shift register circuit SFD in the previous stage.

The even-stage start signal STVE is input to the input terminal IN of the unit shift register circuit SFD ₂ which is the first stage (first stage) of the even-number scan signal abnormality detection circuit 400b. In each unit shift register circuit SFD in the second and subsequent stages, the input terminal IN is connected to the output terminal OUT of the unit shift register circuit SFD in the previous stage.

  In the scanning signal abnormality detection circuit 400 of FIG. 9, each of the unit shift register circuits SFD synchronizes with the gate line GL signal to generate the signal (the start signal STV or the output signal of its own preceding stage) input to the input terminal IN. While shifting in time, the signal is transmitted to the unit shift register circuit SFD of the subsequent stage of itself.

A plurality of unit shift registers SFD which operates so cascade connected as shown in FIG. 9, the scanning signal abnormality to constitute a detection circuit 400, the input terminal IN of the unit of the first-stage shift register circuit SFD ₁ and SFD ₂ The input signals (start signals STVO and STVE) input to the unit shift register circuit SFD are sequentially transmitted through the unit shift register circuit SFD while being shifted at a timing synchronized with the gate signal GLs as shown in the timing chart of FIG. Accordingly, the odd scan signal abnormality detection circuit 400a transmits the transmitted pulse to the odd abnormality judgment circuit 800a, and the even scan signal abnormality detection circuit 400b transmits the transmitted pulse to the even abnormality judgment circuit 800b.

  As described above, by constantly monitoring the output levels of the odd abnormality judgment circuit 800a and the even abnormality judgment circuit 800b, it is possible to easily detect a defect in the scanning signal or its drive circuit during display operation of the electro-optical device. It becomes. Further, by arranging the gate line drive circuit and the scanning signal abnormality detection circuit separately on the left and right of the display portion, even in the case of a display device with a narrow frame, the central position of the display portion becomes easy.

The inputs to the reset terminal RST of the final stage may be the start signals STVO and STVE. In this case, the dummy gate lines GLd ₁ and GLd ₂ become unnecessary.

  In addition, the scanning signal abnormality detection circuit 400 may be provided with a dummy stage. When the level of the pulse to be shifted decreases in the unit shift register circuit SFD, the level of the pulse to be shifted further decreases while shifting to the next stage and to the next stage. Therefore, by providing the dummy stage, it is possible to detect the abnormality of the gate line more reliably. Needless to say, in the case of providing a dummy stage in the scanning signal abnormality detection circuit 400, it is also necessary to increase the number of dummy stages of the gate line drive circuit.

  Further, in the drive timing (FIG. 12) in the present embodiment, the adjacent gate lines overlap, but it is not necessary to overlap as shown in FIG.

  The gate line drive circuit 200 can also be applied to an integrated circuit (gate driver IC) employing a crystalline silicon transistor. In this case, since the general gate driver IC does not generate a dummy signal, the start signal STV is input to the RST terminal of the final stage of the abnormality detection circuit 400. Since the gate driver IC normally has a low output voltage level, a level shifter is provided to raise the H level of the start signal.

  The anomaly detection circuit 400 can apply an amorphous silicon TFT if the frame size is not particularly a problem. It is also possible to form an equivalent circuit by an integrated circuit (IC) employing a crystalline silicon transistor. When using an IC, a level shift circuit is applied as needed.

  In the first and second embodiments described above, the present invention is applied to a liquid crystal display device adopting a liquid crystal layer as an electro-optical layer as an example of a display device, and the contents thereof are described. The present invention is also applicable to a display device that employs electroluminescence (EL), organic EL, plasma display, electronic paper, or the like as an electro-optical layer that converts light into luminance. Furthermore, the present invention can be widely applied to an electro-optical device such as an imaging device (image sensor) which converts light intensity into an electric signal.

DESCRIPTION OF SYMBOLS 10 liquid crystal display device 100 liquid crystal display part 101 pixel 102 pixel switch element 103 capacitor 104 liquid crystal display element 200, 200a, 200b gate line drive circuit 300 source driver 400, 400a, 400b scanning signal abnormality detection circuit 500 display panel 600 timing controller 700 voltage Generation circuit 800, 800a, 800b Abnormality judgment circuit

Claims (7)

A TFT substrate provided with a display area in which scanning signal lines and image signal lines are arranged in a matrix, and thin film transistors and pixel electrodes are formed at intersections of these signal lines, and an electro-optical layer corresponding to the display area In the electro-optical device
A scanning signal line drive circuit for driving the scanning signal line and a scanning signal abnormality detection circuit are formed in the peripheral portion of the display area on the TFT substrate.
The scan signal abnormality detection circuit is disposed on the opposite side of the display area with respect to the scan signal line drive circuit.
The scanning signal abnormality detection circuit is driven by a scanning signal output from the scanning signal line drive circuit to the scanning signal line,
The electro-optical device according to claim 1, wherein the scanning signal is input to the scanning signal abnormality detection circuit via the scanning signal line. And an abnormality determination circuit that receives an output of the scanning signal abnormality detection circuit and detects an abnormality of the scanning signal line,
2. The electro-optical device according to claim 1, wherein the abnormality determination circuit comprises a comparator circuit and a latch circuit. The scanning signal abnormality detection circuit is composed of a plurality of unit shift registers connected in cascade.
The unit shift register inputs the scan signal of the scan signal line corresponding to the stage and outputs the scan signal to the unit shift register of the next stage.
Set at the output of the unit shift register of the previous stage,
3. The electro-optical device according to claim 1, wherein the output of the unit shift register of the next stage is input and reset. The scanning signal abnormality detection circuit is composed of a plurality of unit shift registers connected in cascade.
The unit shift register includes a first transistor that receives the scan signal of the scan signal line corresponding to the stage and outputs the scan signal to the next stage.
A second transistor for supplying an output signal of the unit shift register of the previous stage to a first node to which the control electrode of the first transistor is connected;
3. The electro-optical device according to claim 1, further comprising a third transistor that inputs the output signal of the unit shift register of the next stage to the control electrode to discharge the first node. The scanning signal line drive circuit is composed of a plurality of unit shift registers connected in cascade and formed of a plurality of transistors.
5. The electro-optical device according to claim 4, wherein the plurality of transistors are manufactured in the same manufacturing process as the first to third transistors.   The electro-optical device according to claim 4, wherein the channels of the first to third transistors are formed of an oxide semiconductor.   3. The electro-optical device according to claim 1, wherein at least one of the scanning signal line drive circuit and the scanning signal abnormality detection circuit is an integrated circuit employing a crystalline silicon transistor.