JPH11326422A - Drive circuit for display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent drop of a production yield caused by a defect inside a drive circuit for a signal line and a scanning line, and automate defect detection for a shift register and a buffer circuit inside the drive circuit. SOLUTION: A display unit is provided with an external drive circuit 2 for drive-controlling a scanning line driving circuit 1. The circuit 1 has a shift register 4 connected with plural latch circuits 3 and switching circuits 8 in series, and an inspection circuit 6 for detecting a failure of the respective latch circuits 3. The external drive circuit 2 has a memory 14 for storing an inspection result resulting from the inspection circuit 6. Data stored in the memory 14 are synchronized with an operation clock of the register to be read out in order, so as to be supplied to the switching circuit 8. The circuit 8 selects the latch circuit 3 of no defect in response to the data read out from the memory 14. A scanning line is normally driven thereby to enhance a production yield even when a part of the latch circuits 3 inside the shift register 4 gets defective.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for automatically detecting a failure of a shift register or a buffer circuit in a drive circuit for driving a signal line or a scanning line and replacing the failed part.

[0002]

2. Description of the Related Art Thin and lightweight display devices are widely used in word processors, personal computers, portable televisions and the like. In particular, liquid crystal display devices are being actively developed because they are thin, lightweight, and easy to reduce power consumption, and high-resolution, large-screen size liquid crystal display devices are available at relatively low prices. It has become

[0003] Among liquid crystal display devices, an active matrix type liquid crystal display device in which a TFT (Thin Film Transistor) is arranged near each intersection of a signal line and a scanning line has excellent color development and little afterimage. It is thought to be mainstream.

In a conventional active matrix type liquid crystal display device, a driving circuit for driving signal lines and scanning lines is formed on a substrate different from a pixel array substrate on which signal lines and scanning lines are arranged. The entire device could not be downsized.

For this reason, development of a manufacturing process for integrally forming a drive circuit on a pixel array substrate has been actively conducted.

[0006]

A driving circuit for driving signal lines and scanning lines on a pixel array substrate includes a shift register and a buffer circuit. The shift register includes flip-flops for the number of signal lines and scanning lines therein, and the buffer circuits are provided for the number of signal lines and scanning lines.

Recently, the resolution of the liquid crystal display device has been increasing, and accordingly, the number of stages of the shift register has increased and the number of buffer circuits has also increased. Therefore, there is a high possibility that a failure occurs in a flip-flop or a transistor included in a buffer circuit in the shift register.

In particular, when a signal line driving circuit and a scanning line driving circuit are integrally formed on a pixel array substrate, TFTs and the like constituting these driving circuits must be finely processed. Such failures are likely to occur.

In order to cope with such a failure, for example, a redundant circuit is formed on a pixel array substrate, and when a failure occurs in a signal line driving circuit or the like, it is considered that a failure portion is switched to the redundant circuit. Can be

However, in order to replace a failed part with a redundant circuit, an inspection device or the like is connected to the pixel array substrate in advance, and
An inspection signal is supplied from the outside to the pixel array substrate to check whether or not a desired output signal can be obtained. Based on the inspection result, switching to a redundant circuit must be performed, and the inspection procedure is complicated. There is a problem that the inspection takes time.

The present invention has been made in view of such a point, and an object of the present invention is to prevent a reduction in manufacturing yield due to a failure of a shift register, a buffer circuit, or the like in a signal line or scanning line driving circuit. Another object of the present invention is to provide a display device capable of automating defect detection and repair of a shift register, a buffer circuit, and the like.

[0012]

To solve the above-mentioned problems, a first aspect of the present invention is to provide a timing signal generating section configured by arranging a plurality of latch circuits arranged in parallel with each other, A switching circuit disposed between each of the timing signal generators, for selecting one of the outputs of the plurality of latch circuits and outputting the selected output to each of the latch circuits of the next-stage timing signal generation circuit; A test circuit that differentiates the output of the switching circuit and outputs the output to a test circuit bus, and an external circuit that samples a differential signal on the test circuit bus based on a predetermined clock signal. The switching circuit generates a control signal for selecting a latch circuit in accordance with the level of the sampled signal, and counts the clock signal to correspond to the control signal. And outputs to the switch circuit.

According to a second aspect of the present invention, there is provided a timing signal generating section having a plurality of latch circuits arranged in cascade, a buffer circuit constituted by arranging a plurality of buffer sections each arranged in parallel with each other, A switching circuit for selecting one of the plurality of buffer units, an inspection circuit for differentiating the output of the buffer circuit and outputting the output to an inspection circuit bus, and a differential circuit on the inspection circuit bus. An external circuit that samples a signal based on a predetermined clock signal, and each output terminal of the plurality of latch circuits is connected to each input terminal of the plurality of buffer units at the first stage in the buffer circuit. The external circuit generates a control signal for the switching circuit to select the buffer unit according to the level of the sampled signal, and And outputs to the switch circuit corresponding to the control signal by counting the click signal.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display device according to the present invention will be specifically described with reference to the drawings. Hereinafter, a liquid crystal display device will be described as an example of the display device.

(First Embodiment) FIG. 1 shows a first embodiment of a display device.
FIG. 3 is a schematic block diagram of the embodiment. FIG. 1 illustrates a block configuration around a scanning line driving circuit in a display device, and omits a signal line driving circuit, a pixel array unit, and the like.

The display device shown in FIG. 1 includes a scanning line driving circuit 1 and
An external driving circuit 2 for controlling the scanning line driving circuit 1 is provided.
The detailed configuration of the external drive circuit 2 will be described later.

The scanning line driving circuit 1 shown in FIG. 1 has a shift register 4 in which the same number of latch circuits 3 as the number of scanning lines are cascaded, and an AND connected to each output terminal of the shift register 4.
A gate 5, an inspection circuit 6 connected to the output terminal of each AND gate 5, and a buffer circuit 7 connected to each inspection circuit 6
And Each buffer circuit 7 is configured by cascade-connecting a plurality of inverters, and an output terminal of each buffer circuit 7 is connected to a corresponding scanning line.

The shift register 4 includes, as shown in FIG.
As a set, two latch circuits 3 and a switching circuit 8 connected in parallel are connected in cascade by the same number as the scanning lines. Each switching circuit 8 is composed of an inverter IV1 and a clocked buffer CB1, and selects one of the two latch circuits 3 according to the logic of switching signals M1 and M2 from the external drive circuit 2 described later.

The shift register 4 starts a shift operation when the start pulse signal STV is supplied from the external drive circuit 2, and outputs a shift pulse in synchronization with an operation clock CLK also supplied from the external drive circuit 2. .

The latch circuit 3 includes three inverters IV2 to IV4, for example, as shown in FIG. Also,
The clocked buffer CB1 is, for example, as shown in FIG.
A PMOS transistor Q1 is connected between the power supply terminal VDD and the ground terminal.
It is configured by connecting Q2 and NMOS transistors Q3 and Q4 in series. The switching signal M1 is input to the gate terminal of the PMOS transistor Q1 in the clocked buffer CB1 on the upper stage, and the switching signal M is input to the gate terminal of the NMOS transistor Q4.
2 is input. In addition, the lower side clocked buffer CB
The switching signal M2 is input to the gate terminal of the PMOS transistor Q1 in 1, and the switching signal M1 is input to the gate terminal of the NMOS transistor Q4.

When the switching signal M1 is at a low level, the switching signal M
When 2 is at a high level, the upper latch circuit 3 in the shift register 4 of FIG. 1 is selected. Conversely, the switching signal M
When 1 is at the high level and the switching signal M2 is at the low level, the lower latch circuit 3 is selected.

FIG. 4 is a waveform diagram showing the output of the AND gate 5. FIG. 4 shows an operation clock CLK for operating the shift register 4, an output of the first-stage latch circuit 3, an output of the second-stage latch circuit 3, an output of the third-stage latch circuit 3, and a fourth-stage latch circuit. 3, the output of the first-stage AND gate 5, the output of the second-stage AND gate 5, and the output of the third-stage AND gate 5 are shown. The output of each AND gate 5 is supplied to a corresponding inspection circuit 6, respectively.

As shown in FIG. 4, a driving method of supplying a shift pulse to each scanning line every half cycle of the operation clock CLK of the shift register 4 is called a half clock shift method.

FIG. 5 is a circuit diagram showing a detailed configuration of the inspection circuit 6. As shown in FIG. 5, the inspection circuit 6 includes an NMOS transistor Q5, a capacitor C1, and a resistor R1 for each scanning line, and the source terminal of the NMOS transistor Q5 is connected to the output terminal OUT. ing. The gate terminal of the NMOS transistor Q5 is connected to the corresponding output terminal of the AND gate 5 and the input terminal of the buffer circuit 7 shown in FIG.

FIG. 6 is a diagram showing an output waveform of the inspection circuit 6. As shown in the drawing, when the output of the AND gate 5 includes a positive or negative pulse, a peak-shaped pulse signal as a differential waveform thereof is output from the inspection circuit 6. Also, NMOS
Since the source terminal of the transistor Q5 is connected to the output terminal, when a pulse is input to the gate terminal of any one of the NMOS transistors Q5, the inspection circuit 6 outputs a mountain-shaped pulse signal.

FIG. 7 is a block diagram showing a detailed configuration of the external drive circuit 2. As illustrated, the external drive circuit 2 includes a buffer circuit 11, a latch circuit 12, an address generation circuit 13, a memory 14, and an output buffer 15. The inspection circuit 6 in the scanning line driving circuit 1 is stored in the memory 14.
The inspection result data of the buffer circuit 11 and the latch circuit 1
2 is stored. More specifically, the failure detection information determined as a failure by the inspection circuit 6 is stored at an address of the memory 14 corresponding to the failure location.

The memory 14 has a 2-bit data structure, and the data stored in the memory 14
5, and is output from output terminals M1 and M2. Complementary signals whose logics are inverted from each other are output from the output terminals M1 and M2. The data output from the output terminals M1 and M2 is input to the shift register 4 in the scanning line driving circuit 1 shown in FIG.

FIG. 8 is a timing chart of each part in the display device shown in FIG. 1, and includes a start pulse signal STV as an operation start signal of the shift register 4, an output signal of the inspection circuit 6, and an operation clock CLK of the shift register 4. , Memory 1
4 shows the waveforms of the outputs M1 and M2 and their inverted signals M1 and M2. In the present specification, a signal having a bar above a symbol in the drawings is represented by adding a term “bar” after the symbol.

The start pulse signal STV shown in FIG. 8 is output once for one screen (frame). When the start pulse signal STV is output, the shift register 4 starts a shift operation, and each output terminal of the shift register 4 sequentially outputs a pulse having one cycle width of the operation clock CLK. When a pulse is output from the shift register 4, the inspection circuit 6 outputs a mountain-shaped signal that is a differential waveform of the pulse.

FIG. 8 shows an example in which some of the latch circuits 3 in the shift register 4 are defective and no pulse is output from the second output terminal from the left of the shift register 4. In this case, at the time T2 to T3, although the inspection circuit 6 should output a mountain-shaped pulse signal,
The output of the inspection circuit 6 remains at the low level. In the present embodiment, the output of the inspection circuit 6 is input to the timing drive circuit 6, and the timing drive circuit 6 specifies a failure location in the shift register 4.

As shown in detail in FIG. 7, the timing drive circuit 2 includes an address generation circuit 13 therein. The address generation circuit 13 sequentially increments in synchronization with the operation clock CLK of the shift register 4. I do. Outputs A1 to An of the address generation circuit 13 are supplied to address terminals of the memory 14.

The timing drive circuit 2 determines whether or not a peak-shaped pulse signal which should appear in the output of the inspection circuit 6 appears.
It is determined that the shift register 4 is abnormal. For example, in the case of FIG. 8, since the output of the inspection circuit 6 is at the low level during the time T2 to T3, the timing driving circuit 2 determines whether the output of the inspection circuit 6 is at the low level by two times from the left.
It is determined that the third latch circuit 3 is defective, and the data M is stored in the address A2 of the memory 14 corresponding to the latch circuit 3.
1 = 0 and M2 = 1 are written.

As described above, the timing driving circuit 2
Stores the failure detection results of all the latch circuits 3 in the shift register 4 in the memory 14 from the first output of the start pulse signal STV to the next output of the start pulse signal STV after the power is turned on. I do.

FIG. 9 is a timing chart showing the relationship between the start pulse signal STV input to the shift register 4 and the write signal and the read signal of the memory 14. As shown in FIG. 9, after the power is turned on, first the start pulse signal S
From the time when the TV is output until the next start pulse signal STV is output, the write signal is enabled, and thereafter, the write signal is disabled and the read signal is enabled. FIG. 9 shows that the write signal and the read signal are enabled when they are at the low level.

When the read signal is enabled, the memory 14 outputs 2-bit data M1 and M2 corresponding to the address generated by the address generation circuit 13 in FIG. The data M1 and M2 are input to the scanning line driving circuit 1. Each switching circuit 8 in the shift register 4
Selects one of the upper and lower latch circuits 3 in FIG. 1 according to the logic of the data M1 and M2.

For example, when there is no defect in the latch circuit 3 in the shift register 4, the data M1 and M2 output from the memory 14 become "1" and "0", respectively. Register 4 is selected. On the other hand, FIG.
As shown in FIG. 7, when the second latch circuit 3 from the left in the shift register 4 has a defect, the data M1 and M2 output from the memory 14 temporarily become "0" and "1", 1 is selected as the second latch circuit 3 from FIG.

As described above, in the first embodiment, the shift register 4 in which the latch circuit 3 and the switching circuit 8 are cascaded in the scanning line driving circuit 1 and the inspection circuit for detecting the failure of each latch circuit 3 6 and the external drive circuit 2
A memory 14 for storing the inspection result by the inspection circuit 6
And the switching circuit 8 is switched based on the inspection result data stored in the memory 14, so that even if some of the latch circuits 3 in the shift register 4 become defective,
The scanning lines can be normally driven. Therefore, the manufacturing yield of the display device can be improved. Further, since failure detection and replacement of a failed portion can be performed without using an inspection device or the like, inspection can be automated, and inspection man-hours can be reduced.

(Second Embodiment) In the second embodiment, the failure detection of the buffer circuit 7 in the scanning line drive circuit 1 and the replacement of the failure part are performed.

FIG. 10 is a schematic block diagram of a display device according to a second embodiment of the present invention. FIG. 10 illustrates a block configuration around the scanning line driving circuit 1 in the display device, and omits a signal line driving circuit, a pixel array unit, and the like.

The display device shown in FIG. 10 has a shift register 4 in which a plurality of latch circuits 3 are cascaded, an AND gate 5 connected to each output terminal of the shift register 4, and an output terminal of the AND gate 5. And a check circuit 6 for detecting a failure of the buffer circuit 7a.

The internal configurations of the latch circuit 3 and the inspection circuit 6 in the shift register 4 are the same as in the first embodiment. The inspection circuit 6 supplies a mountain-shaped pulse signal to the external drive circuit 2 if a pulse is included in the output of the buffer circuit 7a. The external drive circuit 2 is configured in the same manner as in the first embodiment, and based on an output from the inspection circuit 6, a buffer circuit 7
The failure detection result of a is stored in the memory 14 in the external drive circuit 2. More specifically, when the output of the inspection circuit 6 does not include a mountain-shaped pulse signal that should originally exist, it is determined that a failure exists in the buffer circuit 7a, and the memory 14 corresponding to the failure location is determined. Address data M3 = 0, M4
= 1 is written.

When the failure detection of the buffer circuit 7a is completed, the memory 14 outputs the stored data M3, M4. The data M3 and M4 become "1" and "0" respectively when there is no failure in the buffer circuit 7a, and become "0" and "1" when there is a failure.

As shown in FIG. 10, the buffer circuit 7a includes two clocked buffers CB2 and CB connected in parallel.
3 in series. One of the two clocked buffers CB2 and CB3 connected in parallel is selected according to the logic of the data M3 and M4 output from the memory 14.

FIG. 11 is a circuit diagram showing the internal configuration of two clocked buffers CB2 and CB3 connected in parallel in the buffer circuit 7a. As shown, the data M3 is "1".
When the data M4 is "0", the clocked buffer CB
When the data M3 is "0" and the data M4 is "1", the clocked buffer CB3 is selected.

As described above, in the second embodiment, since a faulty part can be replaced for each stage in the buffer circuit 7a, even if a fault occurs at a plurality of places, normal operation is possible, and the manufacturing yield is reduced. Improvement can be achieved.

When it is desired to detect only one defect in the buffer circuit 7a, as shown in FIG. 12, the first and second buffer units B1 and B2 each including a plurality of inverters connected in series are connected to each other. The clocked inverters CB4 and CB4 are connected in parallel and only the last stage of each of the buffer units B1 and B2 is connected.
What is necessary is just to connect CB5. In this case, each buffer unit B1,
If any of the inverters in B2 is defective, the clocked inverter may be switched to disconnect the buffer having that inverter.

(Third Embodiment) The third embodiment is a combination of the first and second embodiments.

FIG. 13 is a schematic block diagram of a third embodiment of the display device according to the present invention, and shows a block configuration around the scanning line driving circuit 1 as in the first and second embodiments. .

The display device shown in FIG. 13 is characterized in that the failure detection of both the shift register 4 and the buffer circuit 7a is performed. The internal configuration of the shift register 4 is the same as that of FIG. 1, and the internal configuration of the buffer circuit 7a is the same as that of FIG. The output terminal of the AND gate 5 is connected to a test circuit 6 for detecting a fault in the shift register 4, and the output terminal of the buffer circuit 7a is connected to a test circuit 6 for detecting a fault in the buffer circuit 7a. Is done.

The memory 14 stores 2-bit data M1 and M2 indicating the result of the fault detection in the shift register 4 and 2-bit data M3 and M4 indicating the result of the fault detection in the buffer circuit 7a.

As described above, in the third embodiment, since the failure detection and the replacement of the failed part in both the shift register 4 and the buffer circuit 7a can be performed, the circuit is more complicated than in the first and second embodiments. However, the production yield can be further improved.

(Other Embodiments) First to Third Embodiments
In the embodiment, the example in which the failure detection in the scanning line driving circuit 1 is performed has been described, but the failure detection in the signal line driving circuit may be performed. The signal line driving circuit includes the shift register 4 and the buffer circuit 7a, as in the case of the scanning line driving circuit 1. However, since the start pulse signal STV is input to the shift register 4 in the signal line driving circuit for each horizontal line, all the fault locations in the signal line driving circuit are detected during one horizontal line period. Then, the result is stored in the memory 14 in the external drive circuit 2.

When detecting a fault in the signal line drive circuit, even if a fault is detected only in the shift register 4 as in the first embodiment, a fault in only the buffer circuit 7a is detected as in the second embodiment. Even when the detection is performed, the failure detection of both the shift register 4 and the buffer circuit 7a may be performed as in the third embodiment.

Since an analog switch for switching whether or not to supply pixel data to the signal line is provided in the signal line driving circuit, a failure of the analog switch may be detected.

In the above-described first to third embodiments, an example has been described in which the scanning lines are driven by the half clock shift method in which the operation clock CLK of the shift register 4 is shifted by a half cycle. CLK to 1
The scanning lines may be driven by a one-clock shift method in which the scanning lines are shifted by one period. Alternatively, the scan lines may be driven by a decoding method in which an externally input address signal is decoded and a shift pulse is output.

In the first and third embodiments, the example in which the upper and lower latch circuits 3 are provided in the shift register 4 has been described. However, three or more latch circuits 3 may be provided. As the number of selectable latch circuits 3 increases, it becomes possible to cope with a large number of defective portions, so that the production yield is improved. Similarly, in the second and third embodiments, three or more sets of buffer units may be provided in the buffer circuit 7a.

In each of the embodiments described above, the liquid crystal display device is described as an example. However, the present invention can be applied to various display devices other than the liquid crystal display device, for example, a plasma display device.

[0058]

As described above in detail, according to the present invention, since the switching circuit is controlled to be switched based on the result of differentiation by the inspection circuit, the shift register in the signal line driving circuit or the scanning line driving circuit can be used. Even if a part of the buffer unit or the like breaks down, normal operation is ensured, and the manufacturing yield of the display device can be improved. Further, in the present invention, a failure (defect) is detected based on a result differentiated by the inspection circuit, so that the display device can be inspected without using an inspection measuring instrument or the like, and the inspection can be automated. Man-hours can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a first embodiment of a display device.

FIG. 2 is a circuit diagram showing an internal configuration of a latch circuit in FIG. 1;

FIG. 3 is a circuit diagram showing an internal configuration of a clocked buffer in FIG. 1;

FIG. 4 is a waveform chart showing an output of an AND gate in FIG. 1;

FIG. 5 is a circuit diagram showing a detailed configuration of an inspection circuit.

FIG. 6 is a diagram showing an output waveform of a test circuit.

FIG. 7 is a block diagram showing a detailed configuration of an external drive circuit.

8 is a timing chart of each part in the display device shown in FIG.

FIG. 9 is a timing chart showing a relationship between a write signal and a read signal of a memory.

FIG. 10 is a schematic block diagram of a second embodiment of the display device.

FIG. 11 is a circuit diagram showing an internal configuration of a clocked inverter in the buffer circuit.

FIG. 12 is a circuit diagram showing a modification of the buffer circuit.

FIG. 13 is a schematic block diagram of a third embodiment of the display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Scan line drive circuit 2 External drive circuit 3 Latch circuit 4 Shift register 5 AND gate 6 Inspection circuit 7 Buffer circuit 8 Switching circuit 11 Buffer circuit 12 Latch circuit 13 Address generation circuit 14 Memory 15 Output buffer

Claims (5)

[Claims] 1. A timing signal generator configured by arranging a plurality of latch circuits arranged in parallel in tandem with each other, and an output of the plurality of latch circuits arranged between each of the timing signal generators. A switching circuit for selecting one of the outputs and outputting the selected output to each latch circuit of the next-stage timing signal generation circuit; a test circuit for differentiating the output of each switching circuit and outputting the output to a test circuit bus; An external circuit that samples a differential signal on a circuit bus based on a predetermined clock signal, wherein the external circuit controls the switching circuit to select a latch circuit according to the level of the sampled signal. A driving circuit for a display device, which generates a signal and outputs the control signal to a corresponding switching circuit by counting the clock signal. 2. A timing signal generating section having a plurality of latch circuits arranged in cascade, a buffer circuit constituted by arranging a plurality of buffer sections arranged in parallel with each other, and a plurality of buffer circuits arranged in parallel. A switching circuit for selecting any one of the buffer units, an inspection circuit for differentiating an output of the buffer circuit and outputting the output to an inspection circuit bus, and a predetermined clock for a differentiated signal on the inspection circuit bus. An external circuit that performs sampling based on a signal, wherein each output terminal of the plurality of latch circuits is connected to each input terminal of the plurality of buffer units at an initial stage in the buffer circuit. The switching circuit generates a control signal for selecting the buffer unit according to the level of the sampled signal, and counts the clock signal. The display device drive circuit and outputs a switching circuit to a corresponding control signal by preparative. 3. The external circuit includes a storage circuit for storing switching control data of the switching circuit based on the sampled signal, and each of the switching circuits includes switching control data stored in the storage circuit. The driving circuit for a display device according to claim 1, wherein the switching control is performed based on: 4. A signal line driving circuit for driving a signal line of a pixel array section in which signal lines and scanning lines are arranged vertically and horizontally, and a scanning line driving circuit for driving a scanning line of the pixel array section, At least one of the signal line driving circuit and the scanning line driving circuit has the inspection circuit and the external circuit, and the external circuit includes a storage control circuit that performs control for storing the switching control data in the storage circuit. When controlling the switching circuit in the signal line driving circuit, the storage control circuit stores all the switching control data in the storage circuit within one horizontal synchronization period, and 4. The display device driving circuit according to claim 3, wherein when the switching circuit in the circuit is controlled, all the switching control data is stored in the storage circuit within one vertical synchronization period. 5. The storage control circuit, after all the switching control data is stored in the storage circuit, every time a start pulse signal is input to the timing signal generation section, 5. The display device driving circuit according to claim 4, wherein the switching control data stored in the storage circuit is sequentially supplied to the corresponding switching circuit in synchronization with an operation clock.