JPH0915557A - Data signal line driving circuit, scanning signal line driving circuit and picture display device - Google Patents

Abstract

PURPOSE: To provide a scanning signal line driving circuit and a data signal line driving circuit capable of relieving generated plural defects and to provide a picture display device capable of drastically enhancing excellent article rate. CONSTITUTION: When defective is not present, all of outputs of shift registers SR are inputted to normal video signal output circuits SDU, and all of data signal lines SL are connected to the normal video signal output circuits SDU. Besides, when the defective is present in either one of normal video signal output circuits SDU, the defective video signal output circuit SDU (fail) is separated from shift registers SR and data signal lines SL and also connections of succeeding normal video signal output circuits SDU are successively changed to the just before shift register SR and data signal line SL, and even a shift register SR and a data line are connected even to the spare video signal output circuit SDUR arranged at an extreme rear.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data signal line driving circuit and a scanning signal line driving circuit used in an active matrix driven image display device and incorporating a redundancy technique for defect relief. The present invention relates to an image display device including at least one of the data signal line drive circuit and the scanning signal line drive circuit.

[0002]

2. Description of the Related Art An active matrix drive system is known as one of image display devices. As shown in FIG. 21, this type of image display device has a pixel array AR.
Y, a data signal line drive circuit SD and a scanning signal line drive circuit GD that drive the pixel array ARY, and a timing signal generation circuit that generates a timing signal to be input to the data signal line drive circuit SD and the scanning signal line drive circuit GD. TI
M. In FIG. 21, DAT is a video signal, S
YN is a synchronization signal.

FIG. 22 shows the pixel array section ARY, the data signal line drive circuit SD and the scanning signal line drive circuit GD shown in FIG.
FIG. As shown in FIG. 22A, this image display device is provided with a large number of scanning signal lines GLj and a large number of data signal lines SLi in a state where the scanning signal lines and the data signal lines intersect with each other, and two adjacent scanning lines are provided. A pixel PIX is provided in a portion surrounded by the signal line and two adjacent data signal lines.
Are provided in a matrix. That is, each pixel column has one data signal line and each pixel row has one scanning signal line.

In the case of a liquid crystal display device, each pixel PlX has, as shown in FIG. 22B, a pixel transistor SW as a switching element, and a pixel capacitance composed of a liquid crystal capacitance CL and an auxiliary capacitance CS added as necessary. Composed by. Generally, in an active matrix type liquid crystal display device, in order to stabilize the display in the pixel,
An auxiliary capacitance CS is added in parallel with the liquid crystal capacitance CL.
The auxiliary capacitance CS is affected by the liquid crystal capacitance CL, the leak current of the pixel transistor SW, the fluctuation of the pixel potential due to the parasitic capacitance such as the gate / source capacitance of the pixel transistor SW, or the display data dependency of the liquid crystal capacitance CL. , To keep it to a minimum.

In FIG. 22B, the data signal line SLi is connected to one electrode of the pixel capacitor through the drain and source of the pixel transistor SW which is a switching element, and the gate of the pixel transistor SW is connected to the scanning signal line G.
The other electrode of the liquid crystal capacitor connected to Lj is connected to the counter electrode across the liquid crystal cell, and the other electrode of the auxiliary capacitor is connected to a common electrode line common to all pixels or an adjacent scanning signal line.

The scanning signal line GLj is connected to a scanning signal line drive circuit GD which outputs a scanning signal. The data signal line SLi is connected to a data signal line drive circuit SD that samples a video signal and transfers the sampled video signal to a data signal line or amplifies and transfers the data signal line. The scanning line drive circuit GD and the data signal line drive circuit SD are respectively connected to the power supplies VGH / VGL and VGL.
It is driven by SH / VSL (see FIG. 22A).

The data signal line drive circuit SD outputs a display data signal for each pixel or for one horizontal scanning period (1H).
Output to the data signal line SLi for each line. When the scanning signal line GLj is activated, the pixel transistor SW becomes conductive, and the display data signal sent on the data signal line SLi is written in the pixel capacitor. Then, when the scanning signal line GLj is set to the inactive state, the pixel transistor SW is turned off, and thus the display is maintained.

The data signal line drive circuit SD has a dot sequential drive system and a line sequential drive system. Here, the dot-sequential driving method means, as shown in FIG. 23, video data DAT via a sampling switch SWT controlled by an output of a scanning circuit (shift register SR).
Is directly written to the data signal line SLi. Therefore, although the scale of the driving circuit is reduced, the writing time is shortened, which limits the increase in screen size. As the sampling switch SWT, usually one transistor or two transistors of different conductivity types connected in parallel is used. However, in terms of sampling capacity, and
A CMOS configuration is desirable from the viewpoint of suppressing the level fluctuation of the video signal.

On the other hand, the line-sequential driving system means, as shown in FIG. 24, a video signal DA sampled in a horizontal scanning period.
The amplifier circuit A for T
The data signal line SLi is transferred to the MP and is transferred in the next horizontal scanning period.
To write to. Therefore, although the scale of the driving circuit becomes large, there is a feature that it is possible to cope with a large screen because the writing time is sufficient. As the configuration of the amplifier circuit AMP, the operational amplifier type shown in FIG.
There is a source follower type shown in FIG.

On the other hand, as the scanning signal line drive circuit GD,
An example is one having a configuration as shown in FIG. this is,
The product signal of the output signal from the scanning circuit (shift register SR) and the gate pulse GPS that defines the width of the scanning signal is amplified by the buffer circuit BUF and output.

Here, in the data signal line driving circuit SD shown in FIGS. 23 and 24 and the scanning signal line driving circuit GD shown in FIG. 26, the shift register SR is used as the scanning circuit. FIG. 27 shows the shift register SR
Is shown. Each one stage of the shift register SR is composed of one inverter and two clocked inverters, and the start pulse signal SPS is sequentially transferred to the next stage in synchronization with rising and falling of the clock signal CLK. Transferred.

As a scanning circuit, this shift register S
In addition to R, there is a decoder type. This is, for example,
As shown in FIG. 28, a plurality of address signals A1, A2 ...
Or its inverted signal A1 , A2 The scanning circuit can be configured by outputting the product signal of ... And making the input address signal of each stage different.

By the way, in many conventional active matrix type liquid crystal display devices, a switching element of a pixel portion is formed of an amorphous silicon thin film transistor formed on a glass substrate, and a scanning signal line driving circuit and a data signal line are formed. The switching element of the drive circuit is composed of a plurality of externally attached driver ICs.

On the other hand, in recent years, in order to downsize the image display device, improve reliability, reduce cost, etc., a scanning signal line driving circuit and a data signal line driving circuit are monolithically formed on the same substrate as the pixel array. The technology that constitutes it is being developed. At this time, a field effect transistor using a single crystal or non-single crystal (for example, polycrystalline or amorphous) silicon thin film is used as the active element. In practice, a polycrystalline silicon thin film transistor is often used because it can be formed in a large area and a high driving force required for a scanning signal line driving circuit or a data signal line driving circuit can be realized.

[0015]

However, in a non-single crystal silicon thin film transistor, for example, a polycrystalline silicon thin film transistor, at present, the manufacturing process thereof is L.
It is not established as well as the transistor on the single crystal silicon substrate used in SI or the like, and there is a problem that defects such as short circuit and disconnection are likely to occur. Further, when the drive circuit is monolithically formed on the same substrate as the pixel array, the area becomes very large and the possibility of defects is increased depending on the screen size.

Here, the types of defects include point defects, line defects, and surface defects. With respect to surface defects, there are many defects, and even if the defects can be repaired, great cost and labor are required. Therefore, they are usually disposed of as defective products.

A point defect is caused by a defective pixel, and if it is a small number, it is inconspicuous and may be ignored. Further, as a defect prevention measure, it has been proposed to provide two transistors in each pixel and disconnect the defective transistor to relieve the defect of the pixel switch (Japanese Patent Laid-Open No. 5-66148).

On the other hand, since line defects are very conspicuous, even if the number is small, it is necessary to repair them. Causes of line defects include defects in the data signal lines and scanning signal lines, such as disconnections and short circuits, as well as defects in the data signal line driving circuits and scanning signal line driving circuits. Here, the data signal line and the scanning signal line are mere wirings, whereas the data signal line driving circuit and the scanning signal line driving circuit have many elements, wirings, contact regions, and the like.
The probability of occurrence of defects also increases. Further, as described above, in the data signal line drive circuit and the scanning signal line drive circuit formed by using the polycrystalline silicon thin film transistor,
Since the manufacturing process is incomplete, the probability of defect occurrence is
It is higher than the process of the driver IC formed on the single crystal silicon substrate.

Therefore, in order to improve the manufacturing yield of the image display device, it is important to reduce the line defects, especially the defect rate of the drive circuit. For that purpose, it is necessary to incorporate a redundancy technique that enables steady circuit operation even when there is a defect, as well as reducing defects by improving the manufacturing process.

The following is proposed as a redundancy system for the drive circuit. For example, JP-A-6167
As shown in No. 200, two scanning signal line driving circuits and two data signal line driving circuits are arranged and connected to each wiring, and when one of the two driving circuits is defective, Some attempt to obtain a normal operation by electrically disconnecting a defective drive circuit.

However, in such a configuration, two identical drive circuits are required, and the area occupied by the peripheral circuits is two.
There is a problem in that the manufacturing cost is doubled and the manufacturing cost is increased. In addition, if there is a defect in one driving circuit, the driving circuit must be separated as a defect, and if there is one defect in each of the two driving circuits, it cannot be repaired. Is limited.

As another example, Japanese Patent Laid-Open No. 6-8328.
As shown in No. 6, the drive circuit is divided into a plurality of blocks, and in each block, two series of shift registers are used. This guarantees normal operation by switching the connection to the spare shift register when the regular shift register is defective. This redundant system has an advantage that even if there are many defects in the same drive circuit, if they are dispersed in different blocks, the entire drive circuit can be repaired. However, since this redundancy technique is intended only for the relief of the shift register, it is necessary to combine it with other techniques for the relief of the entire drive circuit. Generally, in the drive circuit, the area occupied by the shift register is relatively small,
The probability of defects occurring in circuits other than the shift register is higher, and it is important to repair that part.

The present invention has been made in order to solve the problems of the prior art as described above, and a scanning signal line drive circuit and a data signal line drive circuit capable of relieving a plurality of defects that have occurred, and a non-defective rate are leapt. It is an object of the present invention to provide an image display device that can be enhanced.

[0024]

A data signal line drive circuit of the present invention comprises a scanning circuit which outputs pulse signals in time series,
And a video signal output circuit that captures the video signal in synchronization with the pulse signal and outputs the video signal to a data signal line.
Any one of the normal video signal output circuits having the same number as the scanning circuits and the data signal lines, one or more preliminary video signal output circuits, and the plurality of video signal output circuits adjacent to the scanning circuits and the data signal lines. And a switching means for connecting to the crab, whereby the above-mentioned object is achieved.

In the data signal line drive circuit of the present invention,
The control means for controlling the switching means may be composed of a plurality of fuses and resistance elements connected in series between two power supply terminals.

The data signal line drive circuit of the present invention includes a scanning circuit which outputs pulse signals in time series, and a video signal output which takes in a video signal in synchronization with the pulse signal and outputs the video signal to the data signal line. Circuit and one or more blocks, each block having the same number of normal scanning circuits and the same number of normal video signal output circuits as the data signal lines, and one or more preliminary scanning circuits and preliminary video signal outputs. A circuit, switching means for connecting the data signal line to any of the plurality of adjacent video signal output circuits, and connecting the scanning circuit to any of the plurality of adjacent video signal output circuits A second switching circuit, whereby the above object is achieved.

In the data signal line drive circuit of the present invention,
The control means for controlling the switching means and the second switching means may be constituted by a plurality of fuses and resistance elements connected in series between two power supply terminals.

In the data signal line drive circuit of the present invention,
The control means for controlling the switching means and the second switching means comprises a plurality of fuses and resistance elements connected in series between two power supply terminals, and further has another fuse adjacent to the resistance element. It can be configured.

In the data signal line drive circuit of the present invention,
The control means for controlling the switching means and the second switching means includes two systems including a plurality of fuses and resistance elements connected in series between two power supply terminals, one system and the other system. The configuration may be such that the potentials are reversed.

In the data signal line drive circuit of the present invention,
The control unit that controls the switching unit and the second switching unit may include a plurality of fuses connected in series between two power supply terminals and an antifuse on one power supply terminal side. .

In the data signal line drive circuit of the present invention,
The control means for controlling the switching means and the second switching means may be composed of a pair of fuse and antifuse.

In the data signal line drive circuit of the present invention,
It is possible to adopt a configuration having means for outputting the video signal, which has been captured in synchronization with the pulse signal, to the data signal line as it is.

In the data signal line drive circuit of the present invention,
It may be configured to have a means for amplifying the video signal taken in in synchronization with the pulse signal and outputting it to the data signal line.

The scanning signal line driving circuit of the present invention includes a scanning circuit which outputs pulse signals in time series, and a scanning signal output circuit which sequentially outputs scanning signals to the scanning signal lines in synchronization with the pulse signal. Each of which is composed of one or more blocks, each block having the same number of normal scanning signal output circuits as the scanning circuits and the scanning signal lines, one or more preliminary scanning signal output circuits, the scanning circuits and the The above-mentioned object can be achieved by having switching means for connecting each scanning signal line to any one of a plurality of adjacent scanning signal output circuits.

A scanning signal line driving circuit of the present invention includes a scanning circuit which outputs pulse signals in time series, and a scanning signal output circuit which sequentially outputs scanning signals to scanning signal lines in synchronization with the pulse signal. And one or more pre-scanning circuits and pre-scanning signal output circuits, each block having at least one normal scanning circuit and the same number of normal scanning signal output circuits as the scanning signal lines. Switching means for connecting the scanning signal line to any of the plurality of adjacent scanning signal output circuits, and second for connecting the scanning circuit to any of the plurality of adjacent scanning signal output circuits
By having a switching circuit, the said objective can be achieved.

In the scanning signal line drive circuit of the present invention, the control means for controlling the switching means may be composed of a plurality of fuses and resistance elements connected in series between two power supply terminals.

In the scanning signal line drive circuit of the present invention, the control means for controlling the switching means and the second switching means comprises a plurality of fuses and resistance elements connected in series between two power supply terminals. can do.

In the scanning signal line drive circuit of the present invention, the control means for controlling the switching means and the second switching means are composed of a plurality of fuses and resistance elements connected in series between two power supply terminals, and Another fuse may be provided adjacent to the resistance element.

In the scanning signal line drive circuit of the present invention, the control means for controlling the switching means and the second switching means is composed of a plurality of fuses and resistance elements connected in series between two power supply terminals. Two systems may be provided, and one system and the other system may be provided with potentials opposite to each other.

In the scanning signal line drive circuit of the present invention, the control means for controlling the switching means and the second switching means includes a plurality of fuses connected in series between two power supply terminals, and one power supply An antifuse may be provided on the terminal side.

In the scanning signal line drive circuit of the present invention, the control means for controlling the switching means and the second switching means may be composed of a pair of fuse and antifuse.

The image display device of the present invention comprises display pixels arranged in a matrix, a data signal line drive circuit for giving a video signal to the pixels, and a scanning signal line drive circuit for controlling writing to the pixels. In an active matrix type image display device including at least one of the data signal line driving circuit and the scanning signal line driving circuit, the data signal line driving circuit and the scanning signal line driving circuit according to claim 1. The above object is achieved.

In the image display device of the present invention, at least one of the data signal line drive circuit and the scanning signal line drive circuit may be formed of a non-single crystal silicon thin film transistor.

[0044]

In the present invention, the data signal line drive circuit is
Each block is composed of one or more blocks, and in each block, the same number of regular video signal output circuits as the scanning circuits and data signal lines and one or more spare video signal output circuits are provided, and the scanning circuits and the data signal lines are Each has switching means for connecting to any of a plurality of adjacent video signal output circuits. In each block, when the normal video signal output circuit is not defective, the normal video signal output circuit is connected to the corresponding scanning circuit and data signal line in advance, and the spare video signal output circuit is Is not connected. On the other hand, in each block, when a part of the normal video signal output circuit is defective, the defective normal video signal output circuit is not connected to the scanning circuit and the data signal line, but immediately after (or just before) the defective portion. From the video signal output circuit to the spare video signal output circuit are sequentially connected to the adjacent scanning circuit and data signal line.

As described above, since the repair of defects is carried out in each block, even if the number of defects is large, the number of defects in each block should be equal to or less than the number of spare video signal output circuits in each block. Thus, normal operation as a data signal line drive circuit can be obtained.

Further, since the means for sequentially switching the connection of the video signal output circuit after the defective portion can be dealt with only by modifying the wiring at one portion, the labor and cost required for the relief can be reduced.

Further, since the defect of the video signal output circuit which occupies the largest area in the data signal line drive circuit can be repaired, the non-defective rate of the data signal line drive circuit can be dramatically improved.

Further, in the present invention, the data signal line drive circuit is composed of one or more blocks, and in each block, the scanning circuit and the video signal output circuit have the same number of regular scanning circuits and regular scanning circuits as the data signal lines. A video signal output circuit, at least one preliminary scanning circuit and a preliminary video signal output circuit, and switching means for connecting the data signal line to any of a plurality of adjacent video signal output circuits, and the above scanning. And a switching circuit for connecting the output part of the circuit to the scanning circuit at either the next stage or the next stage. In each block, when there is no defect in the normal scanning circuit and the normal video signal output circuit, the normal video signal output circuit is connected to the corresponding data signal line in advance, and the spare video signal output circuit is Not connected to. At this time, the preliminary scanning circuit performs interlaced scanning. On the other hand, in each block, when a part of the normal scanning circuit or the normal video signal output circuit is defective, the normal video signal output circuit corresponding to the defective portion is not connected to the data signal line, but immediately after the defective portion. (Or immediately before) the video signal output circuit to the spare video signal output circuit are sequentially connected to the adjacent data signal lines. At the same time, the scanning circuit corresponding to the defective portion is interlaced and the preliminary scanning circuit is incorporated so that the scanning is performed normally.

As described above, since the repair of defects is carried out in each block, the number of defects in each block should be equal to or less than the number of spare video signal output circuits in each block even if a large number of defects occur. Thus, normal operation as a data signal line drive circuit can be obtained.

Further, since the means for sequentially switching the connection of the scanning circuit and the video signal output circuit after the defective portion can be dealt with only by modifying the wiring at one portion, the labor and cost required for the relief can be reduced. You can

Further, since it is possible to relieve defects of all the circuit elements constituting the data signal line drive circuit, it is possible to dramatically improve the non-defective rate of the data signal line drive circuit.

Further, in the present invention, in the scanning signal line driving circuit, the scanning signal line driving circuit is composed of one or more blocks, and in each block, the scanning signal output circuit includes the scanning circuit and the scanning signal line. Switching means for connecting the scanning circuit and the scanning signal line to any one of a plurality of adjacent scanning signal output circuits, each of which includes the same number of normal scanning signal output circuits and one or more preliminary scanning signal output circuits. Have. In each block, when there is no defect in the normal scanning signal output circuit, the normal scanning signal output circuit is connected to the corresponding scanning circuit and scanning signal line in advance, and the preliminary scanning signal output circuit is Is not connected. On the other hand, when a part of the normal scanning signal output circuit is defective in each block, the defective normal scanning signal output circuit is not connected to the scanning circuit and the scanning signal line, but immediately after (or just before) the defective portion. The scanning signal output circuit to the preliminary scanning signal output circuit are sequentially connected to the adjacent scanning circuit and scanning signal line.

As described above, since the repair of the defect is carried out in each block, the number of defects in each block should be equal to or less than the number of preliminary scanning signal output circuits in each block even if the number of defects increases. In this case, normal operation as the scanning signal line drive circuit can be obtained.

Further, the means for sequentially switching the connection of the scanning signal output circuits after the defective portion can be dealt with only by correcting the wiring at one portion, so that the labor and cost required for the relief can be reduced.

In addition, since the defect of the scan signal output circuit which occupies the largest area in the scan signal line drive circuit can be relieved, the non-defective rate of the scan signal line drive circuit can be dramatically improved.

Further, in the present invention, in the scanning signal line driving circuit, the scanning signal line driving circuit is composed of one or more blocks, and in each block, the scanning circuit and the scanning signal output circuit are connected to the scanning signal line. To connect the scanning signal line to any one of a plurality of adjacent scanning signal output circuits, which is composed of the same number of normal scanning circuits and normal scanning signal output circuits, and one or more preliminary scanning circuits and preliminary scanning signal output circuits. And a switching circuit for connecting the output section of the scanning circuit to the scanning circuit at either the next stage or the next stage. Then, in each block, when there is no defect in the normal scanning circuit and the normal scanning signal output circuit, the normal scanning signal output circuit is connected to the corresponding scanning signal line in advance, and the preliminary scanning signal output circuit is , Not connected to any. At this time, the preliminary scanning circuit performs interlaced scanning. On the other hand, in each block, when there is a defect in the normal scanning circuit or a part of the normal scanning signal output circuit, the normal scanning signal output circuit corresponding to the defective portion is not connected to the scanning signal line but immediately after the defective portion. (Or immediately before) the scan signal output circuit to the preliminary scan signal output circuit are sequentially connected to adjacent scan signal lines. At the same time, the scanning circuit corresponding to the defective portion is interlaced and the preliminary scanning circuit is incorporated so that the scanning is performed normally.

As described above, since the repair of the defect is performed in each block, the number of defects in each block depends on the number of defects in the preliminary scanning circuit and the preliminary scanning signal output circuit in each block even if the number of defects is large. If the number is less than or equal to the number, normal operation as the scanning signal line drive circuit can be obtained.

Further, since the means for sequentially switching the connection of the scanning circuit and the scanning signal output circuit after the defective portion can be dealt with only by correcting the wiring at one portion, the labor and cost required for the relief can be reduced. You can

Further, since it is possible to relieve defects of all the circuit elements constituting the scanning signal line driving circuit, it is possible to dramatically improve the non-defective rate of the scanning signal line driving circuit.

Further, in the data signal line drive circuit, in the structure having the means for outputting the video signal taken in synchronization with the pulse signal as it is to the data signal line,
It is necessary to arrange a very large element as an element for outputting a video signal in the video signal output circuit, but since such an element has a very high probability of occurrence of defects,
The effectiveness of the present invention is increased.

Further, in the data signal line drive circuit, in the structure having means for amplifying the video signal taken in in synchronization with the pulse signal and outputting it to the data signal line, means for amplifying the video signal is required. However, the circuit which constitutes this has a large number of elements and also occupies a large area. Therefore, the probability of occurrence of a defect in the video signal output circuit becomes very high, which increases the effectiveness of the present invention.

Further, in the data signal line drive circuit and the scanning signal line drive circuit, the control of the switching means is made up of a plurality of fuses and resistance elements connected in series between two power supply terminals in each block. Since the means is provided, it is possible to control all the switching means in the block by cutting the fuse only at one place. Therefore, the steps required for defect relief are significantly reduced, and the relief cost is reduced. This is the same when the control means is as follows. A plurality of fuses connected in series between two power supply terminals when the fuse and the resistance element are connected in series between the two power supply terminals, and further another fuse is adjacent to the resistance element. And a resistance element are provided in two systems, and when one system and the other system are provided with potentials in opposite directions, it is composed of a plurality of fuses and resistance elements connected in series between two power supply terminals. In the case where two systems are provided, and one system and the other system are provided with potentials in opposite directions,
A case where a plurality of fuses connected in series between two power supply terminals are provided, an antifuse is provided on one power supply terminal side, and a case where a pair of fuses and an antifuse are provided are applicable. Further, in the image display device of the present invention, since at least one of the data signal line drive circuit and the scanning signal line drive circuit is the above-mentioned data signal line drive circuit or scanning signal line drive circuit, each drive circuit is relieved. As a result, an image display device having a high yield and a high yield rate can be obtained.

In the image display device, the data signal line driving circuit and the scanning signal line driving circuit may be
If at least one of the thin film transistors is a non-single crystal (amorphous or polycrystalline) silicon thin film transistor, the number of defects in the manufacturing process is relatively large, so that the effect of relieving defects in each drive circuit becomes large. This is effective in improving the yield rate of display devices.

[0064]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1A and 1B are diagrams showing a configuration example of a data signal line drive circuit according to the present invention, which corresponds to one block of the data signal line drive circuit. . In FIG. 1, the normal video signal output circuit SDU and the spare video signal output circuit SDUR are parts other than the shift register SR in the data signal line drive circuit (for example, those shown in FIGS. 23 and 24). . In this configuration example, four shift registers SR, four regular video signal output circuits SDU, and one spare video signal output circuit SDU
R and switch circuits (switching circuits) SW1 and SW2 for controlling the respective connections. FIG. 1 (a)
Is a connection state when there is no defect, and FIG.
This is the connection state when there is a defect in the third video signal output circuit from the left.

As shown in FIG. 1A, when there is no defect, all the outputs of the shift register SR are input to the normal video signal output circuit SDU and the data signal line SL.
Are all connected to the regular video signal output circuit SDU. At this time, the preliminary video signal output circuit SDUR is not connected to any of the shift registers SR and the data signal lines SL.

On the other hand, if any of the normal video signal output circuits SDU is defective, as shown in FIG.
The defective video signal output circuit SDU (fail) is separated from the shift register SR and the data signal line SL, and the subsequent normal video signal output circuit SDU is sequentially moved to the previous shift register SR and the data signal line SL.
Further, the shift register SR and the data signal line SL are also connected to the auxiliary video signal output circuit SDUR arranged at the end.

As described above, by connecting the circuit unit after the defective portion to the adjacent circuit unit, the function as a block can be maintained.

2 and 3 show specific examples of the configuration shown in FIG. First, the case of FIG. 2 will be described. Shift register SR and video signal output circuit SDU and SDU
The switching circuit SW1 for controlling the connection with and is composed of an inverter (inverting) circuit and a NAND (negative logical product) circuit. Also, the video signal output circuit SDU and SDUR
Circuit S for controlling the connection between the data signal line SL and the data signal line SL
W2 is composed of a transfer gate.

The control signal of each switching circuit SW1 and SW2 is made up of a plurality of fuses FUS and resistance elements RES which are inserted in series between the power supply VCC and the ground GND. The fuse FUS is normally in a conductive state, and is a fuse that is cut off by some external process (for example, laser irradiation). Actually, as shown in FIG.
-1) and (a-2), it is composed of metal wiring (usually the uppermost metal wiring) having a length and width suitable for cutting {(a-1) is a plane surface. Figure, (a-
2) is a front view}, which is irradiated with a laser (hν),
As shown in (a-3), the conductive state is changed to the cutoff state. Note that the element is arranged apart from other elements so as not to affect characteristics of other elements (transistor or the like) when cut.

If there is no defect in the video signal output circuit SDU, none of the fuses FUS is cut. For this reason,
Due to the resistance element RES, all control signals become high level. At this time, all shift registers SR and data signal lines SL are connected to the left video signal output circuit SDU. On the other hand, if any of the video signal output circuits SDU (for example, the third from the left) is defective, the corresponding (third from the left) fuse FUS is cut. As a result, the control signal after the disconnection point is set to the low level. As a result, the shift register SR and the data signal line SL before the disconnection point are connected to the left video signal output circuit SDU, and the shift register SR and the data signal line SL after the disconnection point are the right video signal output circuit SDU. SDU or S
Connected to DUR.

As described above, even if the video signal output circuit SDU is defective, the normal operation of the block of the data signal line drive circuit can be obtained.

Although the transfer gate is composed of an n-channel type transistor in FIG. 2, in particular, in the switching circuit SW2 for transferring the video signal, from the viewpoint of driving capability, the n-channel type transistor and the p-channel type transistor are used. A CMOS configuration in which type transistors are connected in parallel is preferable. This is the same in the following embodiments.

Next, the case of FIG. 3 will be described. The switching circuit SW1 for controlling the connection between the shift register SR and the video signal output circuits SDU and SDU and the switching circuit SW2 for controlling the connection between the video signal output circuits SDU and SDUR and the data signal line SL are both transfer gates. It consists of The control signals of the switching circuits SW1 and SW2 and the operation principle thereof are the same as those in the example of FIG. In this embodiment, only the video signal output circuit SDU can be relieved (the scanning circuit such as the shift register cannot be relieved), but in the normal data signal output circuit, the video signal output circuit SDU occupies most of the area. Also, the probability of occurrence of defects is overwhelmingly large in the video signal output circuit SDU, and redundancy in this portion alone is sufficiently effective. As for the redundancy of the shift register section, a combination of the technique disclosed in the first embodiment and the technique disclosed in Japanese Patent Laid-Open No. 6-83286 may be used in addition to the second embodiment described below.

(Embodiment 2) FIGS. 5A and 5B are diagrams showing another configuration example of the data signal line drive circuit according to the present invention, in which one block of the data signal line drive circuit is shown. Correspond. Similar to the first embodiment, in FIG. 5, the normal video signal output circuit SDU and the spare video signal output circuit SDUR are shown.
Is a data signal line drive circuit (for example, FIG. 23 and FIG.
4 and the like) except for the shift register SR. In the present configuration example, four normal shift registers SR, one spare shift register SRR, four normal video signal output circuits SDU, and one spare video signal output circuit SDUR are controlled respectively. Switch circuits SW1 and SW2. Each shift register is fixedly connected to each corresponding video signal output circuit.

FIG. 5A shows a connection state when there is no defect, and FIG. 5B shows a connection state when there is a defect in the third shift register or the video signal output circuit from the left. As shown in FIG. 5A, when there is no defect, all normal shift registers SR are in the operating state, and the spare shift register SRR is interlaced and scanned. All the data signal lines SL are normal shift registers SR.
Is connected to the regular video signal output circuit SDU connected to. At this time, the spare video signal output circuit SDUR
Are not connected to any of the data signal lines SL.

On the other hand, if either the normal shift register SR or the normal video signal output circuit SDU (third from the left) is defective, as shown in FIG. 5B, the defective shift register SR or , The shift register SR corresponding to the defective video signal output circuit SDU is interlaced and scanned, and the normal video signal output circuit SD after the defective portion is scanned.
The U can sequentially switch the connection to the immediately previous data signal line SL. Further, the spare shift register SRR is activated, and the data signal line SL is also connected to the spare video signal output circuit SDUR arranged at the end.

In this way, the circuit unit after the defective portion is interlaced and scanned, and the adjacent circuit units are connected to each other, whereby the function as a block can be maintained.

6 and 7 show specific examples of the configuration shown in FIG. First, the case of FIG. 6 will be described. The switching circuit SW1 for controlling the interlaced scanning of the shift registers SR and SRR includes an inverter (inverting) circuit and an N
AND (Negative AND) circuit, OR-NAND (OR /
Negative AND) circuit. Further, the switching circuit SW2 for controlling the connection between the video signal output circuits SDU and SDUR and the data signal line SL is composed of a transfer gate.

The control signal of each switching circuit SW1 and SW2 is made up of a plurality of fuses FUS and a resistance element RES which are inserted in series between the power supply VCC and the ground GND, as in the first embodiment. That is, when there is no defect in the shift register SR or the video signal output circuit SDU, none of the fuses FUS is blown, so that all the control signals become high level by the resistance element RES. At this time, all normal shift registers SR operate normally, and the spare shift register SRR is interlaced. Further, the data signal line SL is connected to the regular video signal output circuit SDU on the left side, and the spare video signal output circuit SDU is connected.
Not connected to R.

On the other hand, if any of the shift register SR or the video signal output circuit SDU (for example, the third from the left) is defective, the corresponding (third from the left) fuse FUS is cut off. The control signal after the disconnection point is set to low level. As a result, the shift register SR corresponding to the cut position is interlaced and scanned, and the spare shift register SRR operates. Also,
The data signal line SL at the cutting point is connected to the left video signal output circuit SDU, and the data signal line SL after the cutting point is at the right video signal output circuit SDU or SDU.
Connected to. As described above, even if there is a defect in the shift register or the video signal output circuit, normal operation as a block of the data signal line drive circuit can be obtained.

Next, the case of FIG. 7 will be described. Switching circuit SW1 for controlling interlaced scanning of shift registers SR and SRR, and video signal output circuits SDU and SDU
The switching circuit SW2 for controlling the connection between R and the data signal line SL is composed of a transfer gate.

The control signals of the switching circuits SW1 and SW2, and the operating principle thereof are the same as those in the above-mentioned embodiment, and therefore will be omitted.

In this embodiment, not only the video signal output circuit but also the scanning circuit (shift register) can be repaired, so that the repair rate is high.

(Embodiment 3) FIGS. 8A and 8B are diagrams showing a configuration example of a scanning signal line driving circuit according to the present invention, which corresponds to one block of the scanning signal line driving circuit. .
In FIG. 8, the normal scanning signal output circuit GDU and the preliminary scanning signal output circuit GDUR are provided in the scanning signal line driving circuit (for example, the one shown in FIG. 26) in the shift register S.
It is a part other than R. In this configuration example, four shift registers SR, four normal scanning signal output circuits GDU, 1
The pre-scanning signal output circuit GDUR and the switch circuits SW1 and SW2 for controlling the respective connections. FIG. 8A shows a connection state when there is no defect, and FIG. 8B shows a connection state when there is a defect in the third scanning signal output circuit from the left.

As shown in FIG. 8A, when there is no defect, all the outputs of the shift register SR are input to the normal scanning signal output circuit GDU and all the scanning signal lines GL are supplied with the regular scanning signal. It is connected to the output circuit GDU.
At this time, the preliminary scanning signal output circuit GDUR is not connected to any of the shift register SR and the scanning signal line GL.

On the other hand, if any one of the normal scanning signal output circuits GDU (third from the left) is defective, FIG.
As shown in (b), the defective scanning signal output circuit GDU
(Fail) is the shift register SR and the scanning signal line GL
And the subsequent normal scanning signal output circuit GDU is sequentially switched to the previous shift register SR and the scanning signal line GL, and further, the preliminary scanning signal output circuit GDU is arranged at the end. Also, the shift register SR and the scanning signal line GL are connected.

As described above, by connecting the circuit unit after the defective portion to the adjacent circuit unit, the function as a block can be maintained.

9 and 10 show specific examples of the configuration shown in FIG. First, the case of FIG. 9 will be described. The switching circuit SW1 for controlling the connection between the shift register SR and the scanning signal output circuits GDU and GDU is composed of an inverter (inversion) circuit and a NAND (negative logic multiplication) circuit. Further, the scanning signal output circuits GDU and G
The switching circuit SW2 that controls the connection between the DUR and the scanning signal line GL is composed of a NAND circuit.

The control signal of each switching circuit SW1 and SW2 is made up of a plurality of fuses FUS and a resistance element RES which are inserted in series between the power supply VCC and the ground GND. When the scanning signal output circuit GDU has no defect, none of the fuses FUS is cut, and the resistance element RES causes all the control signals to be at a high level.
At this time, all shift registers SR and scanning signal lines G
L is connected to the left scanning signal output circuit GDU.

On the other hand, if one of the scanning signal output circuits GDU (for example, the third one from the left) is defective, the corresponding (third from the left) fuse FUS is cut off to cut the fuses after the cut point. Bring the control signal low. As a result, the shift register SR and the scanning signal line SL before the cutting point are connected to the left scanning signal output circuit GDU, and the shift register SR and the scanning signal line GL after the cutting point are the right scanning signal output circuit GDU. GDU or GD
Connected to UR. As described above, even if the scanning signal output circuit has a defect, it is possible to obtain a normal operation as a block of the scanning signal line drive circuit GDU.

Next, the case of FIG. 10 will be described. The switching circuit SW1 that controls the connection between the shift register SR and the scanning signal output circuits GDU and GDU and the switching circuit SW2 that controls the connection between the scanning signal output circuits GDU and GDU and the scanning signal line GL are both transfer gates. It consists of

The control signals of the switching circuits SW1 and SW2 and the operating principle thereof are the same as those in the example of FIG.

In this embodiment, only the scanning signal output circuit GDU can be relieved (the scanning circuit such as the shift register SR cannot be relieved), but in the normal scanning signal line drive circuit, most of the scanning signal output circuit is provided. Since the area occupies an area, the probability of occurrence of a defect is overwhelmingly large in the scanning signal output circuit, and redundancy of this portion is sufficiently effective. In particular, in a multi-scan display device in which the scanning method can be changed depending on the type of image, the scanning signal line drive circuit may include a complicated logic circuit. In that case, the area occupied by the scanning signal output circuit is increased. Will be even larger. Further, as for the redundancy of the shift register section, a combination of the third embodiment and the technique disclosed in Japanese Patent Laid-Open No. 6-83286 may be used in addition to the one shown in the fourth embodiment described below.

Example 4 FIGS. 11A and 11B show
It is a figure showing other examples of composition of a scanning signal line drive circuit concerning the present invention, and corresponds to one block of a scanning signal line drive circuit. Similar to the third embodiment, in FIG. 11, the normal scanning signal output circuit GDU and the preliminary scanning signal output circuit GDUR are shown.
Is a part other than the shift register SR in the scanning signal line drive circuit (for example, the one shown in FIG. 26). In this configuration example, four normal shift registers SR, one preliminary shift register SRR, four normal scanning signal output circuits GDU, and one preliminary scanning signal output circuit GDU
And switch circuits SW1 and SW2 for controlling each connection. Each shift register is fixedly connected to each corresponding scan signal output circuit. FIG. 11A shows a connection state when there is no defect, and FIG. 11B shows a connection state when there is a defect in the third shift register or scanning signal output circuit from the left.

As shown in FIG. 11A, when there is no defect, all the normal shift registers SR are in the operating state, and the spare shift register SRR is interlaced and scanned. The scanning signal lines GL are all connected to the normal scanning signal output circuit GDU connected to the normal shift register SR. At this time, the preliminary scanning signal output circuit GD
UR is not connected to any scanning signal line GL.

On the other hand, when either the normal shift register SR or the normal scanning signal output circuit GDU (third from the left) is defective, as shown in FIG. 11B, the defective shift register SR or , A shift register SR corresponding to a defective scanning signal output circuit GDU (fail)
However, the interlaced scanning is performed, and the normal scanning signal output circuit GDU after the defective portion is sequentially scanned by the previous scanning signal line G.
The connection can be switched to L. Further, the preliminary shift register SRR becomes operable, and the scanning signal line SL is also connected to the preliminary scanning signal output circuit GDUR arranged at the end.

In this way, the circuit unit after the defective portion is interlaced and scanned, and is connected to the adjacent circuit unit, whereby the function as a block can be maintained.

12 and 13 show specific examples of the configuration shown in FIG. First, the case of FIG. 12 will be described. The switching circuit SW1 that controls the interlaced scanning of the shift registers SR and SRR includes an inverter (inverting) circuit, a NAND (negative logical product) circuit, and an OR-NAND.
It is composed of a (logical sum / negative logical product) circuit. The switching circuit SW2 that controls the connection between the scanning signal output circuits GDU and GDU and the scanning signal line GL is composed of a NAND circuit.

The control signals of the switching circuits SW1 and SW2 are made up of a plurality of fuses FUS and resistance elements RES which are inserted in series between the power supply VCC and the ground GND, as in the third embodiment. That is, when there is no defect in the shift register SR or the scanning signal output circuit GDU, none of the fuses FUS is blown, so that all the control signals become high level by the resistance element RES.
At this time, all normal shift registers SR operate normally, and the spare shift register SRR is interlaced.
Further, the scanning signal line GL is connected to the regular scanning signal output circuit GDU on the left side and is not connected to the preliminary scanning signal output circuit GDUR.

On the other hand, if any of the shift register SR or the scanning signal output circuit GDU (for example, the third one from the left) is defective, the corresponding (third from the left) fuse FUS is cut off. The control signal after the disconnection point is set to low level. As a result, the shift register corresponding to the cut position is interlaced and scanned, and the spare shift register SRR is activated. In addition, the scanning signal line GL at the cut portion is provided on the left side with the scanning signal output circuit GD.
Scan signal line GL connected to U and after the disconnection point
Is connected to the scanning signal output circuit GDU or GDU on the right side. As described above, even if the shift register or the scanning signal output circuit has a defect, it is possible to obtain a normal operation as a block of the scanning signal line driving circuit.

Next, the case of FIG. 13 will be described. Switching circuit SW1 for controlling interlaced scanning of shift registers SR and SRR, and scanning signal output circuits GDU and GD
Switching circuit S for controlling connection between UR and scan signal line GL
Both W2 are composed of transfer gates. The control signals of the switching circuits SW1 and SW2, and the operation principle thereof are the same as those in the above-described embodiment, and therefore will be omitted.

In the present embodiment, not only the scanning signal output circuit but also the defect of the scanning circuit (shift register) can be relieved, so that the relief rate becomes high.

In the above embodiment, one block is 4
Although it is composed of a circuit for driving the data signal lines, it is not limited to this, and any number of data signal lines may be supported. However, if the number of data signal lines in one block is large, the probability that a defect can be remedied is low, and conversely, if the number of data signal lines in one block is small, the area increases significantly due to the redundant circuit. It is necessary to select the optimum block configuration for the defect occurrence rate in this process.

Further, in the above embodiment, only one spare circuit is arranged at the tail end of one block, but the position of this spare circuit may be anywhere or plural. Good.

Further, in the first and third embodiments, the example of the shift register is given as the scanning circuit, but the present invention is not limited to this, and it can be applied to the case where another scanning circuit, for example, a decoder type scanning circuit is used. .

As described above, according to the present invention, for one defect, it is sufficient to cut the fuse at one position, and the trouble at the time of defect repair is greatly reduced.

In each of the above embodiments, the switching means is controlled by cutting the fuse. Here, as the fuse, a metal wiring used in the drive circuit, for example, an aluminum wiring may be used as it is. Laser light such as a YAG laser can be used as a means for blowing the fuse. Of course, other configurations, materials and methods may be used as long as the switching means can be controlled.

(Fifth Embodiment) A modification of the fifth embodiment to the following eleventh embodiment for a data signal line drive circuit will be described. In addition, Example 5 to Example 1
The modifications up to 1 can be similarly applied to the scanning line drive circuit.

FIG. 14 is a diagram showing one block of the data signal line drive circuit according to the fifth embodiment. In this block, the fuse FUS is provided adjacent to the resistance element RES in the control means including a plurality of fuses FUS and resistance elements RES connected in series between the power supply VCC and the ground GND. .

In this case, when the block is not defective, the fuse FUS adjacent to the resistance element RES is cut off. On the other hand, when a block has a defect,
Since one fuse FUS is surely cut off somewhere, there is no current path between the power supply VCC and the ground GND, and a steady current (through current) hardly flows. Therefore, the power consumption can be reduced.

(Sixth Embodiment) FIG. 15 is a diagram showing one block of a data signal line drive circuit according to the present embodiment. In this block, power supply VCC and ground GND
Two control means including a plurality of fuses FUS and a resistance element RES connected in series between and are provided, and the potential directions of the respective control means are opposite to each other.

In this case, the defect relief is paired with 2
The fuses FUS are cut at the same time. Since the control signal and its inverted signal can be separately generated by the two control means, an inverting circuit (inverter) for generating the inverted signal becomes unnecessary. That is, since the control means does not include a transistor and is composed only of wiring, the probability that the control circuit itself becomes defective is extremely small, and the repair rate is improved. However, in order to remedy defects, 2
It is necessary to cut the individual fuse FUS. However, depending on the shape and arrangement of the fuses FUS (such as arranging them close to each other), it is possible to cut two fuses FUS in a single process (laser irradiation, etc.), thus suppressing an increase in cost. To be

(Embodiment 7) FIG. 16 is a diagram showing one block of a data signal line drive circuit according to the present embodiment. This block has a configuration in which the fifth and sixth embodiments described above are combined.

In this case as well, it is needless to say that the object of the present invention can be achieved by making it similar to the fifth and sixth embodiments, and the description thereof will be omitted.

(Embodiment 8) FIG. 17 is a diagram showing one block of a data signal line drive circuit according to the present embodiment 8. As shown in FIG. This block has a configuration in which the switching means SW1 and SW2 in the configuration of the fifth embodiment described above are CMOS in which an n-channel transistor and a p-channel transistor are connected in parallel.

In this case, the signal transfer rate increases. Further, since the transferable signal amplitude also becomes large, it is particularly effective for the switching means (SW2) on the data signal line side of the data signal line drive circuit for transferring the analog signal.
This does not necessarily have to be applied to both the switching means SW1 and SW2, and only one switching means (normally SW2) may be used.

(Embodiment 9) FIG. 29 is a diagram showing one block of a data signal line drive circuit according to the present embodiment 8. This block reverses the high potential side and the low potential side of the configuration shown in FIG.
The ES is provided on the high potential side. Even in this case, the same effect as that of FIG. 3 can be obtained.

The above arrangement can be similarly applied to each of the above-described first to eighth embodiments. As one example, it can be as shown in FIG.

FIG. 30 is a diagram in which the configuration of the ninth embodiment is applied to the configuration of FIG. In this FIG. 30, the same effect as in FIG. 14 can be obtained.

(Embodiment 10) FIG. 18 is a diagram showing one block of a data signal line drive circuit according to the tenth embodiment. This block includes switching means SW1 and SW2.
In the control means, the anti-fuse AF is provided instead of the resistance element. That anti-fuse AF
Is the opposite of the fuse FUS, which is normally in the cutoff state,
It is brought into a conductive state by laser irradiation or the like. For example, as shown in (b-1) and (b-2) of FIG. 4, the anti-fuse AF is composed of two-layer metal wirings stacked with a thin insulating film interposed between {(b-1) Plan view, (b-2) is a front view}. By irradiating this with a laser or the like, the insulating film is destroyed, and the upper metal wiring and the lower metal wiring are electrically connected as shown in FIG. 4B-3.

In the case of this embodiment, when a defect occurs in the block, the fuse FUS at the corresponding location is cut and the anti-fuse AF is made conductive. As a result, as in the case of the fifth embodiment, the steady current does not flow, so that the power consumption can be reduced. Further, it is necessary to process two locations (laser irradiation, etc.) in one block, but it is not necessary to modify a block having no defect. Therefore, when the number of defects is relatively small, it is better than in the case of the fifth embodiment. Can also be low cost. Further, the present invention may have a configuration in which the antifuse AF is provided on the high potential side.

(Embodiment 11) FIG. 19 is a diagram showing one block of a data signal line drive circuit according to the present embodiment. This block has a configuration in which a control circuit for controlling the switching means SW1 and SW2 is provided for each of the switching means SW1 and SW2, that is, one shift register SR or one data signal line SL.

In this structure, if a block is defective, all the fuses after the defective portion may be cut off.

(Embodiment 12) FIG. 20 shows a switching means S.
As the W1 and SW2, the fuse FUS and the anti-fuse AF are directly used without using a transistor.

In the case of this structure, in order to relieve a defect, all the fuses FUS after the defective part are cut, and at the same time, all the antifuses AF after the defective part are made conductive.

In the case of the present embodiment, as compared with the eleventh embodiment, the circuit (transistor) accompanying the provision of the redundancy mechanism.
The addition of is eliminated and the area can be kept small.

The above-mentioned fifth and sixth embodiments and eighth to eleventh embodiments are also included in the scope of the present invention when combined with each other. Example 7
Shows the configuration when the fifth and sixth embodiments are combined. The fifth to eleventh embodiments described above are modifications of the configuration shown in FIG. 3, but FIG. 2, FIG. 6, FIG. 7, FIG. 9, FIG. 10, FIG. 12, FIG. The same can be applied to the case of modifying the configuration in the case.

(Example 13) Example 13 according to the present invention
Is an image display device using at least one of a data signal line driving circuit and a scanning signal line driving circuit according to the present invention. The block configuration of this embodiment is shown in FIGS.
This is similar to the conventional image display device shown in FIG. By adopting such a configuration as the image display device, it becomes possible to remedy defects that have occurred in the data signal line drive circuit SD and the scanning signal line drive circuit GD, so that the occurrence probability of line defects is greatly increased. It can be reduced.

Further, when the present technology is applied to a circuit composed of a polycrystalline silicon thin film transistor, it is very effective for occurrence of defects at a high frequency due to process defects.

Here, as a mode in which a polycrystalline silicon thin film transistor is used as a constituent element of a drive circuit of an image display device, in addition to a monolithic structure formed on the same glass substrate as the pixel array, it is formed on another glass substrate. An example is a GOG (glass on glass) structure in which the formed drive circuit is mounted on the pixel array substrate.

Although some examples of the present invention have been shown above, the present invention is not limited to the above examples,
It applies to all configurations based on the same concept.

[0133]

According to the present invention, the drive circuit is composed of one or more blocks, and in each block,
Arrange the same number of normal drive circuit units as the signal lines and one or more preliminary drive circuit units, and if the normal drive circuit is defective, connect the subsequent drive circuit units to the next drive circuit unit in sequence. Since the means for switching is provided, this makes it possible to relieve even when there are a plurality of defects in the drive circuit, and the number of steps for relieving is reduced, so that the relief rate and the relief cost can be improved. Further, when the preliminary drive circuit is used, the configuration is switched to the adjacent drive circuit unit, so there is no detour in the signal path, and there is almost no signal delay due to the technique of the present invention.

As described above, the defect of the drive circuit caused by the defect generated during the manufacturing process can be relieved with a high probability at a low cost and with almost no adverse effect on others, so that the non-defective rate can be improved. It is possible to obtain a high image display device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of one block of a data signal line drive circuit according to the present invention, where (a) is a case where there is no defect in the block and (b) is a case where there is a defect.

FIG. 2 is a diagram showing a specific circuit configuration example of a data signal line drive circuit in FIG.

FIG. 3 is a diagram showing another specific circuit configuration example of the data signal line drive circuit of FIG.

4 (a-1) to (a-3) are diagrams showing a configuration of a fuse, and (b-1) to (b-3) are diagrams showing a configuration of an anti-fuse.

FIG. 5 is a diagram showing another configuration example of one block of the data signal line drive circuit according to the present invention, where (a) shows a case where there is no defect in the block and (b) shows a case where there is a defect. .

6 is a diagram showing a specific circuit configuration example of the data signal line drive circuit of FIG.

FIG. 7 is a diagram showing another specific circuit configuration example of the data signal line drive circuit of FIG.

FIG. 8 is a diagram showing a configuration example of one block of the scanning signal line drive circuit according to the present invention, where (a) is a case where there is no defect in the block and (b) is a case where there is a defect.

9 is a diagram showing a specific circuit configuration example of the scanning signal line drive circuit of FIG.

10 is a diagram showing another specific circuit configuration example of the scanning signal line drive circuit of FIG.

FIG. 11 is a diagram showing another configuration example of one block of the scanning signal line drive circuit according to the present invention, where (a) shows a case where there is no defect in the block and (b) shows a case where there is a defect. .

12 is a diagram showing a specific circuit configuration example of the scanning signal line drive circuit of FIG.

13 is a diagram showing another specific circuit configuration example of the scanning signal line drive circuit of FIG.

FIG. 14 is a data signal line drive circuit 1 according to the fifth embodiment.
It is a figure which shows the structural example of a block.

FIG. 15 is a data signal line drive circuit 1 according to the sixth embodiment.
It is a figure which shows the structural example of a block.

FIG. 16 is a data signal line drive circuit 1 according to the seventh embodiment.
It is a figure which shows the structural example of a block.

FIG. 17 is a data signal line drive circuit 1 according to the eighth embodiment.
It is a figure which shows the structural example of a block.

FIG. 18 is a diagram illustrating a configuration example of one block of the data signal line drive circuit according to the tenth embodiment.

FIG. 19 is a diagram showing a configuration example of one block of a data signal line drive circuit according to an eleventh embodiment.

FIG. 20 is a diagram illustrating a configuration example of one block of a data signal line drive circuit according to a twelfth embodiment.

FIG. 21 is a block diagram showing a configuration of the present invention and a conventional liquid crystal display device.

22A is a diagram showing a configuration of the present invention and a conventional liquid crystal display device, and FIG. 22B is a diagram showing a pixel configuration thereof.

FIG. 23 is a diagram showing a configuration example of a data signal line drive circuit of a dot sequential drive system in a conventional liquid crystal display device.

FIG. 24 is a diagram showing a configuration example of a data signal line drive circuit of a line sequential drive system in a conventional liquid crystal display device.

25 is a diagram showing a configuration example of an amplifier circuit in the data signal line drive circuit shown in FIG. 24.

FIG. 26 is a diagram showing a configuration example of a scanning signal line drive circuit in a conventional liquid crystal display device.

27 is a diagram showing a configuration example of a scanning circuit (shift register) used in the data signal line driving circuit shown in FIGS. 23 and 24 and the scanning signal line driving circuit shown in FIG. 26.

FIG. 28 is a diagram showing a configuration example of a decoder circuit which is another system of the scanning circuit.

FIG. 29 is a first example of the data signal line drive circuit according to the ninth embodiment.
It is a figure which shows the structural example of a block.

FIG. 30 is a diagram in which the configuration of the ninth embodiment is applied to the configuration of FIG. 14, and is a diagram illustrating a configuration example of one block of a data signal line drive circuit.

[Explanation of symbols]

SR Normal shift register SRR Preliminary shift register SDU Normal video signal output circuit SDUR Preliminary video signal output circuit GDU Normal scanning signal output circuit GDUR Preliminary scanning signal output circuit SW1, SW2 switching circuit SL Data signal line GL scanning signal line FUS Fuse RES Resistor element VCC power supply voltage terminal GND ground terminal ARY pixel array GD scanning signal line drive circuit SD data signal line drive circuit TIM timing signal generation circuit DAT video signal SYN timing signal PIX pixel CKS, CKG clock signal SPS, SPG start pulse signal GPS pulse signal VGH Scan signal line circuit High potential VGL Scan signal line circuit Low potential VSH Data signal line circuit High potential VSL Data signal line circuit Low potential CL Liquid crystal capacitance CS Auxiliary capacitance SW Pixel transistor Star LAT latch circuit SWT sampling circuit TRF transfer signal AMP amplifier circuit CSAMP, Chold storage capacitor BUF buffer circuit CLK, / CLK clock signals A1, A2 ..., A1 , A2 ... Address signals TR1a, TR1b ... Transistors Vb1a, Vb1b ... Bias voltage

Claims (20)

[Claims] 1. One or more comprising: a scanning circuit which outputs a pulse signal in time series; and a video signal output circuit which captures a video signal in synchronization with the pulse signal and outputs the video signal to a data signal line. Of blocks, each block having the same number of normal video signal output circuits as the scanning circuits and the data signal lines, one or more spare video signal output circuits, and the scanning circuits and the data signal lines adjacent to each other. And a switching means for connecting to any one of the plurality of video signal output circuits. 2. One or more having a scanning circuit for outputting a pulse signal in time series, and a video signal output circuit for capturing a video signal in synchronization with the pulse signal and outputting the video signal to a data signal line. Each block includes the same number of normal scanning circuits and the same number of normal video signal output circuits as the data signal lines, one or more preliminary scanning circuits and preliminary video signal output circuits, and the data signal lines. Switching means for connecting to any of the plurality of adjacent video signal output circuits, and second for connecting the scanning circuit to any of the plurality of adjacent video signal output circuits
A data signal line driving circuit having a switching circuit. 3. The data signal line drive circuit according to claim 1, wherein the control means for controlling the switching means includes a plurality of fuses and resistance elements connected in series between two power supply terminals. 4. The data signal line drive according to claim 2, wherein the control means for controlling the switching means and the second switching means comprises a plurality of fuses and resistance elements connected in series between two power supply terminals. circuit. 5. The control means for controlling the switching means and the second switching means comprises a plurality of fuses and resistance elements connected in series between two power supply terminals, and further adjacent to the resistance element. The data signal line drive circuit according to claim 2, further comprising another fuse. 6. The control means for controlling the switching means and the second switching means includes two systems each including a plurality of fuses and resistance elements connected in series between two power supply terminals, and one system. 3. The data signal line drive circuit according to claim 2, wherein the potential of the other system is opposite to that of the other system. 7. The control means for controlling the switching means and the second switching means includes a plurality of fuses connected in series between two power supply terminals and an antifuse on one power supply terminal side. Item 2. The data signal line drive circuit according to Item 2. 8. The data signal line drive circuit according to claim 2, wherein the control means for controlling the switching means and the second switching means comprises a pair of fuse and antifuse. 9. The data signal line drive circuit according to claim 1, further comprising means for outputting the video signal, which is captured in synchronization with the pulse signal, to the data signal line as it is. 10. The data signal line drive circuit according to claim 1, further comprising means for amplifying a video signal captured in synchronization with the pulse signal and outputting the amplified video signal to a data signal line. 11. A scanning circuit that outputs a pulse signal in time series, and a scanning signal line sequentially in synchronization with the pulse signal,
A scan signal output circuit for outputting a scan signal, and each block is composed of one or more blocks, and each block has the same number of normal scan signal output circuits as the scan circuits and the scan signal lines, and one or more preliminary scans. The signal output circuit, the scanning circuit and the scanning signal line, respectively,
A scanning signal line drive circuit having switching means for connecting to any one of a plurality of adjacent scanning signal output circuits. 12. A scanning circuit that outputs a pulse signal in time series, and a scanning signal line sequentially in synchronization with the scanning signal,
A scan signal output circuit for outputting a scan signal, and each block is composed of one or more blocks, and each block has the same number of normal scan circuits and the same number of normal scan signal output circuits as the scan signal lines and one or more blocks. Preliminary scanning circuit and preliminary scanning signal output circuit, switching means for connecting the scanning signal line to any of a plurality of adjacent scanning signal output circuits, and a plurality of scanning signal output circuits adjacent to the scanning circuit And a second switching circuit for connecting to any of the above. 13. The scanning signal line drive circuit according to claim 11, wherein the control means for controlling the switching means includes a plurality of fuses and resistance elements connected in series between two power supply terminals. 14. The scanning signal line drive according to claim 12, wherein the control means for controlling the switching means and the second switching means comprises a plurality of fuses and resistance elements connected in series between two power supply terminals. circuit. 15. The control means for controlling the switching means and the second switching means comprises a plurality of fuses and resistance elements connected in series between two power supply terminals, and further adjacent to the resistance element. The scanning signal line drive circuit according to claim 12, further comprising another fuse. 16. The control means for controlling the switching means and the second switching means includes two systems each including a plurality of fuses and resistance elements connected in series between two power supply terminals, and one system. 13. The scanning signal line drive circuit according to claim 12, wherein the other system is provided with a potential opposite to that of the other system. 17. The control means for controlling the switching means and the second switching means includes a plurality of fuses connected in series between two power supply terminals and an antifuse on one power supply terminal side. Item 12. The scanning signal line drive circuit according to Item 12. 18. The scanning signal line drive circuit according to claim 12, wherein the control unit that controls the switching unit and the second switching unit includes a pair of fuse and antifuse. 19. An active matrix comprising display pixels arranged in a matrix, a data signal line drive circuit for applying a video signal to the pixels, and a scanning signal line drive circuit for controlling writing to the pixels. An image display apparatus, wherein at least one of the data signal line drive circuit and the scanning signal line drive circuit is the one according to any one of claims 1 to 17. 20. The image display device according to claim 19, wherein at least one of the data signal line drive circuit and the scanning signal line drive circuit is formed of a non-single crystal silicon thin film transistor.