JP2009205001A - Drive circuit and display device provided with the drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit which can be self-repaired when a defective video signal output part is detected and is capable of more simplifying wiring lines connected to the video signal output parts. <P>SOLUTION: The drive circuit 10 includes output terminals OUT1 to OUT18, 19 video signal output parts, including output circuits 11_1 to 11_19, respectively; a decision part decision quality of the respective video signal output parts and switches SWB1 to SWB18 switching connection of the output terminals and the video signal output parts, according to the decision result by the decision part, wherein when it is determined by the decision part that the i-th video signal output part (i is a natural number of m or smaller) is defective, the switches SWB1 to SWB18 connects the j-th video signal output part (j is a natural number of i-1 or smaller) to the j-th output terminal and connects (k+1)-th video signal output part (k is a natural number of 18 or smaller) to the k-th output terminal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a drive circuit for driving a display device that self-detects a defect and performs self-repair, and a display device including the drive circuit.

  In recent years, with the increase in size and definition of liquid crystal panels and the like, in the semiconductor integrated circuit for liquid crystal drive, the number of output terminals for liquid crystal drive has increased, and the multi-value voltage output from the output terminal has been increased in multiple gradations. Progressing. For example, some of the currently mainstream liquid crystal driving semiconductor integrated circuits have about 500 output terminals capable of outputting 256 gray scale voltages. Further, development of a semiconductor integrated circuit for driving a liquid crystal having 1000 or more output terminals is currently underway. Also, development of a semiconductor integrated circuit for driving a liquid crystal capable of outputting 1024 gradations has been carried out with the increase in the color of the liquid crystal panel.

  Here, the configuration of a conventional semiconductor integrated circuit for driving a liquid crystal will be described below with reference to FIG. FIG. 28 is a block diagram showing a configuration of a conventional semiconductor integrated circuit for driving a liquid crystal.

  The liquid crystal driving semiconductor integrated circuit 101 shown in FIG. 1 can output m gray scale output voltages from n liquid crystal driving signal output terminals. First, the configuration of the liquid crystal driving semiconductor integrated circuit 101 will be described. A liquid crystal driving semiconductor integrated circuit 101 includes an external clock input terminal 102, a gradation data input terminal 103 having a plurality of signal input terminals, a LOAD signal input terminal 104, and V0 terminals 105 and V1 terminals which are reference power supply terminals. 106, a V2 terminal 107, a V3 terminal 108, and a V4 terminal 109. Further, the liquid crystal driving semiconductor integrated circuit 101 includes n liquid crystal driving signal output terminals 111-1 to 111-n (hereinafter, the liquid crystal driving signal output terminals are referred to as signal output terminals. Further, the liquid crystal driving signal output is output. Terminals 111-1 to 111-n are collectively referred to as signal output terminals 111). The liquid crystal driving semiconductor integrated circuit 101 includes a reference power supply correction circuit 121, a pointer shift register circuit 123, a latch circuit unit 124, a hold circuit 125, and a D / A converter (Digital Analog Converter: hereinafter referred to as DAC) circuit. 126 and an output buffer 127. The pointer shift register circuit 123 includes n-stage shift register circuits 123-1 to 123-n. Further, the latch circuit unit 124 includes n latch circuits 124-1 to 124-n, and the hold circuit 125 includes n hold circuits 125-1 to 125-n. The DAC circuit 126 includes n DAC circuits 126-1 to 126-n. In addition, the output buffer 127 is composed of n output buffers 127-1 to 127-n, and each output buffer 127 is composed of an operational amplifier.

  Next, the operation of the liquid crystal driving semiconductor integrated circuit 101 will be described. The pointer shift register circuit 123 sequentially selects from the first latch circuit 124-1 to the nth latch circuit 124-n based on the clock input signal input from the clock input terminal 102. The latch circuit 124 selected by the pointer shift register circuit 123 stores the gradation data from the gradation data input terminal 103. The gradation data corresponds to each latch circuit 124, in other words, corresponds to each signal output terminal 111 and is data synchronized with the clock input signal. In addition, each of the latch circuits 124-1 to 124-n outputs gradation data having different values corresponding to each of the signal output terminals 111 to hold circuits connected to the respective latch circuits. Each of the hold circuits 125 to which the gradation data is input outputs the digital data to the DAC circuits 126-1 to 126-n based on the data LOAD signal.

  Here, the DAC circuits 126-1 to 126-n select one voltage value from m kinds of gradation voltages based on the gradation data from the hold circuit 125, and output to the output buffers 127-1 to 127-n. Output. Note that the DAC circuit 126 can output m types of gradation voltages depending on the voltages input from the reference power supply terminals V0 terminal 105 to V4 terminal 109. Next, the output buffer 127 buffers the gradation voltage from the DAC circuit 126 and outputs it as a liquid crystal driving signal to the signal output terminals 111-1 to 111-n.

  Next, FIG. 29 illustrates a specific configuration example of the shift register 123, the latch circuit 124, and the hold circuit 125.

  FIG. 29 shows the configuration of the liquid crystal driving semiconductor integrated circuit 101 having 18 outputs from the liquid crystal driving signal output terminals OUT1 to OUT18. Pointer shift registers DF_1 to DF_18 (hereinafter collectively referred to as pointer shift register DF) provided in the liquid crystal driving semiconductor integrated circuit 101 correspond to the pointer shift register circuit 123 shown in FIG. 28, and are latch circuits DLA_1. ~ DLA_18 (hereinafter collectively referred to as latch circuit DLA) corresponds to latch circuit 124 shown in FIG. 28, and hold circuits DLB_1 to DLB_18 (hereinafter collectively referred to as hold circuit DLB) are shown in FIG. The output circuits 11_1 to 18 correspond to the DAC circuit 126 and the output buffer 127 shown in FIG. 28 and are input from a start pulse signal line (SP signal line) indicating the start timing of the pointer shift register. Operation start signal (SP signal), and The operation clock signal input from the clock signal line (CLK signal line) corresponds to the shift clock input signal shown in FIG. 28, and the gradation data input from the DATA signal line corresponds to the gradation data shown in FIG. Correspondingly, the data LOAD signal input from the LS signal line corresponds to the data LOAD signal shown in FIG.

  As shown in FIG. 29, each pointer shift register DF is constituted by a D-flip flop, and each latch circuit DLA and each hold circuit DLB are constituted by D latches. Further, the number of each of the pointer shift registers DF, the latch circuits DLA, and the hold circuits DLB included in the liquid crystal driving semiconductor integrated circuit 101 is the same as the number of liquid crystal driving signal output terminals OUT.

  As described above, the same number of shift register circuits 123, latch circuits 124, hold circuits 125, DAC circuits 126, and output buffers 127 as the liquid crystal drive signal output terminals 111 are required, and the liquid crystal drive signal output terminals 111 are 1000 in number. If it is a terminal, 1000 pieces of each of the circuits 124 to 127 are required.

  As described above, in recent years, display devices such as liquid crystal panels have been increased in size and definition, and a full-spec high definition television (HDTV) has 1,920 data lines. Therefore, the display driving semiconductor integrated circuit needs to give a signal of gradation voltage of R, G, B for each data line. As a result, the display driving semiconductor integrated circuit has 1920 lines × 3 (R · G B) = 5760 output numbers, in other words, 5760 liquid crystal drive signal output terminals need to be provided. Here, when the number of outputs of one display driving semiconductor integrated circuit is 720, eight display driving semiconductor integrated circuits are required.

  In general, a display driving semiconductor integrated circuit is tested at the wafer stage, is subjected to a shipping test after being packaged, and a display test is performed after being mounted on a liquid crystal panel. Furthermore, semiconductor integrated circuits that may cause initial failures are removed by screening tests such as burn-in and stress tests. Therefore, a display device on which a display driving semiconductor integrated circuit in which display failure occurs is not shipped to the market. However, a display defect rarely occurs while using the display device due to a very small defect or a foreign matter adhering and mixing that has not been determined to be defective during a pre-shipment test or a screening test. For example, even if the ratio of occurrence of display defects after shipment in one data line of a semiconductor integrated circuit for display driving is 0.01 ppm (parts per hundred million), the number of data lines is 5760 full. In the spec HDTV, the display defect occurrence rate is 57.6 ppm (57.6 / 1,000,000). That is, about one in about 17361 units will cause display defects, and the larger the size and the higher definition, the higher the rate of occurrence of display defects.

  When such a display defect occurs, it is necessary to quickly collect the display device and repair the display driving semiconductor integrated circuit. Will be reduced.

  Here, in the prior art, the display driving semiconductor integrated circuit is provided with a spare circuit provided for the defective circuit, and the defective circuit is switched to the spare circuit, so that the defect of the display driving semiconductor integrated circuit is eliminated. Avoidance is disclosed.

Specifically, in Patent Document 1, the display driving semiconductor integrated circuit includes a spare parallel circuit at each stage of the shift register, and performs a self-inspection of the shift register. A technique for avoiding display defects caused by a defective shift register by selecting one having no defect is disclosed. Further, in Patent Document 2, a selector is provided at the input and output of the DAC circuit, and the selector is switched based on the RAM information in which the position of the defective DAC circuit is stored. A method for switching a DAC circuit is disclosed.
JP-A-6-208346 (released July 26, 1994) Japanese Patent Laid-Open No. 8-278771 (released on October 22, 1996)

  However, Patent Document 1 discloses a method for detecting a shift register defect by providing a spare circuit in parallel with the shift register, and a self-repairing method for switching a defective shift register to a spare shift register. It does not disclose a method for detecting a defect or a self-repair method in other output circuits such as a DAC circuit.

  Patent Document 2 discloses a configuration in which a defective DAC circuit is detected and a defective DAC circuit is switched to a spare DAC circuit. In this configuration, the output of the spare DAC circuit is disclosed. Further, it is necessary to perform wiring so that the output of all other DAC circuits can be switched. Therefore, the wiring connected to the spare DAC circuit becomes complicated on the circuit board, and the circuit board on which the DAC circuit is mounted becomes large.

  It is an object of the present invention to provide a drive circuit that can self-repair when a defective video signal output unit is detected and that has a simplified wiring connected to the video signal output unit, and a display device including the drive circuit. .

In order to solve the above problems, a drive circuit according to the present invention provides
M (m is a natural number greater than or equal to 2) output terminals connected to the display device, digital video data captured from the outside is converted into a video signal, and the video signal can be output to the output terminal, at least m + 1 A plurality of video signal output units, a determination unit that determines the quality of each of the video signal output units, and a connection switching unit that switches connection between the output terminal and the video signal output unit according to a determination result by the determination unit And the connection switching unit is h-th (h is a natural number equal to or less than m) output terminal when all the video signal output units are determined to be good by the determination unit. Is connected to the h-th video signal output, and the determination unit determines that the i-th (i is a natural number less than or equal to m) video signal output unit is defective. Natural number less than 1) The j-th video signal output unit is connected to the output terminal, and the k + 1-th video signal output unit is connected to the k-th (k is a natural number between i and m). .

  According to said structure, each video signal output part with which a drive circuit is provided takes in digital video data from the outside, converts it into a video signal, and outputs this video signal to a display apparatus via each output terminal. Further, the drive circuit includes a determination unit that determines whether each video signal output unit is good and a connection switching unit that switches connection between each output terminal and the video signal output unit.

  Here, when the determination unit determines that all the video signal output units are good, the connection switching unit outputs the h-th video signal output to the h-th output terminal (h is a natural number equal to or less than m). Connect each individually. That is, the video signal from the first video signal output unit is output to the first output terminal, and the video signal from the second video signal output unit is output to the second output terminal. Thereafter, similarly, the video signals from the third to m-th video signal output units are output to the third to m-th output terminals.

  On the other hand, when the determination unit determines that the i-th (i is a natural number equal to or less than m) video signal output unit is defective, the connection switching unit is j-th (j is a natural number equal to or less than i-1). The j-th video signal output unit is connected to the output terminal, and the k + 1-th video signal output unit is connected to the k-th output terminal (k is a natural number between i and m). Therefore, the video signal output unit determined to be defective is not connected to any output terminal. For example, when it is determined that the seventh video output unit is defective, the video signals from the first to sixth video signal output units are individually output to the first to sixth output terminals, respectively. The video signals from the 8th to m + 1th video signal output units are individually output to the 7th to mth output terminals, respectively. Therefore, the video signal from the seventh video signal output unit determined to be defective by the determination unit is not output to any output terminal.

  In this way, when a defective video signal output unit occurs, the integrated circuit disconnects the defective video signal output unit from the output terminal, and uses only the normal video signal output unit having no defect, and outputs each output terminal. In other words, the integrated circuit can self-repair when it detects a defective video signal output section.

  Furthermore, when it is determined that the i-th video signal output unit is defective, the connection switching unit connects the k + 1-th video signal output unit to the k-th output terminal. In other words, the connection switching unit connects the connection destination of each output terminal from the video signal output unit connected when all video signal output units are determined to be good, to the video signal output unit adjacent to this video signal output unit. Switch sequentially. As a result, it is possible to prevent the wiring between the video signal output unit and the output terminal from becoming complicated, and as a result, it is possible to suppress an increase in the size of the circuit board.

  In addition, the drive circuit according to the present invention includes a determination unit that determines whether each video signal output unit is good. The connection switching unit is configured to output each output terminal as described above according to the determination result by the determination unit. And the connection of each video signal output unit. In other words, the drive circuit according to the present invention determines whether each video signal output unit included in the drive circuit is good and detects that the video signal output unit is defective. However, a video signal can be output to each output terminal using a normal video signal output unit without repair.

  As described above, the drive circuit of the present invention can self-repair when a defective video signal output unit is detected, and has an effect that the wiring connected to the video signal output unit can be further simplified.

The drive circuit according to the present invention further includes:
Among the plurality of video signal output units, a selection unit that selects a video signal output unit that captures the digital video data is provided, and the selection unit determines that all the video signal output units are good by the determination unit. The h-th video signal output unit is selected as the video signal output unit for capturing the digital video data corresponding to the h-th output terminal, and the determination unit selects the i-th video signal output unit. Is determined to be defective, the nth video signal output unit is selected as the video signal output unit for capturing the digital video data corresponding to the nth (n is a natural number equal to or less than i) output terminal. Preferably, the (k + 1) th video signal output unit is selected as the video signal output unit that captures the digital video data corresponding to the kth output terminal.

  According to the above configuration, when the determination unit determines that all the video signal output units are good, the h-th video signal is used as a video signal output unit that captures digital video data corresponding to the h-th output terminal. Select the output section. Thus, when all the video signal output units are determined to be good by the determination unit, the h-th video signal output unit is connected to the h-th output terminal. A video signal corresponding to the output terminal is output from each video signal output terminal. That is, the digital video data corresponding to the first output terminal is captured by the first video signal output unit, the digital video data corresponding to the second output terminal is captured by the second video signal output unit, and so on. In addition, digital video data corresponding to the third to m-th output terminals are taken in by the third to m-th video signal output units. At this time, each of the first to m-th output terminals is connected to each of the first to m-th video signal output units, and therefore corresponds to each of the first to m-th output terminals. A video signal is output from each video signal output unit.

  On the other hand, when it is determined that the i-th video signal output unit is defective, the selection unit sets n as a video signal output unit that captures digital video data corresponding to the n-th (n is a natural number equal to or smaller than i) output terminal. The k-th video signal output unit is selected as the video signal output unit that captures the digital video data corresponding to the k-th output terminal. Accordingly, the video signal corresponding to the i-th output terminal is output to both the i + 1-th video signal output unit and the i-th video signal output unit determined to be defective. However, the i + 1-th video signal output unit is connected to the i-th output terminal, and the i-th video signal output unit determined to be defective is not connected to any output terminal. In addition, since the k + 1th video signal output unit is connected to the kth output terminal, the video signal corresponding to each output terminal is connected to each output terminal except for the ith video signal output unit. Output from the signal output unit.

  For example, when the determination unit determines that the seventh video signal output unit is defective, the selection unit is the first video signal output unit that captures digital video data corresponding to the first to seventh output terminals. The seventh to seventh video signal output units are selected, and the eighth to m + 1th video signal output units are selected as video signal output units for capturing digital video data corresponding to the seventh to mth output terminals. Thus, the eighth video signal output unit and the seventh video signal output unit determined to be defective both capture the video signal corresponding to the seventh output terminal. However, the eighth video signal output unit is connected to the seventh output terminal, and the seventh video signal output unit determined to be defective is not connected to any output terminal. In addition, since the ninth to m + 1th video signal output units are connected to the eighth to mth output terminals, as a result, the video signal corresponding to each output terminal receives the seventh video signal at each output terminal. Output from each video signal output unit excluding the video signal output unit.

  As described above, when it is determined that the video signal output unit is defective, the drive circuit of the present invention can perform self-repair and output a video signal corresponding to each output terminal to each output terminal.

In the drive circuit according to the present invention,
Each output terminal includes a plurality of sub-output terminals equal to the number of primary colors of display pixels included in the display device, each video signal output unit includes a plurality of output units equal to the number of primary colors, and the determination unit includes When it is determined that at least one of the plurality of output units constituting each of the video signal output units is defective, it is preferable to determine that the video signal output unit is defective.

  According to the above configuration, each output terminal includes a plurality of sub output terminals equal to the number of primary colors, and each video signal output unit includes a plurality of output sections equal to the number of primary colors.

  For example, when the display color is composed of three primary colors of RGB, each output terminal is composed of a set of three sub output terminals, and each video signal output unit is composed of a set of three output units.

  When the determination unit determines that at least one of the output units constituting each video signal output unit is defective, the video signal output unit including the defective output unit is any output terminal and connection terminal. The connection between the output terminal and the connection terminal and the video signal output unit is sequentially switched to the connection with the video signal output unit adjacent to the video signal output unit connected before the failure is detected.

  This makes it possible to switch the connection between the output terminal and the connection terminal and the video signal output unit in units of the number of primary colors constituting the display color. Therefore, even in the drive circuit for driving the color display device, A self-healing function can be implemented without complicating the wiring.

  In the drive circuit according to the present invention, it is preferable that the number of primary colors is three.

  According to the above configuration, for example, it is possible to drive a display device configured with three primary colors of RGB.

In the drive circuit according to the present invention,
Each of the output terminals includes a plurality of sub-output terminals equal to a number that is a natural number times the number of primary colors of the display pixels included in the display device, and each of the video signal output units is a plurality of numbers that are equal to a natural number of times the number of primary colors. The determination unit determines that the video signal output unit is defective when it is determined that at least one of the plurality of output units constituting each video signal output unit is defective. Is preferred.

  According to the above configuration, each output terminal includes a plurality of sub output terminals equal to a number that is a natural number multiple of the number of primary colors, and each video signal output unit includes a plurality of output units that are equal to a natural number multiple of the number of primary colors. Become.

  For example, when the display color is composed of three primary colors RGB and two kinds of gradation voltages are output as video signals corresponding to the primary colors, each output terminal is composed of a set of six sub output terminals, and each video The signal output unit may be configured by a set of six output units.

  When the determination unit determines that at least one of the output units constituting each video signal output unit is defective, the video signal output unit including the defective output unit is any output terminal and connection terminal. The connection between the output terminal and the connection terminal and the video signal output unit is sequentially switched to the connection with the video signal output unit adjacent to the video signal output unit connected before the failure is detected.

  As a result, the connection between the output terminal and the connection terminal and the video signal output unit can be switched in units of natural numbers of the number of primary colors constituting the display color, so that the gradation voltage corresponding to the primary color has a plurality of signals. The self-repair function can be implemented without complicating the wiring of the circuit board even in the drive circuit for driving the color display device set by the above.

  In the driving circuit according to the present invention, it is preferable that the number of primary colors is 3 and the natural number is 2.

  According to the above configuration, for example, it is possible to provide a color display device having a configuration in which display colors are configured by three primary colors of RGB, and gradation voltages corresponding to each of RGB are set by two signals.

The drive circuit according to the present invention further includes:
The selection unit includes a plurality of connection terminals connected to the output units in units of the number of primary colors, and the output units are connected to any one of the plurality of connection terminals in units of the number of primary colors. It is preferable that

  According to said structure, the dot inversion drive of a display apparatus is attained, for example.

  A liquid crystal display device according to the present invention includes any one of the drive circuits described above.

  In the drive circuit of the present invention, as described above, m (m is a natural number of 2 or more) output terminals connected to the display device and digital video data captured from the outside are converted into video signals, and the video At least m + 1 video signal output units capable of outputting a signal to the output terminal, a determination unit for determining the quality of each video signal output unit, and the output terminal and the above according to a determination result by the determination unit And a connection switching unit that switches a connection with the video signal output unit, wherein the connection switching unit is configured to perform an h th operation when all the video signal output units are determined to be good by the determination unit. When the h-th video signal output is connected to the output terminal (h is a natural number less than m), the i-th (i is a natural number less than m) video signal output unit is defective by the determination unit. If determined, The j-th video signal output unit is connected to the output terminal (j is a natural number equal to or less than i−1), and the k + 1-th output terminal is connected to the k-th output terminal (k is a natural number of i or more and m or less) Connect the video signal output unit.

  Therefore, the drive circuit of the present invention can self-repair when a defective video signal output unit is detected, and the wiring connected to the video signal output unit can be further simplified.

  Embodiments according to the present invention will be described below with reference to the drawings.

Embodiment 1
Embodiment 1 of the present invention will be described below with reference to FIGS.

(Configuration of self-healing circuit)
First, the configuration of a display driving semiconductor integrated circuit (hereinafter referred to as an integrated circuit) 10 according to the present embodiment will be described with reference to FIG. For simplicity, the integrated circuit 10 is an integrated circuit with 18 outputs corresponding to FIG. 28 described as a conventional example, but the number of outputs from the integrated circuit 10 is not limited to 18.

  FIG. 1 is a block diagram showing a configuration of an integrated circuit 10 (drive circuit) when performing normal operation according to the present embodiment. As shown in FIG. 1, the integrated circuit 10 includes liquid crystal driving signal output terminals OUT1 to OUT18 (hereinafter abbreviated as output terminals OUT1 to OUT18, collectively referred to as output terminals OUT), and a D-flip-flop_1. ˜D-flip-flop_19 (hereinafter abbreviated as DF_1 to DF_19, generically referred to as DF), latch circuits DLA_1 to DLA_18, and spare latch circuit DLA_19 (hereinafter generically referred to as all latch circuits including spare). The latch circuit DLA), the hold circuits DLB_1 to DLA_18, the spare hold circuit DLB_19 (hereinafter, all the hold circuits including the spare are collectively referred to as the hold circuit DLB), and the output circuits 11_1 to 11_1. 11_18 and spare output circuit 11_19 (hereinafter, all output circuits including spares) When collectively referred to as the output circuit 11), 18 switches SWA 1 to SWA 18 (hereinafter referred to collectively as switches SWA), and 18 switches SWB 1 to SWB 18 (hereinafter collectively referred to as switches SWB) And).

  Note that the video signal output unit in the claims corresponds to a block configured by the latch circuit DLA, the hold circuit DLB, and the output circuit 11 in the present embodiment. Further, the integrated circuit 10 drives video signal lines provided in the display device via each output terminal OUT, and the integrated circuit 10 may be provided in the display device.

  Each DF is connected in series and constitutes a shift register 20 (selection unit). Therefore, the shift register 20 has each DF based on a start pulse signal (hereinafter referred to as SP signal) and a clock signal (hereinafter referred to as CLK signal) input from the SP signal line and the CLK signal line. A pulse signal is sequentially output to the latch circuit DLA, and the latch circuit DLA that takes in gradation data is selected.

  Here, each of the latch circuits DLA sequentially receives input pulse signals (hereinafter referred to as selection signals), and in synchronization with the input timing of the selection signals, from the DATA signal line, each output terminal OUT. Gradation data corresponding to is sequentially fetched. Each latch circuit DLA outputs the fetched gradation data to the hold circuit DLB connected thereto. Each hold circuit DLB holds the output gradation data, and then each output circuit that connects the gradation data held based on the data LOAD signal (hereinafter referred to as LS signal) from the LS signal line to each hold circuit DLB. 11 is output.

  The output circuit 11 includes a DAC (Digital Analog Converter) circuit (not shown) that converts grayscale data into a grayscale voltage signal, an operational amplifier (not shown) that functions as a buffer circuit, and the operation of the output circuit. And a determination flag indicating whether the operation by the determination circuit is good or bad.

  Each output circuit 11 outputs a Flag indicating its own quality. Taking one output circuit 11 as an example, the output circuit 11_1 outputs Flag1 which becomes “1” when the output circuit 11_1 becomes defective, and becomes “0” when the output circuit 11_1 is normal. Flag1 is output. Similarly, the output circuits 11_2 to 10_18 also output Flags 2 to 18 indicating their own quality. The circuit configuration and determination operation for determining the quality of operation for each output circuit will be described later.

  As shown in FIG. 1, the switches SWA1 to SWA18 switch the input destination of each DF, and the switching of each of the switches SWA1 to SWA18 is controlled by the values of Flag1 to Flag18 output from each output circuit 11. Is done. Specifically, when Flagi from the i-th output circuit 11 — i is “1”, the input destination of the (i + 1) -th DF_i is the input of the i-th DF_i, and when Flagi is “0”, The input destination of the (i + 1) th DF_i is the output of the ith DF_i. In addition, said i is an integer which satisfy | fills the relationship of 1 <= i <= 18, and is the same also in the following description. Taking the switch SWA7 as an example, the switch SWA7 is controlled by the value of Flag7 output from the output circuit 11_7. When Flag7 is “1”, the switch SWA7 connects the input of DF_8 to the input of DF_7. To do. On the other hand, when Flag7 is “0”, the switch SWA7 connects the input of DF_8 to the output of DF_7.

  Further, as shown in FIG. 1, the switches SWB1 to SWB18 (connection switching units) switch the connection destinations of the output terminals OUT1 to OUT18. The switches SWB1 to SWB18 are switched from Flag1 to Flag18. It is controlled by the obtained values of Flag_X1 to Flag_X18. Here, Flag_X1 to Flag_X18 are obtained by a control circuit (not shown) using the logical expression shown in FIG. The operation of the switch SWB will be specifically described. When Flag_Xi obtained by combining Flag1 to Flagi with a logical expression OR is “1”, the i-th switch SWBi connects the i-th output terminal OUTi with the i + 1-th output terminal OUTi. Connected to the output of the output circuit 11_i + 1. On the other hand, when Flag_Xi is “0”, the i-th switch SWBi connects the i-th output terminal OUTi to the output of the i-th output circuit 11_i. Taking the switch SWB7 as an example, the switch SWB7 is controlled by the value of Flag_X7. When Flag_X7 is “1”, the switch SWB7 connects the output terminal OUT7 to the output of the output circuit 11_8. On the other hand, when Flag_X7 is “0”, the switch SWB7 connects the output terminal OUT7 to the output of the output circuit 11_7.

  Note that in the integrated circuit 10 shown in FIG. 1, the latch circuits DLA_1 to DLA_18 and the hold circuits DLB_1 to DLB_18 that latch grayscale data input from the outside are each one circuit for one output terminal OUT. However, if the gradation data to be input is 6 bits, 6 circuits are required, and if it is 8 bits, 8 circuits are required. In the present embodiment, in order to simplify the description, the latch circuit DLA and the hold circuit DLB are provided as one circuit for one output terminal OUT.

(Normal operation)
Next, an operation when no defective output circuit is generated in the integrated circuit 10, that is, a normal operation will be described below.

  When no defective output circuit is generated, Flags 1 to 18 in the output circuits 11_1 to 11_18 are all “0”. Accordingly, Flag_X1 to Flag_X18 obtained by combining Flag1 to Flag18 by the logical expression OR are all “0”. Therefore, the switches SWA1 to SWA18 and the switches SWB1 to SWB18 in the integrated circuit 10 are all connected as shown in FIG. 1, and the integrated circuit 10 has the same configuration as the conventional circuit shown in FIG.

  Hereinafter, the normal operation of the integrated circuit 10 will be described with reference to FIG. FIG. 2 is a timing chart showing an operation when no defective output circuit is generated in the integrated circuit 10.

  First, an “H” SP signal indicating the operation start of the integrated circuit 10 is input to the input D of the DF_1. DF_1 takes in the value “H” of the SP signal in response to the rise of the CLK signal, and outputs a selection signal of “H” from its output unit Q. As shown in FIG. 2, the SP signal is “L” at the next rising edge of the CLK signal, so that the output part Q of DF_1 is also “L”. In FIG. 2, the selection signals of DF_1 to DF_18 are described as Q (DF_1) to Q (DF_18).

  The output section Q of each DF is connected to the input section D of the next stage DF, and DF_1 to DF_18 constitute a shift register 20. That is, before Q (DF_1), which is a selection signal from DF_1, becomes “L”, DF_2 outputs Q (DF_2) of “H” in response to the fall of the CLK signal, and then Q (DF_1) Becomes “L”. This operation process is similarly performed in DF_2 to DF_18. As shown in FIG. 2, each DF is connected to each latch circuit DLA connected to each output unit Q in synchronization with the falling edge of the CLK signal. Select signals are output sequentially.

  Next, the latch circuit DLA_1 inputs the selection signal from DF_1 to the gate terminal Q. The latch circuit DLA_1 takes in the grayscale data from its own input unit D while “H” is inputted to the gate unit G, and outputs the fetched grayscale data from its output unit Q to the hold circuit DLB_1. Here, the latch circuit DLA_1 holds the gradation data D1 at the time of falling of the input selection signal, and outputs the held gradation data D1 even after the input selection signal becomes “L”. The signal is output from the part Q to the hold circuit DLB_1. Note that the CLK signal and the gradation data are synchronized with each other, and gradation data corresponding to each output terminal OUT is sequentially input to the integrated circuit 10 at each falling edge of the CLK signal. Note that the gradation data D1 to D18 shown in FIG. 2 are gradation data corresponding to the output terminals OUT1 to OUT18, respectively. Further, in FIG. 2, outputs from the output unit Q of each latch circuit DLA are described as Q (DLA_1) to Q (DLA_18).

  Similarly to the latch circuit DLA_1, the latch circuits DLA_2 to DLA_18 sequentially capture the grayscale data D2 to D18 via the DATA signal line during the period in which the selection signals input from the DF_2 to DF_18 are “H”. Even after the selection signal becomes “L”, the fetched gradation data D2 to D18 are output to the hold circuits DLB connected thereto. At this time, the gradation data D1 to D18 output from the latch circuits DLA are input to the input D of the hold circuits DLB_1 to DLB_18. In FIG. 2, signals output from the output units Q by the latch circuits DLA_1 to DLA18 are described as Q (DLA_1) to Q (DLA_18).

  In FIG. 2, the subsequent operation is not described, but after all the latch circuits DLA fetch each of the gradation data D1 to D18, the integrated circuit 10 adds “ H "LS signal is output. When the “H” LS signal is input, each hold circuit DLB outputs the grayscale data D <b> 1 to D <b> 8 input to its own input unit D to each output unit Q. As a result, the gradation data D1 to D18 taken in by the latch circuits DLA_1 to DLA_18 in order are input to the output circuits 11_1 to 11_18. The output circuits 11_1 to 11_18 convert the input grayscale data D1 to D18 into grayscale voltages, buffer the converted grayscale voltages, and corresponding grayscale voltages corresponding to the grayscale data D1 to D18. Is output to each of the output terminals OUT1 to OUT18.

  Note that the standby circuit DF_19, the latch circuit DLA_19, and the hold circuit DLB_19 also operate in response to the input of the CLK signal or the LS signal. However, the output circuit 11_19 is not connected to any of the output terminals OUT1 to OUT18, and does not affect the output waveforms from the output terminals OUT1 to OUT18. Therefore, in the above description, descriptions of the operations of the spare circuit DF_19, the latch circuit DLA_19, and the hold circuit DLB_19 are omitted.

(Self-repair operation)
Next, in the integrated circuit 10, an operation when an abnormality occurs in the output circuit 11_7 and Flag7 is set to “1” by the determination circuit included in the output circuit 11_7, that is, a self-repair operation is described with reference to FIGS. Will be described with reference to FIG. FIG. 3 is a diagram illustrating a configuration of the integrated circuit 10 when performing a self-repair operation according to the present embodiment, and FIG. 4 is a timing chart illustrating an operation when a defective output circuit is generated in the integrated circuit 10. FIG.

  First, as shown in FIG. 3, in the integrated circuit 10, the output circuit 11_7 becomes defective, and Flag7 is set to “1”. Further, Flag_X1 to Flag_X6 are “0” and Flag_X7 to Flag_X18 configured by incorporating Flag7 are “1” by the logical expression OR (see FIG. 1).

  Here, since Flag_X1 to Flag_X6 is “0”, the switches SWA1 to SWA6 and the switches SWB1 to SWB6 perform the same operations as those in the normal operation already described. Therefore, description of operations in DF_1 to DF_6, latch circuits DLA_1 to DLA_6, hold circuits DLB_1 to DLB_6, and output circuits 11_1 to 11_6 is omitted here.

  On the other hand, since Flag7 is set to “1”, SWA7 switches the connection destination of the input unit D of DF_8 from the output unit Q of DF_7 to the output unit Q of DF_6. As shown in FIG. 4, by switching SWA7, DF_7 and DF_8 output selection signals to latch circuits DLA_7 and DLA_8 at the same timing, in other words, in synchronization with the input timing of gradation data D7. . As a result, the latch circuits DLA_7 and DLA_8 both take in the gradation data D7. Further, DF_9 to DF_19 output selection signals to the latch circuits DLA_9 to DLA_19 in synchronization with the input timings of the gradation data D8 to D18, respectively. Thereby, the latch circuit DLA_9 captures the gradation data D8, the latch circuit DLA_10 captures the gradation data D9, and thereafter, similarly, the latch circuits DLA_1 to DLA_19 respectively capture the gradation data D10 to D18. As described above, the latch circuits DLA_8 to DLA_19 respectively capture the grayscale data D7 to D18 that are shifted by one stage as compared with the normal operation. In FIG. 4, selection signals from the DFs are described as Q (DF_1) to Q (DF_19), and outputs from the output units Q of the latch circuits DLA are Q (DLA_1) to Q (DLA_18). It is described.

  Since Flag_X7 is “1”, the switch SWB7 switches the connection destination of the output terminal OUT7 from the output of the output circuit 11_7 to the output of the output circuit 11_8. Therefore, the gradation voltage output from the defective output circuit 11_7 is not output to any output terminal OUT. Further, the gradation voltage corresponding to the gradation data D7 from the output circuit 11_8 is input to the output terminal OUT7. Further, since Flag_X8 to Flag_X18 are “1”, the switches SWB8 to SWB18 connect the output terminal OUT8 and the output circuit 11_9, connect the output terminal OUT9 and the output circuit 11_10, and similarly, the output terminal OUT10. The output circuit 11_1 to the output circuit 11_19 are connected to the output terminal OUT18, respectively. As a result, gradation voltages corresponding to the gradation data D1 to D18 are output to the output terminals OUT1 to OUT18, respectively.

  As described above, when a defect is detected in the output circuit 11, the latch circuit DLA, and the hold circuit DLB, the connection destination of the input portion D of each DF is switched, and the output circuits 11_1 to 11_19 and the output terminal OUT1 are switched. By switching the connection of .about.OUT18, the output circuit 11, the latch circuit DLA, and the hold circuit DLB that are determined to be defective are disconnected, the normal circuit is sequentially shifted, and a spare circuit is added to enable self-repair. Is realized.

(Detection of malfunction in output circuit)
Hereinafter, a method for detecting a defect in the output circuits 11_1 to 11_18 in the integrated circuit 10 will be described. This defect detection method is performed by comparing the reference voltage with the voltage output from the DAC circuit included in each of the output circuits 11_1 to 11_18 in the operational amplifier included in each of the output circuits 11_1 to 11_18. As a method of detecting a problem in the output circuits 11_1 to 11_18, the voltage output from the DAC circuit included in the spare output circuit 11_19 is determined by comparing the voltage output from the DAC circuit included in each of the output circuits 11_1 to 11_18. There is a “first failure detection method” and a “second failure detection method” in which the voltages output from the DAC circuits included in each of the output circuits 11_1 to 11_18 are compared with each other.

(First failure detection method)
Hereinafter, a “first failure detection method” in which the voltage output from the DAC circuit included in the spare output circuit 11_19 is determined by comparing the voltage output from the DAC circuit included in each of the output circuits 11_1 to 11_18 will be described with reference to FIG. Description will be made with reference to FIG.

  FIG. 5 is a diagram illustrating a configuration for detecting a defect in the normal output circuits 11_1 to 11_18 using the spare output circuit 11_19. In FIG. 5, a block including a DAC_1, an operational amplifier 1_1, switches 2, 2b, a determination circuit 3_1, a determination flag 4_1, and a pull-up / pull-down circuit 5_1 corresponds to the output circuit 11_1 in FIG. 1, and the DAC_2, the operational amplifier 1_2, A block configured by the switches 2, 2b, the determination circuit 3_2, the determination flag 4_2, and the pull-up / pull-down circuit 5_2 corresponds to the output circuit 11_2 in FIG. 1, and includes a DAC_3, an operational amplifier 1_3, switches 2, 2b, a determination circuit 3_3, A block constituted by the determination flag 4_3 and the pull-up / pull-down circuit 5_3 corresponds to the output circuit 11_3 in FIG. 1, and a block constituted by the DAC_19 and the operational amplifier 1_19 corresponds to the spare output circuit 11_19 in FIG. .

  The circuit shown in FIG. 5 is incorporated as a part of the integrated circuit 10 that performs the self-repair operation shown in FIG. 1, and each output circuit 11 is connected to a switch that can switch outputs from two adjacent output circuits. Has been. For example, the output terminal OUT1 is connected to a switch that can switch outputs from the output circuit 11_1 and the output circuit 11_2, and the output terminal OUT2 is connected to a switch that can switch outputs from the output circuit 11_2 and the output circuit 11_3. Has been.

  In FIG. 5, only the output circuits 11_1 to 11_3 and the spare output circuit 11_19 are shown for the sake of explanation. However, the detection of the malfunction is performed for all the normal output circuits 11_1 to 11_18, and each output circuit 11_1 is detected. To 11_18 also include circuits similar to the output circuits 11_1 to 11_3.

  The integrated circuit 10 includes latch circuits DLA_1 to DLA_3, hold circuits DLB_1 to DLB_3, output circuits 11_1 to 11_3, and a plurality of switches 2a and 2b. The integrated circuit 10 also includes a latch circuit DLA_19, a hold circuit DLB_19, and an output circuit 11_19 as spare circuits.

  To the latch circuits DLA_1 to DLA_3, gradation data corresponding to the output terminals OUT1 to OUT3 is input via the DATA signal line. Further, the gray scale data is input to the output circuits 11_1 to 11_3 via the hold circuits DLB_1 to DLB_3, and the digital gray scale data is converted into gray scale voltage signals in the output circuits 11_1 to 11_3.

  The plurality of switches 2a are turned on and off by a test signal, and the plurality of switches 2b are turned on and off by a test B signal. Note that the switch 2a and the switch 2b are turned on when an "H" signal is input, and turned off when an "L" signal is input.

(Operation when failure is not judged)
Next, referring to FIG. 5, a description will be given of a normal operation in the case where the defect determination is not performed, that is, in the display driving in which the display device outputs the gradation voltage.

  In the normal operation, the test signal is “L” and the test B signal is “H”. At this time, the switch 2a is turned off and the switch 2b is turned on. Accordingly, the selection signals from DF_1 to DF_3 are input to the latch circuits DLA_1 to DLA_3, and the selection signal from DF_19 is input to the latch circuit DLA_19.

  The latch circuits DLA_1 to DLA_19 acquire grayscale data corresponding to themselves from the grayscale data input terminal via the DATA signal line in synchronization with the input selection signal. The hold circuits DLB_1 to DLB_19 output the gradation data acquired by the latch circuits DLA_1 to DLA_19 based on the LS signal.

  Next, the DAC_1 to DAC_19 receive gradation data from the hold circuits DLB_1 to DLB_19, respectively. The DAC_1 to DAC_19 convert digital gradation data into gradation voltages and output the gradation voltages to the positive input terminals of the operational amplifiers 1_1 to 1_19. Here, the outputs of the operational amplifiers 1_1 to 1_19 are negative feedback to their own negative input terminals because the switch 2b is ON. Accordingly, the operational amplifiers 1_1 to 1_19 operate as a voltage follower. Therefore, the operational amplifiers 1_1 to 1_19 serve as a buffer circuit with respect to the grayscale voltages from the DAC_1 to DAC_19, and the grayscale voltages input to the positive input terminals of the operational amplifiers 1_1 to 1_19 are output to the corresponding output terminals OUT1. Output to ~ OUT19.

  As described above, when a block including a latch circuit DLA, a hold circuit DLA, a DAC, and an operational amplifier connected in series for each output terminal OUT is an output circuit block (video signal output unit), each output circuit block is For the purpose of converting the gradation data input from the gradation data input terminal into a gradation voltage for driving the display device, and outputting the converted gradation voltage to the display device via the output terminal OUT. Yes.

(Switch to operation check test)
When switching to the operation check test for checking the operation of the DAC_1 to DAC_3, the test signal is set to “H” and the test B signal is set to “L”. First, when the switch 2a is turned on, the spare latch circuit DLA_19 receives the TSTR1 signal, which is an STR signal for an operation check test, and the latch circuits DLA_1 to DLA_3 have an STR signal for an operation check test. The TSTR2 signal is input. Further, the gradation voltage from the spare DAC_19 is input to the negative input terminals of the operational amplifiers 1_1 to 1_3. Further, since the switch 2b is turned off, the negative feedback to the negative input terminal of the output of the operational amplifiers 1_1 to 1_3 is cut off. As a result, the operational amplifiers 1_1 to 1_3 are comparators that compare the output voltage from the DAC_1 to DAC_3 connected in series to its own positive input terminal with the output voltage from the DAC_19 that is a spare DAC circuit.

  The test signal and the testB signal are output from a control circuit (not shown) that controls switching of the operation check test and operation of the operation check test. This control circuit is also a circuit for controlling gradation data and LS input via the DATA signal line in the operation check test. Further, this control circuit may be the same as the control circuit that controls the gradation data, the LS signal, and the CLK signal during normal operation, or may be a different control circuit.

(Operation check test 1 of the first defect detection method)
Next, the first procedure of the operation check test will be described below with reference to FIG. FIG. 6 is a flowchart showing a first procedure in the first defect detection method.

  As described above, FIG. 5 shows only the output circuits 11_1 to 11_3 and the spare output circuit 11_19, but the detection of the malfunction is performed for all the normal output circuits 11_1 to 11_18 shown in FIG. Hereinafter, a method for detecting defects in the output circuits 11_1 to 11_18 by performing defect determination on the DAC_1 to DAC_18 included in the output circuits 11_1 to 11_18 will be described.

  The output circuits 11_1 to 11_18 illustrated in FIG. 1 include operational amplifiers 1_1 to 1_18, determination circuits 3_1 to 3_18, determination flags 4_1 to 4_18, and pull-up / pull-down circuits 5_1 to 5_18, respectively.

  In step S21 (hereinafter abbreviated as S21) shown in FIG. 6, the test signal is set to “H” and the test B signal is set to “L”. As described above, the operational amplifiers 1_1 to 1_18 have a role of a comparator by S21.

  In step S22, a counter m included in a control circuit (not shown) is initialized to zero. Further, the control circuit activates the TSTR1 signal, the gradation data corresponding to the value of the counter m, the gradation data corresponding to the value of the counter m, here the gradation data corresponding to the gradation 0, and the spare latch circuit via the DATA signal line. DAL_19 is taken in. Further, the control circuit activates the TSTR2 signal, adds 1 to the value of the counter m, and outputs grayscale data of grayscale m + 1, here, grayscale data of grayscale 1 through the DATA signal line. The data is stored in the latch circuits DLA_1 to DLA_18.

  Next, the spare hold circuit DLB_19 acquires gradation data of gradation 0 from the latch circuit DAL_19 based on the LS signal. Further, the DAC_19 receives gradation data from the hold circuit DLB_19, and outputs a gradation voltage of gradation 0 to the negative input terminals of the operational amplifiers 1_1 to 1_18 (S23). On the other hand, the hold circuits DLB_1 to DLB_18 acquire gradation data of gradation 1 from the latch circuits DLA_1 to DLA_18 based on LS. Further, the DAC_1 to DAC_18 receive grayscale data from the hold circuits DLB_1 to DLB_18. The DAC_1 to DAC_18 output the gradation voltage of gradation 1 to the positive input terminals of the operational amplifiers 1_1 to 1_18 connected in series to the DAC_1 to DAC_18 (S23). Note that the integrated circuit of the present invention outputs n gradation voltages, the gradation voltage of gradation 0 is the lowest voltage value, and the gradation voltage of gradation n is the highest. It shall be a voltage value.

  Next, the operational amplifiers 1_1 to 1_18 compare the gradation voltage from the DAC_1 to DAC_18 input to the positive input terminal and the gradation voltage from the DAC_19 input to the negative input terminal (S24). Specifically, the operational amplifiers 1_1 to 1_18 input a gradation voltage of gradation 1 to their own positive input terminals and input a gradation voltage of gradation 0 to their own negative input terminals. Here, if DAC_1 to DAC_18 are normal, the grayscale voltage of grayscale 1 is higher than the grayscale voltage of grayscale 0, and thus operational amplifiers 1_1 to 1_18 output “H” level signals. Here, if the outputs of the operational amplifiers 1_1 to 1_18 are “L” level signals, the DAC_1 to DAC_18 are defective.

  Next, the determination circuits 3_1 to 3_18 receive the output signals from the operational amplifiers 1_1 to 1_18, and compare the level of the input signal with the expected value stored by itself. Note that the expected values stored in the determination circuits 3_1 to 3_18 are given by the control circuit. In the operation check test 1, the determination circuits 3_1 to 3_18 store the expected value as the “H” level.

Here, the determination circuits 3_1 to 3_18 determine that the DAC_1 to DAC_18 are normal if the signals input from the operational amplifiers 1_1 to 1_18 are the same as the expected value stored in the “H” level. On the other hand, if the signals input from the operational amplifiers 1_1 to 1_18 are “L” level, the determination circuits 3_1 to 3_18 determine that the DAC_1 to DAC18 are defective and output the “H” flag to the determination flags 4_1 to 4_18. To do. When the “H” flag is input from the determination circuits 3_1 to 3_18, the determination flags 4_1 to 4_18 store the input “H” flag in its own internal memory. (S25)
The determination circuits 3_1 to 3_18 receive the output signals from the operational amplifiers 1_1 to 1_18. If the input signals are “H” level, the “L” flag is output to the determination flags 4_1 to 4_18. If the signal is “L” level, the “H” flag may be output to the determination flags 4_1 to 4_18. In this case, the determination flags 4_1 to 4_18 are determined by the determination flags 4_1 to 4_18 even if the “H” flag is input from the determination circuits 3_1 to 3_18 even if the “L” flag is input from the determination circuits 3_1 to 3_18. 4_18 continues to hold the “H” flag. In addition, when it is determined that the determination flag 4_1 to 4_18 is “H”, the subsequent determination operation may not be performed.

  Next, the control circuit determines whether the value of the counter m is n−1 (S26). When the value of the counter m is n−1 or less, the value of the counter m is incremented by 1, and the steps from S23 to S25 are repeated until the value of m becomes n−1. Note that n is the number of gradations that the integrated circuit 10 can output.

(Operation check test 2 of the first defect detection method)
Next, the second procedure of the operation check test will be described below with reference to FIG. FIG. 7 is a flowchart showing a second procedure of the operation check test according to the first defect detection method.

  First, in the operation check test 1, since the gradation voltage always input to the positive input terminals of the operational amplifiers 1_1 to 1_18 is higher than the gradation voltage input to the negative input terminal, only a low voltage is output to the DAC 19. If there is a malfunction that does not occur or if there is a malfunction such that only a high voltage is output to the DAC_1 to _18, the determination circuits 3_1 to 3_18 output an “L” flag indicating normality.

  Therefore, in the operation check test 2, the operation check is performed by inputting a gradation voltage lower than that of the negative input terminal to the positive input terminals of the operational amplifiers 1_1 to 1_18.

  First, after the operation check test 1 is completed, the value of the counter m is initialized to 0 (S31). Next, the control circuit activates the TSTR1 signal, adds 1 to the value of the counter m, and outputs gradation data of gradation m + 1, here gradation data of gradation 1 via the DATA signal line. The spare latch circuit DLA_19 is made to take in. Next, the control circuit activates the TSTR2 signal, and the grayscale data corresponding to the counter m, the grayscale data corresponding to the grayscale 0, here, the latch data DLA_1 to DLA_18 via the DATA signal line. Incorporate.

  Here, as in S23 of the operation check test 1, the DAC_19 inputs the gradation data stored in the latch circuit DLA_19 via the hold circuit DLB_19. Further, the DAC_19 outputs the gradation voltage of gradation m + 1 corresponding to the inputted gradation data, here the gradation voltage of gradation 1, to the negative input terminals of the operational amplifiers 1_1 to 1_18. On the other hand, the DAC_1 to DAC_18 input grayscale data stored in the latch circuits DLA_1 to DLA_18 via the hold circuits DLB_1 to DLB_18. Further, the DAC_1 to DAC_18 are operational amplifiers 1_1 to 1_18 that are connected in series to the gradation voltage of gradation m, here the gradation voltage of gradation 0, corresponding to the inputted gradation data. Is output to the positive input terminal (S32).

  Next, the operational amplifiers 1_1 to 1_18 have a gradation voltage of gradation 0 from DAC_1 to DAC_18 input to the positive input terminal and a gradation voltage of gradation 1 from DAC_19 input to the negative input terminal. Are compared (S33). Here, if DAC_1 to DAC_18 are normal, the gradation voltage of gradation 1 is higher than the gradation voltage of gradation 0, and thus the operational amplifiers 1_1 to 1_18 output the signal of the “L” flag. Here, when the outputs of the operational amplifiers 1_1 to 1_18 are “H” level signals, the DAC_1 to DAC_18 are defective.

  Next, the determination circuits 3_1 to 3_18 compare the level of the output signal from the operational amplifiers 1_1 to 1_18 with the expected value stored by itself. In the operation check test 1, the determination circuits 3_1 to 3_18 store the expected value as the “L” level. Here, the determination circuits 3_1 to 3_18 determine that the DAC_1 to DAC_18 are normal when the signal input from the operational amplifier 1 is the same as the expected value stored in the “L” level. On the other hand, if the signals input from the operational amplifiers 1_1 to 1_18 are “H”, the determination circuits 3_1 to 3_18 determine that the DAC_1 to DAC 18 are defective and output the “H” flag to the determination flags 4_1 to 4_18. . When the “H” flag is input from the determination circuits 3_1 to 3_18, the determination flags 4_1 to 4_18 store the input “H” flag in its own internal memory (S34). The above steps S33 to S34 are repeated until the value of m reaches n-1 (S35, S36).

(Operation check test 3 of the first defect detection method)
Next, the third procedure of the operation check test will be described below with reference to FIG. FIG. 8 is a flowchart showing a third procedure of the operation check test according to the first defect detection method.

  In the case of the DAC_1 to DAC_18 having a problem that the output is open, the operational amplifiers 1_1 to 1_18 continue to hold the grayscale voltages input to the operational amplifiers 1_1 to 1_18 by the executed confirmation test, and the operation confirmation tests 1 and 2 are performed. In some cases, a failure cannot be detected. Here, in the operation check test 3, the pull-down circuits 5_1 to 5_18 are connected to the positive input terminals of the operational amplifiers 1_1 to 1_18. Thus, when the outputs of the DAC_1 to DAC_18 are open, a low voltage is input to the positive input terminals of the operational amplifiers 1_1 to 1_18. As a result, when the outputs of DAC_1 to DAC_18 are open, in other words, when there is no output from DAC_1 to DAC_18, the operational amplifier 1 continues to hold the gradation voltage input to the operational amplifier 1 according to the executed confirmation test. Can be prevented.

  As shown in FIG. 8, the specific procedure of the operation check test 3 is to initialize a counter m to 0 (S41). Next, the pull-up / pull-down circuits 5_1 to 5_18 pull down the positive input terminals of the operational amplifiers 1_1 to 1_18 (S42). The subsequent steps S43 to S47 are the same as the steps S23 to S27 of the operation check test 1 already described above, and therefore the description thereof is omitted here.

  As described above, when the outputs of the DAC_1 to DAC_18 are opened by pulling down the positive input terminals of the operational amplifiers 1_1 to 1_18 and performing the procedure of the operation check test 1, the operational amplifier 1 is in the “L” level. A signal is output. As a result, the determination circuits 3_1 to 3_18 determine that the DAC_1 to DAC_18 are defective from the input “L” level signal, and the determination flags 4_1 to 4_18 store the “H” flag.

(Operation check test 4 of the first defect detection method)
Next, a fourth procedure of the operation check test will be described below with reference to FIG. FIG. 9 is a flowchart showing a fourth procedure of the operation check test according to the first defect detection method.

  Here, like the operation check test 3, the operation check test 4 is for dealing with a problem that the outputs of the DAC_1 to DAC_18 are open. As shown in the figure, first, the counter m is initialized to 0 (S51). Next, the pull-up / pull-down circuits 5_1 to 5_18 pull up the positive input terminals of the operational amplifiers 1_1 to 1_18 (S52). Steps S53 to S57 from here are the same as the steps S32 to S36 of the operation check test 2 described above, and thus the description thereof is omitted here.

  As described above, when the outputs of the DAC_1 to DAC_18 are opened by pulling up the positive input terminals of the operational amplifiers 1_1 to 1_18 and performing the procedure of the operation check test 2, the operational amplifiers 1_1 to 1_18 are “H "Level signal is output. As a result, the determination circuits 3_1 to 3_18 determine that the DAC_1 to DAC_18 are defective from the input “H” level signal, and the determination flags 4_1 to 4_18 store “H”.

(Operation check test 5 of the first defect detection method)
Next, the fifth procedure of the operation check test will be described below with reference to FIG. FIG. 10 is a flowchart showing a fifth procedure of the operation check test according to the first defect detection method.

  In the DAC_1 to DAC_18, there may be a problem that two adjacent gray scales in the DAC_1 are short-circuited. As described above, when two adjacent gradations are short-circuited, DAC_1 to DAC_18 output an intermediate voltage between the two short-circuited gradations. In the case of this defect, the grayscale voltages output from the DAC_1 to DAC_18 are not shifted by one or more grayscales compared to the normal case. Therefore, this malfunction cannot be detected in the operation confirmation tests 1 to 4. Here, the purpose of the operation check test 5 is to detect a defect in which two adjacent gradations are short-circuited in the DAC_1 to DAC_18.

  As shown in the figure, the control circuit first initializes the counter m to 0 (S61). Next, TSTR1 and TSTR2 are activated, and further, gradation data of gradation m, here gradation data of gradation 0, and latch circuit DLA_19 and latch circuits DLA_1 to DLA_18 via DATA signal line. input. Next, DAC_19 and DAC_1 to DAC_18 obtain grayscale data of grayscale 0 from the latch circuit DLA_19 and the latch circuits DLA_1 to DLA_18 via the hold circuit DLB_19 and the hold circuits DLB_1 to DLB_18. Further, DAC_19 and DAC_1 to DAC_18 output a gradation voltage of gradation 0 to the positive input terminals and the negative input terminals of the operational amplifiers 1_1 to 1_18 (S62).

  Next, the positive input terminals and the negative input terminals of the operational amplifiers 1_1 to 1_18 are short-circuited by a switch (not shown). In the operation check tests 1 and 2, when it is determined that the DAC_1 to DAC_18 are not defective, the difference between the gradation voltages input to the positive input terminal and the negative input terminal is one gradation or more. There is no voltage difference. Therefore, there is no problem that a large current flows by short-circuiting the positive input terminal and the negative input terminal.

  Here, in each operational amplifier 1_1 to 1_18, the positive input terminal and the negative input terminal are short-circuited, so that the two input terminals of the operational amplifiers 1_1 to 1_18 input the same gradation voltage. Here, since the operational amplifiers 1_1 to 1_18 originally have input and output offset voltages, even if the same gradation voltage is input to their two input terminals, the outputs of the operational amplifiers 1_1 to 1_18 are “H”. "Or" L "is output. The determination circuits 3_1 to 3_18 store the output levels of the operational amplifiers 1_1 to 1_18 as expected values when the positive input terminals and the negative input terminals of the operational amplifiers 1_1 to 1_18 are short-circuited (S63).

  Next, a switch (not shown) is turned OFF to cancel a short circuit between the positive input terminal and the negative input terminal of the operational amplifiers 1_1 to 1_18. At this time, gradation voltages of gradation 0 from DAC_1 to DAC_18 are input to the positive input terminals of the operational amplifiers 1_1 to 1_18, and gradation voltages of gradation 0 from DAC_19 are input to the negative input terminals. Is done. Here, if DAC_19 and DAC_1 to DAC_18 are not defective, the outputs of the operational amplifiers 1_1 to 1_18 are the same as the expected values stored in the determination circuits 3_1 to 3_18 in S63. Accordingly, the determination circuits 3_1 to 3_18 compare the outputs from the operational amplifiers 1_1 to 1_18 with the expected values stored by the determination circuits 3_1 to 3_18 (S64). If the output values from the operational amplifiers 1_1 to 1_18 are different from the expected values, the determination circuits 3_1 to 3_18 output “H” flags to the determination flags 4_1 to 4_18 (S65).

  Next, the operational amplifiers 1_1 to 1_1 are input so that the grayscale voltage from the DAC_19 is input to the positive input terminals of the operational amplifiers 1_1 to 1_18 and the grayscale voltages from the DAC_1 to DAC_18 are input to the negative input terminals by a switch (not shown). The input of 1_18 is switched (S66). Here, the same processing as S64 is performed (S67). In S67, if the determination circuits 3_1 to 3_18 differ from the outputs from the operational amplifiers 1_1 to 1_18 and the expected values stored therein, the determination circuits 3_1 to 1_18 output “H” flags to the determination flags 4_1 to 4_18 (S68). In this way, by switching between the positive polarity input terminal and the negative polarity input terminal, even if the expected value stored in the determination circuits 3_1 to 3_18 is either the “H” level or the “L” level, Defects can be detected.

  The above steps S62 to S68 are repeated by incrementing the value of the counter m by one until the value of the counter m reaches n (S69, S70).

(Self-repair related to the first defect detection method)
Next, when the determination flags 4_1 to 4_18 store the “H” flag, in other words, in the operation check tests 1 to 5, the determination circuits 3_1 to 3_18 determine that any of the DAC_1 to DAC_18 is defective. The case repair will be described below with reference to FIG. FIG. 11 is a flowchart showing a procedure for self-repair by the above-described self-repair means.

  When the determination circuits 3_1 to 3_18 determine that the DAC_1 to DAC_18 are defective, the determination circuits 3_1 to 3_18 output “H” flags to the determination flags 4_1 to 4_18. Further, the determination flags 4_1 to 4_18 receive the “H” flag from the determination circuits 3_1 to 3_18, and store them in the inside thereof. Here, the control circuit detects whether or not the determination flags 4_1 to 4_18 record “H” (S71). When the control circuit detects that the determination flags 4_1 to 4_18 do not store “H”, the control circuit proceeds to S75. On the other hand, when it is detected that the determination flags 4_1 to 4_18 store “H”, the control circuit checks the number of “H” flags stored in each of the determination flags 4_1 to 4_18. Here, when the number of “H” flags stored in the determination flags 4_1 to 4_18 is plural, the process proceeds to S73. On the other hand, when the number of “H” flags stored in the determination flag 4 is one, the process proceeds to S74 (S72).

  In S74, the DAC_1 to DAC18 corresponding to the determination flags 4_1 to 4_18 storing the “H” flag are invalidated, and a process for repairing the entire output circuit is performed (S74). Specifically, the determination flags 4_1 to 4_18 output the flags stored therein as Flags 1 to 18 to the switches SWA1 to SWA18 and to the control circuit for obtaining Flag_X1 to Flag_X18.

  Next, the process of S73 will be described. When the number of “H” flags stored in the determination flags 4_1 to 4_18 is plural, it is considered that the spare DAC 19 is probabilistically defective. Therefore, in S73, the control circuit sets all the flags stored in the determination flags 4_1 to 4_18 to the “L” flag, and proceeds to the process of S75. Next, when it is determined NO in S71, after the process of S73 or the process of S74, the control circuit switches the test signal to “L” and the test B signal to “H”, and shifts to the normal operation. (S75).

  Next, a procedure from turning on the power of the display device on which the integrated circuit 10 is mounted to performing an operation check test to performing a normal operation will be described below with reference to FIG. FIG. 12 is a flowchart showing a processing procedure from when the display device is turned on until the operation check test is performed and the normal operation is started.

  As shown in the figure, first, when the display device is powered on and the integrated circuit 10 is initialized, all the determination flags 4_1 to 4_18 become “L” flags (S81). Next, the control circuit sets the test signal to “H”, the test B signal to “L”, and switches the integrated circuit 10 to the operation check test state (S82). Next, the control circuit and the integrated circuit 10 perform the above-described operation check test (S83). Further, the control circuit confirms whether or not all the operation confirmation tests 1 to 5 have been completed, and if there is a defective circuit, performs self-repair and shifts to normal operation (S84).

(Second failure detection method)
Hereinafter, a “second defect detection method” for comparing the voltages output from the output circuit to determine a defect will be described with reference to FIGS. 13 to 19. In addition, regarding the description of the second defect detection method, only the parts different from the first defect detection method will be described, and the description of the overlapping parts will be omitted.

  First, the difference between the first defect detection method and the second defect method will be briefly described. In the first failure detection method, the operational amplifiers 1_1 to 1_18 compare the outputs of the DAC_1 to DAC_18 and the output of the spare DAC_19. On the other hand, in the second failure detection method, two adjacent DACs are set as one set, and the outputs from the respective DACs are compared in the operational amplifiers 1_1 to 1_20.

  FIG. 13 is a diagram illustrating a configuration in which a defect is detected in a pair of two output circuits adjacent to each other in the output circuits 11_1 to 11_20. In FIG. 13, a block constituted by DAC_1, operational amplifier 1_1, switches 2, 2b, determination circuit 3_1, determination flag 4_1, and pull-up / pull-down circuit 5_1 corresponds to the output circuit 1 in FIG. 1, and DAC_2, operational amplifier 1_2, A block constituted by the switches 2, 2b, the determination circuit 3_2, the determination flag 4_2, and the pull-up / pull-down circuit 5_2 corresponds to the output circuit 2 of FIG. 1, and includes a DAC_3, an operational amplifier 1_3, switches 2, 2b, a determination circuit 3_3, A block constituted by the determination flag 4_3 and the pull-up / pull-down circuit 5_3 corresponds to the output circuit 3 of FIG. 1 and includes DAC_4, operational amplifier 1_4, switches 2, 2b, determination circuit 3_4, determination flag 4_4, and pull-up / pull-down. By circuit 5_4 The block formed corresponds to the output circuit 4 in FIG. 1, and the block constituted by the DAC_19, the operational amplifier 1_19, the switches 2, 2b, the determination circuit 3A, the determination flag 4A, and the pull-up / pull-down circuit 25A is a spare in FIG. Corresponds to the output circuit 11_19.

  In FIG. 1, the latch circuit DLA_20, the hold circuit DLB_20, and the output circuit 20 are not shown. However, when the second defect detection method is performed, the latch circuit DLA_20, the hold circuit in the integrated circuit 10 shown in FIG. A block including the circuit DLB_20 and the output circuit 1_20 is provided. The output circuit 1_20 includes a DAC_20, an operational amplifier 1_20, switches 2, 2b, a determination circuit 3B, a determination flag 4B, and a pull-up / pull-down circuit 25B.

  The circuit shown in FIG. 13 is incorporated as part of the integrated circuit 10 that performs the self-repairing operation shown in FIG. 1, and each output circuit is connected to a switch that can switch the output from two adjacent output circuits 11. For example, the output terminal OUT1 is connected to a switch capable of switching the output from the output circuit 1 and the output circuit 2, and the output terminal OUT2 is a switch capable of switching the output from the output circuit 2 and the output circuit 3. It is connected to the.

  In FIG. 13, only the output circuits 11_1 to 11_4 and the spare output circuits 11_19 and 11_20 are shown for the sake of explanation. However, the detection of the malfunction is performed for all the normal output circuits 11_1 to 11_20.

  The integrated circuit 10 includes latch circuits DLA_1 to DLA_4, hold circuits DLB_1 to DLB_4, output circuits 11_1 to 11_4, and a plurality of switches 2a and 2b. Further, the integrated circuit 10 includes spare latch circuits DLA_19 and 20, spare hold circuits DLB_19 and 20, spare DAC circuits DAC19 and DAC20, operational amplifiers 1_19 and 1_20, and pull-up / pull-down circuits 25A and 25B. Output circuits 11_19 and 11_20 including the above are provided.

  The operational amplifiers 1_1 to 1_20 input the outputs from the DAC_1 to DAC_20 connected in series to the operational amplifiers 1_1 to 1_20 to their positive input terminals. Furthermore, the operational amplifiers 1_1 to 1_20 input the outputs from the DAC_1 to DAC_20 connected in series to the operational amplifiers adjacent to the operational amplifiers 1_1 to 1_20 to their negative input terminals. Specifically, as shown in the figure, the operational amplifier 1_1 inputs the output from the DAC_1 to its own positive input terminal, and the output from the DAC_2 to its own negative input via the switch 2a. Input to the terminal. Similarly, the operational amplifier 1_2 inputs the output from the DAC_2 to its own positive input terminal, and inputs the output from the DAC_1 to its own negative input terminal via the switch 2a.

  Also in the operational amplifier 1_19, the output from the DAC_19 is input to its own positive input terminal, and the output from the DAC_20 is input to its own negative input terminal via the switch 2a. Further, in the operational amplifier 1_20, the output from the DAC_20 is input to its own positive input terminal, and the output from the DAC_19 is input to its own negative input terminal via the switch 2a.

(Operation when failure is not judged)
In the normal operation of the integrated circuit 10, as in the case of the first defect detection method, the control circuit sets the test signal to the “L” level and the test B signal to the “H” level. Thus, the DAC_1 to DAC_18 convert the grayscale data input from the hold circuits DLB_1 to DLB_18 into a grayscale voltage signal, and output the grayscale voltage to the positive input terminals of the operational amplifiers 1_1 to 1_18. Here, the output of the operational amplifiers 1_1 to 1_18 is negative feedback to its own negative input terminal because the switch 2b is ON. As a result, the operational amplifiers 1_1 to 1_18 operate as a voltage follower. Therefore, the operational amplifiers 1_1 to 1_18 buffer the grayscale voltages from the DAC_1 to DAC_18 and output them to the corresponding output terminals OUT1 to OUT18.

(Switch operation test)
In the switching to the operation check test in the integrated circuit 10, the control circuit sets the test signal to the “H” level and sets the test B signal to the “L” level. First, when the switch 2a is turned on, the TSTR1 signal is input to the latch circuit DLA_19 and the odd-numbered latch circuits DLA (latch circuits DLA_1 and DLA_3). Further, the TSTR2 signal is input to the latch circuit DLA_20 and the even-numbered latch circuits (latch circuits DLA_2 and DLA_4). Further, when the switch 2a is turned on, the output from the adjacent even-numbered DACs (DAC_2, DAC_4) is input to the negative input terminals of the odd-numbered operational amplifiers (operational amplifiers 1_1, 1_3). Outputs from adjacent odd-numbered DACs (DAC_1, DAC_3) are input to the negative input terminals of the operational amplifiers (operational amplifiers 1_2, 1_4). Further, when the test B signal becomes “L” level, the switch 2b is turned OFF. As a result, the negative feedback of the output of the operational amplifiers 1_1 to 1_4 to the negative input terminal is cut off. As a result, the operational amplifiers 1_1 to 1_4 are comparators that compare the outputs from the DAC_1 to DAC_4 connected in series with the operational amplifiers 1_1 to 1_4 with the outputs from the adjacent DAC_1 to DAC_4.

(Operation check test 1 of the second defect detection method)
Next, the first procedure of the operation check test according to the second defect detection method will be described below with reference to FIG. FIG. 14 is a flowchart showing a first procedure of the operation check test according to the second defect detection method.

  As described above, FIG. 13 shows only the output circuits 11_1 to 11_4 and the spare output circuits 11_19 and 11_20, but the detection of the malfunction is performed for all the normal output circuits 11_1 to 11_18 shown in FIG. Hereinafter, a method for detecting defects in the output circuits 11_1 to 11_18 by performing defect determination on the DAC_1 to DAC_18 included in the output circuits 11_1 to 11_18 will be described.

  The output circuits 11_1 to 11_18 illustrated in FIG. 1 include operational amplifiers 1_1 to 1_18, determination circuits 3_1 to 3_18, determination flags 4_1 to 4_18, and pull-up / pull-down circuits 5_1 to 5_18, respectively.

  First, the control circuit sets the test signal to the “H” level and the test B signal to the “L” level (S101). Accordingly, the operational amplifiers 1_1 to 1_18 operate as comparators (S102). Next, the control circuit sets the expected value of the odd-numbered determination circuit (determination circuits 3_1, 3_3,...) To the “L” level. On the other hand, the control circuit sets the expected value of the even-numbered determination circuit (determination circuits 3_2, 3_4,...) To the “H” level.

  Next, the control circuit initializes a counter m included in the control circuit to 0 (S103). Further, the control circuit activates TSTR1, and the latch circuit DLA_19 and the odd-numbered latch circuits (DLA_1, DLA_3,...) Input grayscale data of grayscale m through the DATA signal line. Further, the control circuit activates TSTR2, and the latch circuit DLA_20 and the even-numbered latch circuits (DLA_2, DLA_4,...) Input grayscale data of grayscale m + 1 through the data bus (S104).

  Considering the case where the value of the counter m is 0, the odd-numbered operational amplifiers (operational amplifiers 1_1, 1_3,...) Have a gradation voltage of gradation 0 at their own positive input terminals in series with themselves. Are input from odd-numbered DACs (DAC_1, DAC3,...) Connected to. Further, the odd-numbered operational amplifier inputs the grayscale voltage of grayscale 1 from its adjacent even-numbered DAC (DAC_2, DAC_4,...) To its negative input terminal. Here, if the DAC_1 to DAC_18 connected to the two input terminals of the operational amplifiers 1_1 to 1_18 are normal, the output of the odd-numbered operational amplifier 1 becomes “L”. On the other hand, the even-numbered operational amplifier inputs the gradation voltage of gradation 1 to its positive polarity input terminal from the even-numbered DAC connected in series to itself. Further, the even-numbered operational amplifiers (operational amplifiers 1_2, 1_4,...) Input gradation voltage of gradation 0 from their adjacent odd-numbered DAC circuits to their negative input terminals. Here, if the DAC_1 to DAC_18 connected to the two input terminals of the operational amplifiers 1_1 to 1_18 are normal, the output of the even-numbered operational amplifier becomes “H”.

  Next, the determination circuits 3_1 to 3_18 determine whether the level of the output signal from the operational amplifiers 1_1 to 1_18 matches the expected value stored by itself (S105). When the outputs from the operational amplifiers 1_1 to 1_18 are different from the expected values, the determination circuits 3_1 to 3_18 output “H” flags to the determination flags 4_1 to 4_18 (S106). The above processes from S104 to S106 are repeated until the value of the counter m is incremented by one until the value of the counter m reaches n−1 (S107, S108).

(Operation check test 2 of the second defect detection method)
Next, a second procedure of the operation check test according to the second defect detection method will be described below with reference to FIG. FIG. 15 is a flowchart showing a second procedure of the operation check test according to the second defect detection method.

  The operation check test 2 in the second defect detection method is an operation check in which the voltage relationship between the odd-numbered and even-numbered gradations in the operation check test 1 in the second defect detection method is reversed. This is the same as the operation check test in the second defect detection method.

  First, the control circuit sets the expected value of the odd-numbered determination circuit to “H”, while setting the expected value of the even-numbered determination circuit to “L”. Further, the control circuit initializes a counter m included in the control circuit to 0 (S111).

  Next, the control circuit activates TSTR1, and the latch circuit DLA_19 and the odd-numbered latch circuit input gradation data of gradation m + 1 through the data bus. Further, the control circuit activates TSTR2, and the latch circuit DLA_20 and the even-numbered latch circuit input grayscale data of grayscale m through the data bus (S112).

  Here, considering the case where the value of the counter m is 0, the odd-numbered operational amplifier has a grayscale voltage of grayscale 1 connected to its positive polarity input terminal and is connected in series to the odd-numbered DAC. input. The odd-numbered operational amplifier inputs the gradation voltage of gradation 0 from its adjacent even-numbered DAC to its negative input terminal. Here, if the DAC connected to the two input terminals of the operational amplifier is normal, the output of the odd-numbered operational amplifier is at the “H” level. On the other hand, the even-numbered operational amplifier inputs the gradation voltage of gradation 0 to its own positive input terminal from the even-numbered DAC connected in series to itself. The even-numbered operational amplifier inputs the gradation voltage of gradation 1 from its adjacent odd-numbered DAC to its negative input terminal. Here, if the DAC connected to the two input terminals of the operational amplifier is normal, the output of the even-numbered operational amplifier 1 becomes “L” level.

  Next, the determination circuit 3 compares the level of the output from the operational amplifier with the expected value stored by itself (S113). Here, when the outputs from the operational amplifiers 1_1 to 1_18 are different from the expected values, the determination circuits 3_1 to 3_18 output “H” flags to the determination flags 4_1 to 4_18. The above processes of S112 to S114 are repeated until the value of the counter m is incremented by one until the value of the counter m reaches n−1 (S115, S116).

(Operation check test 3 of the second defect detection method)
Next, a third procedure of the operation check test according to the second defect detection method will be described below with reference to FIG. FIG. 16 is a flowchart showing a third procedure of the operation check test according to the second defect detection method.

  As described in the operation check test 3 of the first failure detection method, when there is a failure in which the output is open in the DAC_1 to DAC_18, the grayscale voltages input to the operational amplifiers 1_1 to 1_18 by the executed check test May continue to be held by the operational amplifiers 1_1 to 1_18, and the failure may not be detected in the operation check tests 1 and 2 of the second failure detection method.

  First, similarly to the operation check tests 1 and 2, the control circuit initializes the value of the counter m included in the control circuit to 0 (S121). In the integrated circuit 10, the pull-up / pull-down circuits 5_1 to 5_18 are connected to the positive input terminals of the DAC_1 to DAC_18. Here, the control circuit controls the pull-up / pull-down circuits 5_1 to 5_18 to pull up the positive input terminals of the odd-numbered operational amplifiers (S122). As a result, when the output of the odd-numbered DAC is open, a high voltage is input to the positive input terminal of the odd-numbered operational amplifier. On the other hand, the control circuit controls the pull-up / pull-down circuits 5_1 to 5_18 so that the positive input terminals of the even-numbered operational amplifiers are pulled down (S122). As a result, when the output of the even-numbered DAC is open, a low voltage is input to the positive input terminal of the even-numbered operational amplifier 1.

  Since the subsequent processes of S123 to S127 are the same as those in the operation check test 1 of the second embodiment, the description thereof is omitted here.

(Operation check test 4 of the second defect detection method)
Next, a fourth procedure of the operation check test according to the second defect detection method will be described below with reference to FIG. FIG. 17 is a flowchart showing a fourth procedure of the operation check test according to the second defect detection method.

  Here, the purpose is to detect the same defect as the operation check test 3 described above. First, as in the previous operation check test, the control circuit initializes the value of the counter m included in the control circuit to 0 (S131). Next, the control circuit controls the pull-up / pull-down circuits 5_1 to 5_18 to pull down the positive input terminals of the odd-numbered operational amplifiers (S122). As a result, when the output of the odd-numbered DAC is open, a low voltage is input to the positive input terminal of the odd-numbered operational amplifier. On the other hand, the control circuit controls the pull-up / pull-down circuits 5_1 to 5_18 so that the positive input terminals of the even-numbered operational amplifiers 1 are pulled up (S122). As a result, when the output of the even-numbered DAC is open, a high voltage is input to the positive input terminal of the even-numbered operational amplifier.

  The subsequent processes of S133 to S137 are the same as those in the operation check test 2 of the second embodiment, and thus description thereof is omitted here.

(Operation check test 5 of the second defect detection method)
Next, a fifth procedure of the operation check test according to the second defect detection method will be described below with reference to FIG. FIG. 18 is a flowchart showing the fifth procedure of the operation check test according to the second defect detection method.

  As described in the operation check test 5 of the first defect detection method, the DAC_1 to DAC_18 may have a problem that two adjacent gray levels in the DAC_1 to DAC_18 are short-circuited. The purpose of the operation check test 5 of the second failure detection method is to detect such a failure.

  As shown in the figure, first, the control circuit initializes the value of the counter m provided therein to 0 (S141). Next, TSTR1 and TSTR2 are activated, and the grayscale data of grayscale m is input to the latch circuit DLA_19, the latch circuit DLA_20, and the latch circuits DLA_1 to DLA_18 via the data bus. Further, by making the LS signal active, the odd-numbered DAC and the even-numbered DAC output the gradation voltage of the same gradation m (S142). Next, the control circuit short-circuits the positive input terminal and the negative input terminal of the operational amplifiers 1_1 to 1_18 through a switch (not shown). By short-circuiting the positive input terminals and the negative input terminals of the operational amplifiers 1_1 to 1_18, the positive input terminals and the negative input terminals of the operational amplifiers 1_18 to 1_18 are input with the same gradation voltage. Become. Next, the determination circuit 3 stores the output level of the operational amplifier when the positive input terminal and the negative input terminal of the operational amplifiers 1_1 to 1_18 are short-circuited as an expected value (S143).

  Next, a switch (not shown) is turned OFF to cancel a short circuit between the positive input terminal and the negative input terminal of the operational amplifiers 1_1 to 1_18. At this time, the grayscale voltage of the grayscale m from the odd-numbered DAC connected in series to the odd-numbered operational amplifiers 1_1 to 1_18 is input to the positive-polarity input terminals, The gradation voltage of gradation m is input from the even-numbered DAC adjacent to. On the other hand, the grayscale voltage of grayscale m from the even-numbered DAC connected in series to itself is input to the positive input terminal of the even-numbered operational amplifier, and the negative-numbered input terminal is an odd number adjacent to itself. The gradation voltage of gradation m from the second DAC is input. Here, the determination circuits 3_1 to 3_18 compare the expected values stored by themselves with the outputs from the operational amplifiers 1_1 to 1_18 (S144). Further, when the outputs from the operational amplifiers 1_1 to 1_18 are different from the expected values stored in the determination circuits 3_1 to 3_18, the determination circuits 3_1 to 3_18 output “H” flags to the determination flags 4_1 to 4_18. Furthermore, the determination flags 4_1 to 4_18 store therein the “H” flag input from the determination circuits 3_1 to 3_18.

  Next, the control circuit uses a switch (not shown) to switch the signal input to the positive input terminals of the operational amplifiers 1_1 to 1_18 from the DAC_1 to DAC_18 with the signal input to the negative input terminal (S146). ). Thereafter, the same processing as S147 is performed (S147). Similarly to S145, when the outputs from the operational amplifiers 1_1 to 1_18 are different from the expected values stored therein, the determination circuits 3_1 to 3_18 output “H” to the determination flags 4_1 to 4_18 (S148). .

  The processes of S142 to S148 are repeated by incrementing the value of the counter m by one until the value of the counter m reaches n (S149, S150).

(Self-repair related to the second defect detection method)
Next, when the determination flag 4 stores “H”, in other words, when the determination circuits 3_1 to 3_18 determine that any of the DAC_1 to DAC_18 is defective in the operation check tests 1 to 5 described above. The repair will be described below with reference to FIG. FIG. 19 is a flowchart illustrating a procedure for invalidating an output circuit determined to be defective and performing self-repair.

  First, the control circuit detects whether or not the determination flags 4_1 to 4_18 store “H” (S151). When the control circuit detects that the determination flags 4_1 to 4_18 do not store “H”, the control circuit proceeds to S153. On the other hand, when the control circuit detects the determination flags 4_1 to 4_18 storing “H”, the output circuit corresponding to the determination flags 4_1 to 4_18 storing “H” and the corresponding output circuit are invalidated. Then, a process for repairing the entire output circuit is performed (S152). Note that in S74, the determination flags 4_1 to 4_18 output the flags stored therein as Flags 1 to 18 to the switches SWA1 to SWA18 and to the control circuit for obtaining Flag_X1 to Flag_X18. .

  Next, the control circuit sets the test signal to “L” and the test B signal to “H”, and shifts to normal operation (S153).

  In the second defect detection method, since two output circuits are determined as one set, two or more output circuits to be invalidated are necessary.

  For this reason, in the case of the first embodiment of self-repair, it is necessary to prepare a spare circuit for two outputs. In the case of a second embodiment of self-repair described later, invalidation processing is performed with a set of three output circuits, and it is difficult to correspond to the second defect detection method. Therefore, in this case, it is desirable to perform invalidation processing with 6 outputs as one set, as in a third embodiment of self-repair described later.

[Embodiment 2]
A second embodiment of the present invention will be described below with reference to FIGS. In addition, the structure shown in Embodiment 2 is a modification of Embodiment 1, and a different location from Embodiment 1 is demonstrated, The description is abbreviate | omitted about the location which overlaps.

(Configuration of self-healing circuit)
First, with reference to FIG. 20, a description will be given of a configuration in which a defective output circuit is replaced with a non-defective output circuit and self-repair is performed in the integrated circuit 10 ′ according to the present embodiment. As in the first embodiment, the integrated circuit 10 ′ is an integrated circuit with 18 outputs, but the number of outputs from the integrated circuit 10 ′ is not limited to 18.

  FIG. 20 is a block diagram showing a configuration of the integrated circuit 10 ′ in the case of performing a normal operation according to the present embodiment. As shown in FIG. 20, the integrated circuit 10 ′ includes output terminals OUT1 to OUT18, DF_20 to DF_26 (hereinafter collectively referred to as DF), latch circuits DLA_R1 to DLA_R6, DLA_G1 to DLA_G6, and DLA_B1 to DLA_B6. Spare latch circuits DLA_R7, DLA_G7 and DLA_B7 (hereinafter referred to as latch circuit DLA when all latch circuits including spare are generically referred to), hold circuits DLB_R1 to DLB_R6, DLB_G1 to DLB_G6 and DLB_B1 to DLB_B6, Spare hold circuits DLB_R7, DLB_G7 and DLB_B7 (hereinafter, all hold circuits including the spare are collectively referred to as hold circuit DLB), output circuits 11_1 to 11_18, and spare output circuit 1 _19～11_21 (hereinafter, may be collectively all of the output circuit including a preliminary to the output circuit 11), and a switch SWA20~ switch SWA25, a switch SWB1～SWB18, the.

  In the present embodiment, the output unit in the claims includes individual latches DLA (for example, latch circuits DLA_R1, DLA_G1, and DLA_B1) and hold circuits DLB (for example, latch circuits DLB_R1, DLB_G1, and DLB_B1, respectively). ) And the output circuit 11 (each of the output circuits 11_1, 11_2, and 11_3), and the video signal output unit in the claims is continuous corresponding to the three primary colors RGB constituting the display color. And a block composed of the latch circuit DLA, the hold circuit DLB, and the output circuit 11 (for example, a block composed of the latch circuits DLA_R1, DLA_G1, DLA_B1, the latch circuits DLB_R1, DLB_G1, DLB_B1, and the output circuits 11_1 to 11_3). It is response.

  Further, the sub output terminals in the claims correspond to the output terminals OUT1 to OUT18, respectively, and the output terminals in the claims have three output terminals arranged corresponding to the video signal output unit. (For example, OUT1 to OUT3).

  The output circuit 11 included in the integrated circuit 10 ′ has the same internal circuit configuration as the output circuit 11 included in the integrated circuit 10 according to the first embodiment, and is a DAC circuit that converts grayscale data into a grayscale voltage signal ( (Not shown), an operational amplifier (not shown) serving as a buffer circuit, a determination circuit that determines whether the operation of the output circuit is good, and a determination flag that indicates whether the operation of the determination circuit is good or bad.

  The integrated circuit 10 ′ according to the present embodiment has three primary colors that constitute display colors, that is, red (R) and green (G), via three DATAR signal lines, DATAG signal lines, and DATAB signal lines, respectively. , And blue (B) gradation data are input. That is, the integrated circuit 10 ′ is configured to drive a color display device in which display colors are configured by three colors of RGB.

  Each input part D of the latch circuits DLA_R1 to DLA_R7 is connected to the DATAR signal line, each input part D of the latch circuits DLA_G1 to DLA_G7 is connected to the DATAG signal line, and each input of the latch circuits DLA_B1 to DLA_B7 Part D is connected to the DATAB signal line.

  Each DF is connected in series and constitutes a shift register 20 '. Therefore, the shift register 20 ′ sequentially outputs selection signals from the DFs to the latch circuits DLA based on the SP signals and the CLK signals input from the SP signal lines and the CLK signal lines, and outputs the gradation data. A latch circuit DLA to be captured is selected.

  The gate part G of the latch circuits DLA_R1, DLA_G1 and DLA_B1 is connected to the output part Q of the DF20, and the gate part G of the latch circuits DLA_R2, DLA_G2 and DLA_B2 is connected to the output part Q of the DF21. The gate part G of the latch circuits DLA_R3, DLA_G3 and DLA_B3 is connected to the output part Q of the DF22, and the gate part G of the latch circuits DLA_R4, DLA_G4 and DLA_B4 is connected to the output part Q of the DF23, and the latch circuit The gate part G of DLA_R5, DLA_G5 and DLA_B5 is connected to the output part Q of the DF24, and the gate part G of the latch circuit DLA_R6, DLA_G6 and DLA_B6 is connected to the output part Q of the DF25, and the latch circuit DLA_R7, The gate portion G of LA_G7 and DLA_B7 is connected to the output Q of the DF26.

  Here, each of the latch circuits DLA takes out the gradation data corresponding to each output terminal OUT1 from the inputted gradation data, and outputs it to each hold circuit DLB to which each is connected. Each hold circuit DLB holds the gradation data from each latch circuit DLA and then outputs it to each output circuit 11 to which it is connected. The output circuit 11 according to the present embodiment includes a DAC circuit, a buffer circuit, a determination circuit, and a determination flag, respectively, similarly to the output circuit 11 according to the first embodiment, and further includes output circuits 11_1 to 11_18. The flag 1 to 18 indicating the pass / fail judgment result is output. Flags 1 to 18 are “0” when the output circuit is a non-defective product, and “1” when the output circuit is defective.

  As shown in FIG. 20, the switches SWA20 to SWA25 switch the input destinations of DF_21 to DF_26, and each switching of the switches SWA20 to SWA25 is controlled by the values of FlagA to FlagF obtained from Flag1 to Flag18. The Here, FlagA to FlagF are obtained by the logical expressions shown in FIG. Specifically, the switches SWA20 and SWA21 will be described as an example. When FlagA is “0”, the switch SWA20 connects the input unit D of DF_21 and the output unit Q of DF_20. On the other hand, when Flag A is “1”, the input unit D of DF_21 and the input unit D of DF_20 are connected. Further, when FlagB is “0”, the switch SWA21 connects the input unit D of DF_22 and the output unit Q of DF_21. On the other hand, when FlagB is “1”, the switch SWA21 connects the input unit D of DF_22 and the output unit of DF_20.

  Similarly, the switches SWA22 to SWA25 connect the input units D of DF_23 to DF_26 to the output units Q of DF_22 to DF_25 arranged one stage upstream when FlagC to FlagF are “0”. On the other hand, the switches SWA22 to SWA25 connect the input units D of DF_23 to DF_26 to the output units Q of DF_21 to DF_24 arranged upstream by two stages when FlagC to FlagF are “1”.

  Further, as shown in FIG. 20, the switches SWB1 to SWB18 switch the connection destinations of the output terminals OUT1 to OUT18. The switching of the switches SWB1 to SWB3 is controlled by the value of FlagA. The switching of SWB6 is controlled by the value of FlagG, the switching of switches SWB7 to SWB9 is controlled by the value of FlagH, the switching of switches SWB10 to SWB12 is controlled by the value of FlagI, and the switches SWB13 to SWB15 The switching is controlled by the value of FlagJ, and the switching of the switches SWB16 to SWB18 is controlled by the value of FlagK. Here, FlagG to FlagK are obtained by the logical expressions shown in FIG.

  The specific operation of the switch SWB will be described. When Flag (any one of FlagA, FlagG to FlagK) input to the i-th switch SWBi is “0”, the switch SWBi is the i-th output terminal. When the i-th output circuit 11_i is connected to OUTi, and the input flag is “1”, the switch SWBi connects the i + 3rd output circuit 11_i + 3 to the i-th output terminal OUTi. Taking the switch SWB7 as an example, the switch SWB7 is controlled by the value of FlagH. When FlagH is “1”, the switch SWB7 connects the output terminal OUT7 to the output circuit 11_10. On the other hand, when FlagH is “0”, the switch SWB7 connects the output terminal OUT7 to the output of the output circuit 11_7.

(Normal operation)
Next, an operation when no defective output circuit is generated in the integrated circuit 10 ′, that is, a normal operation will be described below.

  When no defective output circuit is generated, Flags 1 to 18 in the output circuits 11_1 to 11_18 are all “0”. Accordingly, FlagA to FlagK obtained by combining Flag1 to Flag18 by the logical expression OR are all “0”. Therefore, the switches SWA20 to SWA25 and the switches SWB1 to SWB18 in the integrated circuit 10 'are all connected as shown in FIG.

  Hereinafter, the normal operation of the integrated circuit 10 'will be described with reference to FIG. FIG. 21 is a timing chart showing an operation when no defective output circuit is generated in the integrated circuit 10 ′.

  First, an “H” SP signal indicating the start of operation of the integrated circuit 10 ′ is input to the input D of the DF_20. DF_20 takes in the value “H” of the SP signal in response to the rise of the CLK signal and outputs a selection signal of “H” from its output unit Q. As shown in FIG. 21, since the SP signal is “L” at the next rising edge of the CLK signal, the output section Q of DF_20 is also “L”. In FIG. 21, the selection signals of DF_20 to DF_25 are described as Q (DF_20) to Q (DF_25).

  The output section Q of each DF is connected to the input section D of the next stage DF, and DF_20 to DF_25 constitute a shift register 20 ′. That is, before Q (DF_20), which is a selection signal from DF_20, becomes “L”, DF_21 outputs Q (DF_21) of “H” in response to the fall of the CLK signal, and then Q (DF_20) Becomes “L”. This operation process is similarly performed in DF_20 to DF_25. As shown in FIG. 21, each DF is connected to each latch circuit DLA connected to each output unit Q in synchronization with the falling edge of the CLK signal. Select signals are output sequentially.

  The grayscale data corresponding to RGB is input to each latch circuit DLA via the DATAR signal line, the DATAG signal line, and the DATAB signal line. The gradation data input via the DATAR signal line, the DATAG signal line, and the DATAB signal line changes every time the CLK signal falls. That is, as shown in FIG. 21, in synchronization with the falling timing of the CLK signal, the signal changes from R1 to R2, from G1 to G2, from B1 to B3, and so on. Each latch circuit DLA takes in gradation data input to the input unit D and outputs it to the output unit Q while the selection signal input to its gate unit G is “H”. That is, the latch circuits DLA_R1 to DLA_R6, DLA_G1 to DLA_G6, and DLA_B1 to DLA_B6 each take in gradation data input from the outside while each selection signal line from each DF is “H”, and output to the output unit Q To do. In FIG. 21, the outputs from the output unit Q of each latch circuit DLA are described as Q (DLA_R1) to Q (DLA_B6).

  Accordingly, the latch circuits DLA_R1 to DLA_R6 are sequentially selected in synchronization with the change timing of the grayscale data input via the data signal line DATAAR, and each latch circuit DLA corresponds to each output terminal OUT. Gradation data to be captured is captured. That is, the latch circuits DLA_R1 to DLA_R6 sequentially capture the grayscale data R1 to R6 by the selection signals sequentially output from the DFs. Similarly, the latch circuits DLA_G1 to DLA_G6 sequentially take in the gradation data G1 to G6 by the selection signals sequentially output from the DFs. Similarly, the latch circuits DLA_B1 to DLA_B6 sequentially take in the gradation data B1 to B6 by the selection signals sequentially output from the DFs.

  In FIG. 21, the subsequent operation is not described, but after all the latch circuits DLA have fetched the respective grayscale data, the integrated circuit 10 ′ has the LS of “H” in the gate portion G of each hold circuit DLB. Output a signal. When the “H” LS signal is input, each hold circuit DLB outputs each gradation data input to its own input unit D from each output unit Q. As a result, the gradation data R1 to R6, G1 to G6, and B1 to B6 that are sequentially taken by the latch circuits DLA are input to the output circuits 11_1 to 11_18. The output circuits 11_1 to 11_18 respectively convert the input gradation data into gradation voltages, buffer the converted gradation voltages, and output the converted gradation voltages to the output terminals OUT1 to OUT18 to which they are connected, respectively.

  Note that the standby circuit DF_26, the latch circuits DLA_R7, DLA_G7, and DLA_B7, and the hold circuits DLB_R7, DLB_G7, and DLB_B7 also operate in response to the input of the CLK signal and the LS signal. However, the output circuits 11_19 to 21-21 are not connected to any of the output terminals OUT1 to OUT18, and do not affect the output waveforms from the output terminals OUT1 to OUT18. Therefore, in the above description, descriptions of the operations of the spare circuit DF_26, the latch circuits DLA_R7, DLA_G7, and DLA_B7, and the hold circuits DLB_R7, DLB_G7, and DLB_B7 are omitted.

(Self-repair operation)
Next, in the integrated circuit 10 ′, the operation when the abnormality occurs in the output circuit 11_7 and the flag 7 is set to “1” by the determination circuit included in the output circuit 11_7, that is, the self-repair operation is described with reference to FIGS. This will be described with reference to FIG. FIG. 22 is a diagram illustrating a configuration of the integrated circuit 10 ′ when performing a self-repair operation according to the present embodiment, and FIG. 23 illustrates an operation when a defective output circuit is generated in the integrated circuit 10 ′. It is a timing chart figure.

  First, as shown in FIG. 22, in the integrated circuit 10 ', the output circuit 11_7 becomes defective and Flag7 is set to "1". Further, FlagA, FlagB, and FlagD to FlagG are “0”, and FlagC and FlagH to FlagK configured by incorporating Flag7 are “1” by the logical expression OR (see FIG. 20).

  Here, since FlagA, FlagB, and FlagD to FlagG are “0”, the switches SWA20 and SWA21 and the switches SWB1 to SWB6 perform the same operations as those in the normal operation already described. Therefore, here, DF_20 and DF_21, latch circuits DLA_R1, DLA_R2, DLA_G1, DLA_G2, DLA_B1, and DLA_B2, hold circuits DLB_R1, DLB_R2, DLB_G1, DLB_G2, DLB_B1, and DLB_B2 in the operation 11_11 Description is omitted.

  On the other hand, since FlagC and FlagH to FlagK are “1”, the SWA 22 switches the connection destination of the input unit D of the DF_23 from the output unit Q of the DF_22 to the output unit Q of the DF_21 as illustrated in FIG. . By this switching of SWA22, DF_22 and DF_23 are respectively supplied to latch circuits DLA_R3, DLA_G3, DLA_B3, DLA_R4, DLA_G4, and DLA_B4 at the same timing, in other words, grayscale data R3, G3, A selection signal is output in synchronization with the input timing of B3 and B3. As a result, the latch circuits DLA_R3 and DLA_R4 both receive the gradation data R3, the latch circuits DLA_G3 and DLA_G4 both acquire the gradation data G3, and the latch circuits DLA_B3 and DLA_B4 both acquire the gradation data B3. DF_24 to DF_26 sequentially select selection signals to the latch circuits DLA_R5 to DLA_R7, DLA_G5 to DLA_G7, and DLA_B5 to DLA_B7 in synchronization with the input timings of the gradation data R4 to R6, G4 to G6, and B4 to B6, respectively. Output. As a result, the latch circuits DLA_R5 to DLA_R7, DLA_G5 to DLA_G7, and DLA_B5 to DLA_B7 capture the grayscale data R4 to R6, G4 to G6, and B4 to B6, respectively, based on the input selection signal. In FIG. 23, the selection signal from each DF is described as Q (DF_20) to Q (DF_26), and the output from the output unit Q of each latch circuit DLA is Q (DLA_R1) to Q (DLA_B7). It is described.

  Since FlagH is “1”, the switches SWB7 to SWB9 switch the connection destination of the output terminals OUT7 to T9 from the output of the output circuits 11_7 to 11_9 to the output of the output circuits 11_10 to 11_12. Therefore, the gradation voltages corresponding to the gradation data R3, G3, and B3 output from the defective output circuits 11_7 to 11_9 are not output to any output terminal OUT. Further, the gradation voltages corresponding to the gradation data R3, G3, and B3 from the output circuits 11_10 to 11_12 are input to the output terminals OUT7 to OUT9. Further, since FlagI to FlagK are “1”, the switches SWB10 to SWB18 connect the output terminal OUT10 and the output circuit 11_13, connect the output terminal OUT11 and the output circuit 11_14, and similarly, the output terminal OUT12. The output circuit 11_15 to the output circuit 11_21 are connected to the output terminal OUT18, respectively. As a result, the gradation voltages corresponding to the gradation data R1 to R6, G1 to G6, and B1 to B6 are output to the output terminals OUT1 to OUT18, respectively.

  As described above, when a defect is detected in the output circuit 11, the latch circuit DLA, and the hold circuit DLB, the connection destination of the input portion D of each DF is switched, and the output circuits 11_1 to 11_19 and the output terminal OUT1 are switched. By switching the connection of .about.OUT18, the output circuit 11, the latch circuit DLA, and the hold circuit DLB that are determined to be defective are disconnected, the normal circuit is sequentially shifted, and a spare circuit is added to enable self-repair. Is realized.

  Further, the integrated circuit 10 ′ according to the present embodiment may detect a defect in the output circuit 11 using the first defect detection method described in the first embodiment. Specifically, the output circuit 11 (11_1, 11_4,...) Corresponding to R constituting the display color is output from the DAC circuit included in the output circuit 11_19 and the DAC circuit included in the output circuit 11_19. The output circuit 11 (11_2, 11_5,...) Corresponding to G constituting the display color is compared with the voltage output from the DAC circuit provided therein and the output. The voltage output from the DAC circuit included in the circuit 11_20 is compared in each operational amplifier included in the circuit 11_20, and the output circuit 11 (11_3, 11_6,...) Corresponding to B constituting the display color is included in the DAC included in the circuit 11_20. The voltage output from the circuit is compared with the voltage output from the DAC circuit included in the output circuit 11_21 in each operational amplifier included in the circuit.Accordingly, the determination circuit included in each output circuit 11 determines whether each output circuit 11 is good or bad based on the comparison result in each operational amplifier, and each output circuit 11 determines whether the control circuit is based on the determination result in each determination circuit. And Flag1 to Flag18 are output to each switch SWA and each switch SWB. Note that the configuration and method in which the integrated circuit 10 ′ performs self-repair based on the values of Flag 1 to Flag 18 are as described above.

[Embodiment 3]
Embodiment 3 of the present invention will be described below with reference to FIGS. In addition, the structure shown in Embodiment 3 is a modification of Embodiment 1, and a different location from Embodiment 1 is demonstrated, The description is abbreviate | omitted about the overlapping location.

(Configuration of self-healing circuit)
First, with reference to FIG. 24, a description will be given of a configuration in which a defective output circuit is replaced with a non-defective output circuit in the integrated circuit 10 ″ according to the present embodiment, and self-repair is performed. Similarly, the integrated circuit 10 ″ is an 18-output integrated circuit, but the number of outputs from the integrated circuit 10 ″ is not limited to 18.

  FIG. 24 is a block diagram showing a configuration of the integrated circuit 10 ″ in the normal operation according to the present embodiment. As shown in FIG. 24, the integrated circuit 10 ″ includes output terminals OUT1 to OUT18, DF_20 to DF_27 (hereinafter collectively referred to as DF), latch circuits DLA_R1 to DLA_R6, DLA_G1 to DLA_G6 and DLA_B1 to DLA_B6, spare latch circuits DLA_R7, DLA_G7, DLA_B7, DLA_R8, DLA_G8, and DLA_B8, Hereinafter, all latch circuits including the spare are collectively referred to as latch circuit DLA), hold circuits DLB_R1 to DLB_R6, DLB_G1 to DLB_G6 and DLB_B1 to DLB_B6, and spare hold circuits DLB_R7, DLB_G7, DLB_ 7, DLB_R8, DLB_G8, and DLB_B8 (hereinafter referred to as a hold circuit DLB when generically referring to all hold circuits including a spare), an output circuit 11_1 to 11_18, and a spare output circuit 11_19 to 11_24 (hereinafter, including a spare). When all output circuits are collectively referred to as an output circuit 11), switches SWA 26 to SWA 28, switches SWB 1 to SWB 18, and 32 switches SWREV are provided.

  In the present embodiment, the output section in the claims includes individual latch circuits DLA (for example, latch circuits DLA_R1, DLA_G1, DLA_B1, DLA_R2, DLA_G2, and DLA_B2) and hold circuits DLB (for example, latch circuits). This corresponds to a block consisting of DLB_R1, DLB_G1, DLB_B1, DLB_R2, DLB_G2, and DLB_B2) and an output circuit 11 (each of output circuits 11_1, 11_2, and 11_3). A block (for example, latch circuits DLA_R1, DLA_G1, and DLA_B) that includes a latch circuit DLA, a hold circuit DLB, and an output circuit 11 that are continuously arranged corresponding to positive and negative gradation voltages for each of the three primary colors RGB constituting the color. , DLA_R2, DLA_G2, DLA_B2 a latch circuit DLB_R1, DLB_G1, DLB_B1, DLB_R2, DLB_G2, corresponds to the block) consisting of DLB_B2 output circuit 11_1～11_6 Prefecture.

  Further, the sub output terminals in the claims correspond to the output terminals OUT1 to OUT18, respectively, and the output terminals in the claims have six output terminals arranged corresponding to the video signal output unit. (For example, OUT1 to OUT6).

  The pointer circuit 133 includes connection terminals that can be individually connected to SWA20 to SWA25, and the sub-connection terminals in the claims correspond to the individual sub-connection terminals. Corresponds to two connection terminals arranged corresponding to the video signal output unit.

  Note that the output circuit 11 included in the integrated circuit 10 ″ has the same internal circuit configuration as the output circuit 11 included in the integrated circuit 10 of the first embodiment, and is a DAC circuit (converter that converts gradation data into a gradation voltage signal). (Not shown), an operational amplifier (not shown) serving as a buffer circuit, a determination circuit that determines whether the operation of the output circuit is good, and a determination flag that indicates whether the operation of the determination circuit is good or bad.

  The output circuit 11 included in the integrated circuit 10 ″ is a circuit corresponding to only one side of the output of the positive side voltage and the output of the negative side voltage of the dot inversion drive, and in FIG. 24, the output circuits 11_1, 11_3, 11_5,. The odd-numbered output circuit 11 corresponds to the output of the positive side voltage, and the even-numbered output circuit 11 of the output circuits 11_2, 11_4, 11_6, ... corresponds to the output of the negative side voltage. In order to perform dot inversion driving, it is necessary to be able to output both positive and negative voltages to each output terminal OUT. Therefore, in the integrated circuit 10 ″, switching control of the switch SWREV by the control signal REV is required. By changing the connection between the output circuit and output terminal and the selection signal line, the sampling timing of gradation data is changed, and switching between the positive side voltage and the negative side voltage is realized. To have.

  In addition, the integrated circuit 10 ″ according to the present embodiment has three primary colors, that is, red (R) and green (which constitute display colors) via three DATAAR signal lines, DATAG signal lines, and DATAB signal lines, respectively. G) and blue (B) gradation data are input. That is, the integrated circuit 10 ″ is configured to drive a color display device in which display colors are configured by three colors of RGB.

  Each input part D of the latch circuits DLA_R1 to DLA_R8 is connected to the DATAR signal line, each input part D of the latch circuits DLA_G1 to DLA_G8 is connected to the DATAG signal line, and each input of the latch circuits DLA_B1 to DLA_B8 Part D is connected to the DATAB signal line.

  Each DF is connected in series to constitute a shift register 20 ″. Therefore, the shift register 20 ″ is based on the SP signal and the CLK signal input from the SP signal line and the CLK signal line. A selection signal is sequentially output from each DF to each latch circuit DLA, and a latch circuit DLA that takes in gradation data is selected.

  The gate part G of the latch circuits DLA_R1, DLA_G1 and DLA_B1 is connected to the output part Q of the DF20, and the gate part G of the latch circuits DLA_R2, DLA_G2 and DLA_B2 is connected to the output part Q of the DF21. The gate part G of the latch circuits DLA_R3, DLA_G3 and DLA_B3 is connected to the output part Q of the DF22, and the gate part G of the latch circuits DLA_R4, DLA_G4 and DLA_B4 is connected to the output part Q of the DF23, and the latch circuit The gate part G of DLA_R5, DLA_G5 and DLA_B5 is connected to the output part Q of the DF24, and the gate part G of the latch circuit DLA_R6, DLA_G6 and DLA_B6 is connected to the output part Q of the DF25, and the latch circuit DLA_R7, The gate portion G of LA_G7 and DLA_B7 is connected to the output Q of the DF26, the latch circuit DLA_R8, the gate portion G of DLA_G8 and DLA_B8 is connected to the output Q of the DF27.

  Here, each of the latch circuits DLA takes out the gradation data corresponding to each output terminal OUT1 from the inputted gradation data, and outputs it to each hold circuit DLB to which each is connected. Each hold circuit DLB holds the gradation data from each latch circuit DLA and then outputs it to each output circuit 11 to which it is connected. Note that the output circuit 11 according to the present embodiment includes a determination circuit and a determination flag, respectively, and further has a configuration for outputting Flags 1 to 18 indicating the pass / fail determination results of the output circuits 11_1 to 11_18. Yes. Flags 1 to 18 are “0” when the output circuit is a non-defective product, and “1” when the output circuit is defective.

  As shown in FIG. 24, the switches SWA26 to SWA28 switch the input destinations of DF_22, DF_24, and DF_26. The switching of each of the switches SWA26 to SWA28 is the value of FlagL to FlagN obtained from Flag1 to Flag18. Controlled by. Here, FlagL to FlagN are obtained by the logical expressions shown in FIG. Specifically, when FlagL is “0”, the switch SWA26 connects the input unit D of DF_22 and the output unit Q of DF_21. On the other hand, when FlagL is “1”, the input unit D of DF_22 and the input unit D of DF_20 are connected.

  Similarly, the switches SWA27 and SWA28 connect the input portions D of DF_24 and DF_26 to the output portions Q of DF_23 and DF_25 arranged one stage upstream when FlagM and FlagN are “0”. On the other hand, when FlagM and FlagN are “1”, the switches SWA27 and SWA28 connect the input portions D of DF_24 and DF_26 to the output portions Q of DF_22 and DF_24 arranged two stages upstream.

  As shown in FIG. 24, the switches SWB1 to SWB18 switch connection destinations of the output terminals OUT1 to OUT18. Switching of the switches SWB1 to SWB6 is controlled by the value of FlagL. The switching of the SWB 12 is controlled by the value of FlagO, and the switching of the switches SWB13 to SWB18 is controlled by the value of FlagP. Here, FlagO and FlagP are obtained by the logical expressions shown in FIG.

(Normal operation)
Next, an operation when no defective output circuit is generated in the integrated circuit 10 ″, that is, a normal operation will be described below.

  When no defective output circuit is generated, Flags 1 to 18 in the output circuits 11_1 to 11_18 are all “0”. Accordingly, FlagL to FlagP obtained by combining Flag1 to Flag18 by the logical expression OR are all “0”. Therefore, the switches SWA26 to SWA28 and the switches SWB1 to SWB18 in the integrated circuit 10 ″ are all connected as shown in FIG.

  The normal operation of the integrated circuit 10 ″ will be described below with reference to FIG. 25. FIG. 25 is a timing chart showing the operation when no defective output circuit is generated in the integrated circuit 10 ″.

  First, an SP signal of “H” indicating the start of operation of the integrated circuit 10 ″ is input to the input D of the DF_20. DF_20 takes in the value “H” of the SP signal in response to the rise of the CLK signal and outputs a selection signal of “H” from its output unit Q. As shown in FIG. 25, at the next rising edge of the CLK signal, since the SP signal is “L”, the output section Q of DF_20 is also “L”. In FIG. 25, the selection signals of DF_20 to DF_25 are described as Q (DF_20) to Q (DF_25).

  The output section Q of each DF is connected to the input section D of the next stage DF, and DF_20 to DF_27 constitute a shift register 20 ″. That is, Q (DF_20) which is a selection signal from DF_20 DF_21 outputs Q (DF_21) of “H” before Q becomes “L”, and then Q (DF_20) becomes “L”. This operation process is similarly performed in DF_20 to DF_25. As shown in FIG. 25, each DF is connected to each latch circuit DLA connected to each output unit Q in synchronization with the falling edge of the CLK signal. Select signals are output sequentially.

  The grayscale data corresponding to RGB is input to each latch circuit DLA via the DATAR signal line, the DATAG signal line, and the DATAB signal line. The gradation data input via the DATAR signal line, the DATAG signal line, and the DATAB signal line changes every time the CLK signal falls. That is, as shown in FIG. 25, the signal changes from R1 to R2, from G1 to G2, from B1 to B3,... In synchronization with the falling timing of the CLK signal. Each latch circuit DLA takes in gradation data input to the input unit D and outputs it to the output unit Q while the selection signal input to its gate unit G is “H”. That is, the latch circuits DLA_R1 to DLA_R6, DLA_G1 to DLA_G6, and DLA_B1 to DLA_B6 each take in gradation data input from the outside while each selection signal line from each DF is “H”, and output to the output unit Q To do. In FIG. 25, the outputs from the output unit Q of each latch circuit DLA are described as Q (DLA_R1) to Q (DLA_B6).

  Accordingly, the latch circuits DLA_R1 to DLA_R6 are sequentially selected in synchronization with the change timing of the grayscale data input via the data signal line DATAAR, and each latch circuit DLA corresponds to each output terminal OUT. Gradation data to be captured is captured. That is, the latch circuits DLA_R1 to DLA_R6 sequentially capture the grayscale data R1 to R6 by the selection signals sequentially output from the DFs. Similarly, the latch circuits DLA_G1 to DLA_G6 sequentially take in the gradation data G1 to G6 by the selection signals sequentially output from the DFs. Similarly, the latch circuits DLA_B1 to DLA_B6 sequentially take in the gradation data B1 to B6 by the selection signals sequentially output from the DFs.

  In FIG. 25, the subsequent operation is not described, but after all the latch circuits DLA have fetched the respective grayscale data, the integrated circuit 10 ″ receives the LS of “H” in the gate portion G of each hold circuit DLB. Output a signal. When the “H” LS signal is input, each hold circuit DLB outputs each gradation data input to its own input unit D from each output unit Q. As a result, the gradation data R1 to R6, G1 to G6, and B1 to B6 that are sequentially taken by the latch circuits DLA are input to the output circuits 11_1 to 11_18. The output circuits 11_1 to 11_18 convert the input grayscale data into grayscale voltages, buffer the converted grayscale voltages, and output the converted grayscale voltages to the output terminals OUT1 to OUT18 to which they are connected, respectively.

  Note that the DF_26 and DF_27, which are spare circuits, DLA_R7, DLA_G7, DLA_B7, DLA_R8, DLA_G8, and DLA_B8, and hold circuits DLB_R7, DLB_G7, DLB_B7, DLB_R8, DLB_G8, and B, depending on the input of the CLK signal and the LS signal The circuits 11_19 to 11_24 also operate. However, the output circuits 11_19 to 24 are not connected to any of the output terminals OUT1 to OUT18, and do not affect the output waveforms from the output terminals OUT1 to OUT18. Therefore, in the above description, spare circuits DF_26 and DF_27, which are spare circuits, latch circuits DLA_R7, DLA_G7, DLA_B7, DLA_R8, DLA_G8, and DLA_B8, hold circuits DLB_R7, DLB_G7, DLB_B7, DLB_R8, DLB_G8, and B Description of the operation of the circuits 11_19 to 11_24 is omitted.

(Self-repair operation)
Next, in the integrated circuit 10 ″, an abnormality occurs in the output circuit 11_7, and the operation when Flag7 is set to “1” by the determination circuit included in the output circuit 11_7, that is, the self-repair operation is described with reference to FIGS. This will be described with reference to FIG. FIG. 26 is a diagram showing a configuration of the integrated circuit 10 ″ when the self-repair operation is performed according to the present embodiment, and FIG. 27 shows an operation when a defective output circuit is generated in the integrated circuit 10 ″. It is a timing chart figure.

  First, as shown in FIG. 26, in the integrated circuit 10 ″, the output circuit 11_7 becomes defective, and Flag7 is set to “1”. Further, according to the logical expression OR (see FIG. 24), FlagL and FlagN are “0”, and FlagM, FlagO, and FlagP configured by incorporating Flag7 are “1”.

  Here, since FlagL and FlagN are “0”, the switches SWA26 and SWA28 and the switches SWB1 to SWB6 perform the same operation as in the normal operation already described. Therefore, here, DF_20 and DF_21, latch circuits DLA_R1, DLA_R2, DLA_G1, DLA_G2, DLA_B1, and DLA_B2, hold circuits DLB_R1, DLB_R2, DLB_G1, DLB_G2, DLB_B1, and DLB_B2 in the operation 11_11 Description is omitted.

  On the other hand, since FlagM, FlagO, and FlagP are “1”, as shown in FIG. 26, the switch SWA27 switches the connection destination of the input unit D of DF_24 from the output unit Q of DF_23 to the output unit Q of DF_21. ing. By switching the SWA 27, as shown in FIG. 27, DF_22 and DF_24 are respectively supplied to the latch circuits DLA_R3, DLA_G3, DLA_B3, DLA_R5, DLA_G5, and DLA_B5 at the same timing, in other words, the gradation data R3, G3. , And B3 in synchronization with the input timing. As a result, the latch circuits DLA_R3 and DLA_R5 both receive the gradation data R3, the latch circuits DLA_G3 and DLA_G5 both acquire the gradation data G3, and the latch circuits DLA_B3 and DLA_B5 both acquire the gradation data B3. In addition, as a result of the switching of SWA 27, DF_23 and DF_25 are supplied to latch circuits DLA_R4, DLA_G4, DLA_B4, DLA_R6, DLA_G6, and DLA_B6 at the same timing, in other words, grayscale data R4, as shown in FIG. , G4, and B4 are output in synchronization with the input timing. As a result, the latch circuits DLA_R4 and DLA_R6 both receive the gradation data R4, the latch circuits DLA_G4 and DLA_G6 both acquire the gradation data G4, and the latch circuits DLA_B4 and DLA_B6 both acquire the gradation data B6.

  Further, DF_26 outputs selection signals to the latch circuits DLA_R7, DLA_G7, and DLA_B7 in synchronization with the input timings of the gradation data R5, G5, and B5, and DF_27 inputs the gradation data R6, G6, and B6. In synchronization with the timing, the selection signal is output to the latch circuits DLA_R8, DLA_G8, and DLA_B8. As a result, the latch circuits DLA_R7, DLA_R8, DLA_G7, DLA_G8, DLA_B7, and DLA_B8 capture the grayscale data R5, R6, G5, G6, B5, and B6, respectively, based on the input selection signal. In FIG. 27, the selection signal from each DF is described as Q (DF_20) to Q (DF_27), and the output from the output unit Q of each latch circuit DLA is Q (DLA_R1) to Q (DLA_B8). It is described.

  Since FlagO is “1”, the switches SWB7 to SWB12 switch the connection destinations of the output terminals OUT7 to OUT12 from the outputs of the output circuits 11_7 to 11_12 to the outputs of the output circuits 11_13 to 11_18. Therefore, the gradation voltages corresponding to the gradation data R3, G3, B3, R4, G4, and B4 output from the defective output circuits 11_7 to 11_12 are not output to any output terminal OUT. Further, gradation voltages corresponding to the gradation data R3, G3, B3, R4, G4, and B4 from the output circuits 11_13 to 11_18 are input to the output terminals OUT7 to OUT12. Further, since FlagP is “1”, the switches SWB13 to SWB18 connect the output terminal OUT13 and the output circuit 11_19, connect the output terminal OUT14 and the output circuit 11_21, and connect the output terminal OUT15 and the output circuit 11_23, respectively. Are connected, the output terminal OUT16 and the output circuit 11_20 are connected, the output terminal OUT17 and the output circuit 11_22 are connected, and the output terminal OUT18 and the output circuit 11_24 are connected. As a result, the gradation voltages corresponding to the gradation data R1 to R6, G1 to G6, and B1 to B6 are output to the output terminals OUT1 to OUT18, respectively.

  As described above, when a defect is detected in the output circuit 11, the latch circuit DLA, and the hold circuit DLB, the connection destination of the input portion D of each DF is switched, and the output circuits 11_1 to 11_19 and the output terminal OUT1 are switched. By switching the connection of .about.OUT18, the output circuit 11, the latch circuit DLA, and the hold circuit DLB that are determined to be defective are disconnected, the normal circuit is sequentially shifted, and a spare circuit is added to enable self-repair. Is realized.

  Further, the integrated circuit 10 ″ according to the present embodiment may detect a defect in the output circuit 11 by using the first defect detection method described in the first embodiment. Specifically, each output circuit 11 is detected. Is supplied with an output voltage from the DAC provided in the spare output circuit 11 having the same primary color constituting the display color and the same polarity of the gradation voltage in the dot inversion drive. The output circuit 11 compares the output voltage input from the DAC included in the spare output circuit with the output voltage from the DAC included in the output circuit 11 in the operational amplifier included in the output circuit 11. Accordingly, the determination circuit included in each output circuit 11 In each of the operational amplifiers, whether each output circuit 11 is good or bad is determined based on the comparison result of each operational amplifier, and each output circuit 11 is controlled based on the determination result in each determination circuit. Beauty each switch SWA and the switches SWB, and outputs the Flag1～Flag18. Note that based on the value of Flag1～Flag18, configurations and methods integrated circuit 10 'do the self-healing is as already mentioned.

  Furthermore, the integrated circuit 10 ″ according to the present embodiment may detect a defect in the output circuit 11 using the first defect detection method described in the first embodiment. Specifically, each output circuit 11 may be detected. 24, the output voltages from the DACs provided in the output circuits 11 adjacent to each other are compared in the operational amplifiers provided in the output circuits 11. The output circuit 11_1 outputs the output voltage from the DAC provided in the output circuit 11_1. The output voltage from the DAC included in the output circuit 11_2 is compared with the operational amplifier included in the output circuit 11_2. The output circuit 11_2 compares the output voltage from the DAC included in the output circuit 11_1 and the output voltage from the DAC included in the output circuit 11_1. The output circuits 11_3 and 11_4, 11_5 and 11_6,. As a result, each output circuit 11 determines whether each output circuit 11 is good or bad based on the comparison result of each operational amplifier in the determination circuit included in each output circuit 11. Based on the determination result, Flag1 to Flag18 are output to the control circuit, each switch SWA, and each switch SWB. Note that the configuration and method in which the integrated circuit 10 ″ performs self-repair based on the values of Flag1 to Flag18 have already been described. As stated.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The drive circuit of the present invention may be configured as follows.

(First configuration)
An output terminal connected to the display device, an output circuit block including an output circuit connectable to the output terminal, a spare output circuit block including a spare output circuit connectable to the output terminal, and
A drive circuit for driving the display device, wherein the output is determined to be defective when the determination result of the determination unit is defective. The output circuit including the spare output circuit block was sequentially transferred to the output terminal to which the circuit was connected, and a switching circuit for invalidating the output circuit determined to be defective from the output circuit block was provided. A drive circuit characterized by the above.

(Second configuration)
A plurality of sampling circuits that sequentially capture display data based on pulse signals generated by the shift register, a display output circuit connected to each of the sampling circuits, and a determination unit that determines whether the output circuit is good or bad A sampling circuit connected to the output circuit determined to be defective by switching the pulse signal when the determination result of the determination unit is defective. A drive circuit comprising a switching circuit that invalidates data sampling of the output circuit determined to be defective by invalidating and sequentially shifting the plurality of sampling circuits.

(Third configuration)
According to the first configuration or the second configuration, the preliminary output circuit is provided in units of colors constituting the display pixel, and the output of the unit including the output circuit determined to be defective is invalidated and switched. Driving circuit.

(Fourth configuration)
A drive circuit comprising the preliminary output circuit according to the third configuration in units of three outputs, wherein the three outputs including the output circuit determined to be defective are invalidated and switched.

(Fifth configuration)
A first configuration characterized in that a preliminary output circuit is provided in units of integer multiples of color units constituting display pixels, and switching is performed by invalidating an output of integer multiples of the units including the output circuit determined to be defective. Or the drive circuit as described in a 2nd structure.

(Sixth configuration)
A drive circuit comprising the spare output circuit according to the fifth configuration in units of 6 outputs, wherein the 6 outputs including the output circuit determined to be defective are invalidated and switched.

(Seventh configuration)
The drive circuit according to the fifth configuration or the sixth configuration, which corresponds to dot inversion drive.

  The present invention provides an integrated circuit for driving a display device and a display device provided with the drive circuit, which include specific means for detecting a defect in the output circuit and self-repairing, and can easily cope with the malfunction of the output circuit. In particular, it can be used for large liquid crystal display devices and high-definition televisions.

It is a block diagram which shows the structure of the integrated circuit in the case of performing normal operation based on Embodiment 1 of this invention. FIG. 3 is a timing chart illustrating an operation when no defective output circuit is generated in the integrated circuit according to the first embodiment of the present invention. It is a block diagram which shows the structure of the integrated circuit in the case of performing self-repair operation | movement based on Embodiment 1 of this invention. FIG. 3 is a timing chart illustrating an operation when a defective output circuit is generated in the integrated circuit according to the first embodiment of the present invention. It is a block diagram which shows the structure which detects the malfunction in a normal output circuit using the backup output circuit based on Embodiment 1 of this invention. It is a flowchart figure which shows the 1st procedure of the operation check test in the 1st malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the 2nd procedure of the operation check test in the 1st malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the 3rd procedure of the operation check test in the 1st malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the 4th procedure of the operation check test in the 1st malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the 5th procedure of the operation check test in the 1st malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the procedure which self-repairs after the 1st malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the process sequence from power-on of a display apparatus to Embodiment 1 of this invention until it performs an operation check test and transfers to normal operation. It is a block diagram which shows the structure which detects a malfunction for the output circuit based on Embodiment 1 of this invention by making two adjacent output circuits into a set. It is a flowchart figure which shows the 1st procedure of the operation check test in the 2nd malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the 2nd procedure of the operation check test in the 2nd malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the 3rd procedure of the operation check test in the 2nd malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the 4th procedure of the operation check test in the 2nd malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the 5th procedure of the operation check test in the 2nd malfunction detection method based on Embodiment 1 of this invention. It is a flowchart figure which shows the procedure which invalidates the output circuit determined to be bad and self-repairs according to Embodiment 1 of the present invention. It is a block diagram which shows the structure of the integrated circuit in the case of performing normal operation based on Embodiment 2 of this invention. FIG. 10 is a timing chart illustrating an operation when no defective output circuit is generated in the integrated circuit according to the second embodiment of the present invention. It is a block diagram which shows the state of the integrated circuit in the case of performing self-repair operation | movement based on Embodiment 2 of this invention. It is a timing chart figure showing operation when a defective output circuit occurs in an integrated circuit concerning Embodiment 2 of the present invention. It is a block diagram which shows the structure of the integrated circuit in the case of performing normal operation based on Embodiment 3 of this invention. FIG. 9 is a timing chart illustrating an operation when a defective output circuit is not generated in the integrated circuit according to the third embodiment of the present invention. It is a block diagram which shows the state of the integrated circuit in the case of performing self-repair operation | movement based on Embodiment 3 of this invention. FIG. 9 is a timing chart illustrating an operation when a defective output circuit is generated in an integrated circuit according to a third embodiment of the present invention. It is a block diagram which shows the structure of the semiconductor integrated circuit for a liquid crystal drive in a prior art example. It is a figure which shows the specific structure of the semiconductor integrated circuit for a liquid crystal drive provided with the shift register, the latch circuit, the hold circuit, and the output circuit in a prior art example.

Explanation of symbols

1_1 to 1_20 operational amplifier 2a, 2b switch 3_1 to 3_20 determination circuit (determination unit)
4_1 to 4_20 determination flag 5_1 to 5_20 pull-up / pull-down circuit 10, 10 ′, 10 ″ integrated circuit (drive circuit)
20, 20 ', 20 "shift register (selection unit)
11_11_24 Output circuit (video signal output unit, output unit)
DAC_1 to DAC_18 Digital-analog converter DF_1 to DF_27 D-flip-flop DLA_1 to DLA_19 Latch circuit (video signal output unit, output unit)
DLA_R1 to DLA_R8 latch circuit (video signal output unit, output unit)
DLA_G1 to DLA_G8 latch circuit (video signal output unit, output unit)
DLA_B1 to DLA_B8 latch circuit (video signal output unit, output unit)
DLB_1 to DLB_19 hold circuit (video signal output unit, output unit)
DLB_R1 to DLB_R8 hold circuit (video signal output unit, output unit)
DLB_G1 to DLB_G8 hold circuit (video signal output unit, output unit)
DLB_B1 to DLB_B8 hold circuit (video signal output unit, output unit)
OUT1-OUT18 output terminals (output terminals, sub output terminals)
SWA1 to SWA28 switch SWB1 to SWB18 switch (connection switching unit)

Claims (8)

M output terminals (m is a natural number of 2 or more) connected to the display device;
At least m + 1 video signal output units capable of converting digital video data captured from the outside into a video signal and outputting the video signal to the output terminal;
A determination unit for determining the quality of each of the video signal output units;
A drive circuit including a connection switching unit that switches connection between the output terminal and the video signal output unit according to a determination result by the determination unit,
The connection switching unit
When all the video signal output units are determined to be good by the determination unit, the h-th video signal output unit is connected to the h-th output terminal (h is a natural number equal to or less than m),
When the determination unit determines that the i-th (i is a natural number equal to or less than m) video signal output unit is defective, the j-th (j is a natural number equal to or less than i−1) output terminal is j-th. A drive circuit for connecting the video signal output unit and connecting the k + 1th video signal output unit to the kth (k is a natural number between i and m) output terminals. Among the plurality of video signal output units, comprising a selection unit for selecting a video signal output unit for capturing the digital video data,
The selection part
When the determination unit determines that all the video signal output units are good, the h-th video signal output unit serves as the video signal output unit that captures the digital video data corresponding to the h-th output terminal. Select
When the determination unit determines that the i-th video signal output unit is defective, the video signal output unit captures the digital video data corresponding to the n-th (n is a natural number equal to or smaller than i) output terminal. The nth video signal output unit is selected, and the k + 1th video signal output unit is selected as the video signal output unit that captures the digital video data corresponding to the kth output terminal. The drive circuit according to claim 1. Each output terminal comprises a plurality of sub output terminals equal to the number of primary colors of display pixels provided in the display device,
Each video signal output unit comprises a plurality of output units equal to the number of primary colors,
The determination unit, when determining that at least one of the plurality of output units constituting each of the video signal output units is defective, determines that the video signal output unit is defective. The drive circuit according to 1 or 2.   4. The drive circuit according to claim 3, wherein the number of primary colors is three. Each of the output terminals is composed of a plurality of sub output terminals equal to a number that is a natural number multiple of the number of primary colors of display pixels included in the display device
Each of the video signal output units comprises a plurality of output units equal to a natural number times the number of primary colors,
The determination unit, when determining that at least one of the plurality of output units constituting each of the video signal output units is defective, determines that the video signal output unit is defective. The drive circuit according to 1 or 2.   6. The drive circuit according to claim 5, wherein the number of primary colors is 3 and the natural number is 2. The selection unit includes a plurality of connection terminals connected to the output units in the number of primary colors.
7. The drive circuit according to claim 5, wherein the plurality of output units are connected to any one of the plurality of connection terminals in units of the number of primary colors.   A display device comprising the drive circuit according to claim 1.

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