JP3806333B2 - Semiconductor integrated circuit, semiconductor integrated circuit test apparatus, and semiconductor integrated circuit test method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit used for driving a liquid crystal, for example, a test apparatus for the semiconductor integrated circuit, and a test method for the semiconductor integrated circuit.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, with the increase in integration of semiconductor integrated circuits, the increase in the number of terminals of the semiconductor integrated circuit and the increase in the number of gradations have become remarkable. For example, a liquid crystal display capable of high resolution and capable of expressing many colors Has come to be realized.
[0003]
However, for example, when the number of liquid crystal driving output terminals in a liquid crystal driving semiconductor integrated circuit increases or the gray scale output voltage increases as the liquid crystal panel is multicolored, the liquid crystal driving semiconductor There has been a problem that testing of integrated circuits becomes difficult.
[0004]
That is, generally, in the test of the gradation output voltage of the liquid crystal driving semiconductor integrated circuit, it is necessary to test the D / A converter built in each output terminal. In this D / A converter test, Since it is necessary to determine whether a normal output voltage is output at every gradation output voltage value for each output terminal, the increase in the number of output terminals and the increase in gradation output voltage value result in an increase in the number of gradation output voltage values. The time required to make the determination increases.
[0005]
FIG. 1 shows a basic configuration of a liquid crystal driving semiconductor integrated circuit 100 having liquid crystal driving output terminals 110 for n pixels capable of outputting m grayscale output voltages as an example of a conventional semiconductor integrated circuit. This shows the general structure. Here, the gradation output voltage of the gradation voltage value corresponding to the gradation of each pixel is output from each of the output terminals 110. At this time, the data about the gradation of each pixel, that is, each output terminal The data of the gradation output voltage value to be output is input from the gradation data input terminal 102 as digital data.
[0006]
This digital data is converted into a gradation voltage of a predetermined gradation voltage value which is an analog value by a D / A converter provided for each output terminal 110, and this gradation voltage is required in each pixel. Is supplied to each output terminal 110 as a predetermined gradation voltage.
[0007]
Therefore, when testing whether or not the liquid crystal drive output terminal 110 is normal as described above, digital data corresponding to all gradations (1 to m gradations) is input to the gradation data input terminal 102. At the same time, it is necessary to detect whether or not the grayscale output voltage to be output from each output terminal 110 is output by detecting the grayscale voltage value output for each output terminal 110.
[0008]
Furthermore, when testing this grayscale output voltage, a high-accuracy DC voltage measuring instrument is required, and the settling time during DC measurement by the DC voltage measuring instrument is not short, so it increases in proportion to higher resolution. Thus, how to shorten the test time of the liquid crystal driving semiconductor integrated circuit 100 has been a problem.
[0009]
Although it is possible to shorten the test time by using a semiconductor integrated circuit test apparatus provided with a DC voltage measuring device for each output terminal to be tested, a plurality of DC voltage measuring devices are provided in this way. The provided semiconductor integrated circuit testing apparatus is extremely expensive and used only for a few applications such as research and development, and is not generally used.
[0010]
Therefore, as one of the prior arts aimed at shortening the test time of the semiconductor integrated circuit, Japanese Patent Laid-Open No. 10-2937 discloses upper limit expected value data for each gradation output voltage as shown in FIG. And memories 159 and 160 storing lower limit expected value data at predetermined addresses, D / A converters 154 and 155 for converting the upper limit expected value data and lower limit expected value data into predetermined upper limit expected value voltage and lower limit expected value voltage, An upper limit expected value comparator 152, a lower limit expected value comparator 153, and an upper limit expected value comparator for comparing the gradation output voltage from each output terminal of the semiconductor integrated circuit 151 to be tested with the upper limit expected value voltage and the lower limit expected value voltage 152 and the comparison result output from the lower limit expected value comparator 153 determines whether the gradation output voltage of the semiconductor integrated circuit 151 is good or bad. Constant determining decoder 158, and a semiconductor integrated circuit testing apparatus equipped with a digital function module 161 supplies predetermined digital data to the semiconductor integrated circuit 151 is disclosed.
[0011]
According to this configuration, the upper limit expectation for each gradation is obtained in real time by incrementing the addresses of the memories 159 and 160 in accordance with the gradation change of the gradation output voltage output from each output terminal of the semiconductor integrated circuit 151. A semiconductor integrated circuit test apparatus is set which can set a value voltage and a lower limit expected value voltage and can test a semiconductor integrated circuit 151 generating a multi-gradation voltage at high speed.
[0012]
[Problems to be solved by the invention]
However, in the conventional semiconductor integrated circuit test apparatus represented by the semiconductor integrated circuit test apparatus described in Japanese Patent Application Laid-Open No. 10-2937, the D / D comparator is used as the output signal comparator of the conventional semiconductor integrated circuit test apparatus. Since it is necessary to add an A converter, a memory for storing the value of the upper limit expected value voltage and the value of the lower limit expected value voltage, etc., an increase in the cost of the semiconductor integrated circuit test apparatus is inevitable.
[0013]
Furthermore, assuming the number of output terminals of the semiconductor integrated circuit to be tested, it is necessary to provide a test terminal, a test circuit, etc. in the semiconductor integrated circuit test apparatus in advance, so that the actual semiconductor device integrated circuit When the number of output terminals of the semiconductor integrated circuit to be tested is small in the test of 1, the test terminals and test circuits that are not used are generated in the test terminals and test circuits of the semiconductor integrated circuit test apparatus. In some cases, the configuration of the semiconductor integrated circuit test apparatus is wasted and the cost performance is lowered.
[0014]
An object of the present invention is to provide a semiconductor integrated circuit, a semiconductor integrated circuit test apparatus, and a semiconductor integrated circuit test method capable of determining the quality of a semiconductor integrated circuit at high speed and low cost with a simple configuration. .
[0015]
[Means for Solving the Problems]
The present invention has the following configuration.
[0016]
(1) A plurality of levels having different voltage values in stages according to the input of digital gradation data indicating the gradation voltage value to be output from each output terminal of a semiconductor integrated circuit having a plurality of gradation voltage output terminals. A gradation voltage wiring corresponding to the gradation voltage value to be output is selected from among the adjustment voltage wirings and connected to the output terminal, and the gradation voltage of the gradation voltage value to be output is output to the output terminal. A semiconductor integrated circuit having a D / A converter for outputting each time,
  Of the plurality of gradation voltage wirings,Indicates the first gradation voltage valueBinary data for making the gradation voltage wiring and other gradation voltage wirings have different binary values, and binary data for controlling the timing at which the binary data is supplied to the gradation voltage wiring Based on output control signalThe gradation voltage wiring indicating the first gradation voltage value at a predetermined timing is set to the first value, and the other gradation voltage wiring is set to the second value.A binarizing means is provided.
[0017]
In this configuration, the voltage value of the gradation voltage wiring of the D / A converter provided in the semiconductor integrated circuit that outputs each output terminal based on the input digital data such as image data corresponds to the digital data. The binarized data for binarizing so that the gradation voltage wiring and the other gradation voltage wirings have different values, and the binarized data are output to the gradation voltage wiring. Since the binarization means for binarizing at a predetermined timing by the binarized data output control signal for controlling the timing is provided, the grayscale voltage wiring to be selected in the D / A converter and other grayscale voltages The binarization wiring is binarized into different binarized data at a predetermined timing, and the output from each output terminal is binarized accordingly.
[0018]
Therefore, whether or not the gradation voltage wiring corresponding to the digital data input to the semiconductor integrated circuit is selected in the D / A converter when the semiconductor integrated circuit is inspected. It can be detected at high speed with a simple configuration such as a function test using the.
[0019]
(2) The binarizing means is an operational amplifier as an output voltage source of a D / A converter that allows a multi-value voltage to be output step by step.And a circuit for electrically disconnecting the gradation voltage wiring, A register for storing the binarized data, and a trie for controlling the output timing of the binarized data stored in the register to the plurality of gradation voltage wirings based on the binarized data output control signal. A state buffer is provided.
[0020]
In this configuration, the output value of the semiconductor integrated circuit is obtained by binarizing the voltage values of the plurality of gradation voltage wirings at a predetermined timing based on the predetermined binarized data and the binarized data output control signal. A circuit for binarizing the output of the operational amplifier of the output voltage source of the D / A converter, wherein the binarizing means for binarizing the output from the D / A converter enables the multi-value voltage to be freely output in stages; A register for storing binarized data, and a tristate buffer for controlling output timing of the binarized data stored in the register to the plurality of gradation voltage wirings based on a binarized data output control signal Since it is realized by adding to the semiconductor integrated circuit, the binarization means of the present invention is provided at low cost while suppressing the complexity of the circuit configuration of the semiconductor integrated circuit.
[0021]
(3)A test apparatus for a semiconductor integrated circuit applied to a test for a semiconductor integrated circuit according to (1) or (2),
  The digital gradation data indicating the first gradation voltage value, the gradation voltage wiring corresponding to the first gradation voltage value are set to the first value, and the other gradation voltage wirings are set to the second value. Whether the first value is output from the output terminal to which the first value is to be output among the plurality of output terminals.And determining means for determining whether the D / A converter is good or bad.
[0022]
In this configuration, a predetermined gradation voltage is output from each output terminal in accordance with the input predetermined digital gradation data, and at the time of the test, the predetermined binary data and the binary data output control signal are output. A semiconductor integrated circuit test apparatus capable of outputting binarized data from each output terminal at a predetermined timing based on digital gradation data indicating a predetermined gradation voltage value and the predetermined gradation voltage value The binarized data for which only the grayscale voltage wiring corresponding to is different from the other grayscale voltage wiring is input to the semiconductor integrated circuit, and the digital grayscale data and the binarized data are Judgment means is provided for judging whether the D / A converter is good or bad based on the binarized values output from the plurality of output terminals by matching the timing of reading.
[0023]
For this reason, it is not necessary to provide a DC voltage measuring instrument or the like in the semiconductor integrated circuit test apparatus, so that the configuration of the test apparatus itself is simplified and the semiconductor integrated test is performed at high speed.
[0024]
(4) The present invention is characterized in that output control means for dividing the plurality of output terminals into a predetermined number of output terminal groups and sequentially performing the determination based on the gradation output voltage for each output terminal group is provided.
[0025]
In this configuration, the test apparatus divides a plurality of output terminals provided in a semiconductor integrated circuit to be tested into a predetermined number of output terminal groups, and performs an output for determining a gradation output voltage for each output terminal group. Since the control means is provided, for example, by binarizing all the gradation voltage wirings corresponding to all the output terminals, the binarizing means requires a high current drive capability for the tristate buffer. The increase in cost for realizing the binarization means is prevented.
[0026]
(5)A test method of a semiconductor integrated circuit applied to the test of a semiconductor integrated circuit according to (1) or (2),
  The digital gradation data indicating the first gradation voltage value, the gradation voltage wiring corresponding to the first gradation voltage value are set to the first value, and the other gradation voltage wirings are set to the second value. Binarizing data to be input to the semiconductor integrated circuit;
  Whether the first value is output from the output terminal that should output the first value among the plurality of output terminalsA determination step of determining pass / fail of the D / A converter based on
It is characterized by including.
[0027]
In this configuration, a predetermined gradation voltage wiring is selected from a plurality of gradation voltage wirings provided in accordance with input predetermined digital gradation data, and connected to the output terminal by connecting each output terminal. Binarization that binarizes a voltage value of the predetermined grayscale voltage wiring differently from other grayscale voltage wiring when testing a semiconductor integrated circuit that outputs a predetermined grayscale voltage A step of determining whether or not the semiconductor integrated circuit is good by detecting whether or not a gradation voltage wiring to be selected is selected based on the digital gradation data indicating a predetermined gradation voltage value; Therefore, the quality of the semiconductor integrated circuit is determined at high speed and at low cost without using a DC voltage measuring device or the like.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor integrated circuit, a semiconductor integrated circuit test apparatus, and a semiconductor integrated circuit test method of the present invention will be described with reference to the drawings.
[0029]
FIG. 3 shows the configuration of the semiconductor integrated circuit 1 for driving a liquid crystal according to the present invention. A liquid crystal driving semiconductor integrated circuit 1 includes a D / A converter circuit (hereinafter referred to as a DAC circuit) 2, a gradation voltage operational amplifier 3, a binary control register 4, a binary output buffer 6, and a pointer shift register. 13, a latch circuit 14, and a reference power supply correction circuit 18. As terminals for inputting / outputting predetermined signals and the like to the outside, a clock input terminal 11, a gradation data input terminal 12, a LOAD signal input terminal 15, a first TEST terminal 5a, a second TEST terminal 5b, and an operational amplifier power supply control A terminal 17 and an output terminal 10 are provided.
[0030]
Here, the clock input terminal 11 is supplied with a predetermined clock signal serving as a reference for processing / operation of the present invention. There are x gradation data input terminals 12, and m = 2 for the number of gradation voltages m.^xIt becomes. Therefore, digital gradation data indicating any gradation voltage value among m gradation voltage values corresponding to the gradation to be displayed by each pixel of the liquid crystal is input from the x gradation data input terminals 12. The
[0031]
The LOAD signal input terminal 15 is supplied with a data LOAD signal indicating a timing at which data should be output from each latch circuit 14 to each DAC circuit 2. The first TEST terminal 5a and the second TEST terminal 5b are inputted with predetermined signals used when testing the liquid crystal driving semiconductor integrated circuit 1 from the test apparatus 50 for testing the liquid crystal driving semiconductor integrated circuit 1. The
[0032]
A signal for controlling the output state of the gradation voltage operational amplifier 3 is input to the operational amplifier power supply control terminal 17. A predetermined gradation voltage is output from the output terminal 10 to each pixel of the liquid crystal display. The liquid crystal driving semiconductor integrated circuit 1 according to this embodiment includes output terminals 10 for n pixels.
[0033]
The DAC circuit 2 converts the digital gradation data input to the gradation data input terminal 12 into a predetermined voltage value. The gradation voltage operational amplifier 3 is provided in the same number as the number of gradations of each pixel of the liquid crystal display, and supplies the gradation voltages generated by the reference power supply correction circuit 18 to the gradation voltage wiring L, respectively. .
[0034]
The binarization control register 4 is provided in the same number as the number of gradations of each pixel of the liquid crystal display, that is, the same number as the gradation voltage wiring L, and the gradation voltage wiring L is set to a high level or a low level. Stores digitized data. The binary output buffer 6 controls the output timing of the binarized data output from the binarization control register 4 to the gradation voltage wiring L. The pointer shift register 13 selects the latch circuit 14 in which the digital gradation data input from the gradation data input terminal 12 is to be stored. The latch circuit 14 temporarily holds digital gradation data to be supplied to the DAC circuit 2.
[0035]
In this configuration, digital gradation data for n pixels inputted from the gradation data input terminal 12 to the liquid crystal driving semiconductor integrated circuit 1 is selected by the latch circuit to be stored in the pointer shift register 13 and n pieces of data. Stored in each of the latch circuits 14. The digital gradation data stored in the latch circuit 14 is transferred from the latch circuit 14 to the DAC circuit 2 when a pulse signal indicating the output timing to the DAC circuit 2 input from the LOAD signal input terminal 15 is input. .
[0036]
In the DAC circuit 2, one of the m gradation voltage wirings L is selected based on the digital gradation data. In the liquid crystal driving semiconductor integrated circuit 1, the signal on the gradation voltage wiring L of each DAC circuit 2 becomes an output from the output terminal 10. Therefore, in the normal use state, the signal is selected in each DAC circuit 2. The voltage value of the gradation voltage wiring L becomes the voltage value of the gradation output voltage from the output terminal 10.
[0037]
On the other hand, in the test state in which the liquid crystal driving semiconductor integrated circuit 1 is tested, the operational amplifier power supply control terminal 17 is used to set the gradation voltage operational amplifier 3 to the high resistance output state. The adjustment voltage wiring L is electrically disconnected. For this reason, in this test state, binary data, which will be described later, input to each gradation voltage wiring L is output from each output terminal 10 as it is.
[0038]
As described above, the first TEST terminal 5a is a terminal to which a latch pulse for storing binarized data is input to the binarization control register 4, and the second TEST terminal 5b is a binary output buffer 6. Is a terminal to which a signal for selecting and setting active (high level output state or low level output state) or inactive (high resistance output state) is input. Using the binarized data input from the terminal 5a and the binarized data output control signal input from the second TEST terminal 5b, the operation of the DAC circuit 2 of the liquid crystal driving semiconductor integrated circuit 1 is effectively tested. It is characterized by this.
[0039]
FIG. 4 shows the configuration of the first embodiment of the liquid crystal driving semiconductor integrated circuit 1 according to the present invention. FIG. 6 shows the test of the liquid crystal driving semiconductor integrated circuit 1 according to the first embodiment. It is a timing chart in the case.
[0040]
The digital gradation data input from the gradation data input terminal 12 is sequentially stored in n latch circuits 14 corresponding to the clock signal input from the clock input terminal 11. Each of the n latch circuits 14 is a register for recording data relating to a gradation voltage to be output from each of the n output terminals 10, and all the output terminals are received by n clock input signals input from the clock input terminal 12. Ten gradation voltage data can be stored.
[0041]
After storing the digital gradation data of all the output terminals 10 in the latch circuit 14 and receiving the pulse input from the LOAD signal input terminal 15, the digital gradation data stored in the latch circuit 14 is transferred to the respective DAC circuits 2. The
[0042]
The DAC circuit 2 selects one of the m grayscale voltage wirings L by turning on only one of the m switches configured according to the digital grayscale data. And connected to the output terminal 10. Therefore, a gradation voltage corresponding to the digital gradation data is output from each output terminal 10.
[0043]
On the other hand, the gradation voltage operational amplifier 3 is set to a high resistance output state by fixing the operational amplifier power supply control terminal 17 to an arbitrary level in the test state. For example, in the liquid crystal driving semiconductor integrated circuit 1 of the present embodiment, when the operational amplifier power supply control terminal 17 is set to a low level, the gradation voltage operational amplifier 3 is in a high resistance state, and the operational amplifier power supply control terminal 17 is set to a high level. In order to output the gradation voltage when set, the operational amplifier power supply control terminal 17 is fixed at a low level so that the gradation voltage operational amplifier 3 does not output the gradation voltage to each gradation voltage wiring L.
[0044]
Even if the operational amplifier power supply control terminal 17 is not built in the liquid crystal drive semiconductor integrated circuit 1, the operational amplifier power supply control terminal 17 can be added to the liquid crystal drive semiconductor integrated circuit 1, and the operational amplifier power supply control terminal 17 is added. By doing so, the configuration of the liquid crystal driving semiconductor integrated circuit 1 is not particularly complicated.
[0045]
In addition, a register or flag that can control the operational amplifier to a high resistance is added inside, and the output state of the operational amplifier 3 for gradation voltage is controlled by using these register or flag. The high-resistance output state of the voltage operational amplifier 3 may be set.
[0046]
After the digital gradation data of all the output terminals 10 are transferred to the DAC circuit 2, the binarized data is stored in the binarization control register 4a. The binarized data is generated by the test apparatus 50 of the semiconductor integrated circuit 1 and input from the gradation data input terminal 12. The binarized data is stored in the binarization control register 4a at a predetermined timing corresponding to a predetermined clock input signal in the binarization control register 4a.
[0047]
Data input to the binarization control register 4a may be input by adding a dedicated binarization data input terminal to the liquid crystal driving semiconductor integrated circuit 1 and using the binarization data input terminal. . Further, as a clock input signal used when storing the binarized data of the binarization control register 4a, a clock signal input from the clock input terminal 11 of the digital gradation data can be used. At this time, by adding a terminal for inputting a switching signal for switching between the latch circuit 14 and the binarization control register 4a, the clock input terminal 11 can be shared, and the configuration can be simplified. Can do.
[0048]
As described above, the second TEST terminal 5b is a terminal for inputting a signal for controlling the output of the binarized data stored in the binarization control register 4a to the gradation signal wiring. By setting the TEST terminal 5b to a high level, the tri-state buffer 6a sets the gradation voltage wiring L to a binary value of a high level or a low level according to the binarized data stored in the binarization control register 4a. can do. For this reason, the signal as the binarized data output from the tristate buffer 6a is supplied to the DAC circuit 2 through the gradation voltage wiring L. On the other hand, when the second TEST terminal 5b is set to a low level at this time, the tristate buffer 6a is in a high resistance state, and thus the binarized data of the binarization control register 4a is stored in the gradation voltage wiring L. And is not supplied to the DAC circuit 2.
[0049]
Note that, in a normal use state where the multi-level voltage level is generated from the gradation voltage operational amplifier 3, the second TEST terminal 5b is set to a low level, and thus the binarization of the binarization control register 4a is performed. It is possible to prevent the gradation voltage value of the gradation voltage wiring L from being influenced by data or the like and causing an error in the gradation voltage value.
[0050]
As an example of performing the test of the DAC circuit 2, the test apparatus 50 of the semiconductor integrated circuit 1 selects a first gradation voltage for the latch circuit 14 corresponding to the odd-numbered output terminal 10 (10a, 10c, etc.). The data is stored, and the gradation data for selecting the second gradation voltage is stored in the latch circuit 14 corresponding to the even-numbered output terminal 10 (10b, 10d, etc.). After the gradation data is stored in the latch circuit 14, the test apparatus 50 of the semiconductor integrated circuit 1 inputs the pulse signal to the LOAD signal input terminal 15 at a predetermined timing, whereby the digital gradation data is predetermined. At this timing, the data is transferred from the latch circuit 14 to the DAC circuit 2.
[0051]
After the gradation data is transferred to the DAC circuit 2, only the first register of the binarization control register 4a is set to high level, and the other (m−1) registers are set to low level data. The binarized data to be stored is stored in the binarization control register 4a, and only the grayscale voltage wiring L of the first grayscale voltage is set to the high level, and the other (m−1) grayscale voltages are set. The wiring L is set to a low level.
[0052]
At this time, the second TEST terminal 5b is set to a high level, and the gradation voltage operational amplifier 3 is set to a high resistance output state. By these setting operations, a high level is output from the odd-numbered output terminals 10 (10a, 10c, etc.), and a low level is output from the even-numbered output terminals 10 (10b, 10d, etc.).
[0053]
Next, the binarized data for setting only the gradation voltage wiring L of the second gradation voltage to the high level and setting the other (m−1) gradation voltage wirings L to the low level. Is stored in the binarization control register 4a.
[0054]
At this time, high level data is stored in the second register of the binarization control register 4a, and low level data is stored in the other (m-1) registers. By these setting operations, a low level is output from the odd-numbered output terminals 10 (10a, 10c, etc.), and a high level is output from the even-numbered output terminals 10 (10b, 10d, etc.).
[0055]
Thereafter, the binarized data output from each output terminal 10 is tested using a function test function using a digital comparator. Then, input of digital gradation data corresponding to all output terminals 10 from gradation data input terminal 12, transfer of gradation data to DAC circuit 2 by LOAD signal from LOAD signal input terminal 15, and binarization control register By sequentially rewriting the binarized data 4a, a test is performed as to whether or not the DAC circuit 2 in the liquid crystal driving semiconductor integrated circuit 1 is operating normally.
[0056]
Here, when the grayscale output voltage is tested with a DC voltage measuring device, the settling time takes 1 ms to 3 ms, whereas when the function test function is used, one output is tested at a test rate of 1 μs or less. Is possible. Furthermore, if the function test function of the test apparatus 50 of the semiconductor integrated circuit 1 is used, all the output terminals 10 can be tested at the same time. By using this function test function, the liquid crystal can be driven in a short time. A test of the semiconductor integrated circuit 1 can be performed. In particular, even when various combinations of digital gradation data are written in the latch circuit 14 and the test is performed, the time required for the test does not increase significantly. It can be executed at the time of a test such as a test pattern in consideration of long inter-wiring interference and inter-data interference.
[0057]
FIG. 5 shows a configuration in which the output of the binarization control register 4b is output to the grayscale voltage wiring L using a tristate buffer 6b configured with a clock control inverter as the second embodiment. The binary output buffer 6 that outputs the binarized data of the binarization control register 4b to the gradation output wiring L may have any configuration as long as it is a tri-state buffer capable of realizing a high resistance output state. .
[0058]
Here, the tristate buffer 6b is connected to one gradation voltage wiring L, and outputs a high level output or a low level output from the output terminal via the DAC circuit 2. In this case, the tristate buffer A current driving capability of 6b is required. Assuming that a maximum of n transistors are simultaneously turned on in one gradation voltage wiring L, the tri-state buffer 6b drives a maximum of n transistors and outputs a signal from the n output terminals. Where current drive capability sufficient for output is required, the tristate buffer 6b having high current drive capability increases the chip area and increases the manufacturing cost.
[0059]
Thus, by providing output control means as the third embodiment, an increase in manufacturing cost due to an increase in the chip area of the tristate buffer 6b is prevented.
[0060]
FIG. 7 shows the configuration of the third embodiment of the present invention, and FIG. 8 shows a test timing chart of the DAC circuit shown in FIG. Here, as the output control means, the DAC circuit 2 is divided into two or more output terminal groups, and all the SWs of the DAC circuit 2 corresponding to the output terminal groups other than the output terminal group to be measured are turned off. Only in the DAC circuit 2 corresponding to the output terminal group to be measured, the SW of the gradation voltage wiring L corresponding to the digital gradation data can be turned on.
[0061]
For this reason, the maximum number of transistors that can be turned on simultaneously in one grayscale voltage wiring L can be reduced, so that the current drive capability required for the tristate buffer 6b is reduced. Thus, the cost of the tristate buffer 6b can be reduced.
[0062]
Digital gradation data is transferred from the gradation data latch circuit to the LOAD register 7 in the DAC circuit 2 by the gradation data LOAD signal 15. For the digital gradation data transferred to the LOAD register 7, the gradation data decoder circuit 8 selects one of the 64 SWs.
[0063]
The high resistance control register 9 is a register that selects only one output terminal group among n output terminals divided into four output terminal groups. For example, when the output of the high resistance register 9a is set to a high level and the outputs of the high resistance control registers 9b to 9d are set to a low level, only the output terminal group 10A is a signal on the gradation voltage wiring L 2 An output corresponding to the binarized data of the value control register 4a is performed. On the other hand, since the output terminal group 10B, the output terminal group 10C, and the output terminal group 10D are in a high resistance output state, no output is performed.
[0064]
When the output of the high resistance control register 9c is set to high level and the output of the high resistance control registers 9a, 9b, 9d is set to low level, the output terminal group 10C is a signal on the gradation voltage wiring L. Output corresponding to the binarized data of a certain binarization control register 4a is performed.
[0065]
In this manner, by sequentially switching the high resistance control register 9 set to a high level, at least one of the output terminal groups 10A, 10B, 10C, or 10D can be selected as a test target.
[0066]
As described above, in the DAC circuit 2 corresponding to the output terminal 10 set to the high resistance output state, all the SWs are set to the off state. This setting operation is input to the gradation data decoder circuit 8. It is controlled by the output signal of the high resistance control register 9 that has been set. Therefore, after the digital gradation data is transferred to the LOAD register 7 using this function, the output terminal groups (10A to 10D) are sequentially switched to turn on the single gradation voltage wiring L. Can be reduced to a maximum of n / 4. For this reason, it becomes possible to reduce the current drive capability of the transistor of the tristate buffer 6a that outputs a value corresponding to the binarized data of the binarization control register 4a, and suppresses an increase in chip size and an increase in cost. be able to.
[0067]
In the output control means shown in FIGS. 7 and 8, the output terminal group (10A to 10D) is divided into four, but the output terminal group (10A to 10D) is the current drive capability of the transistor of the tristate buffer 6a. It is possible to divide into arbitrary two or more output terminal groups according to the above. The output terminal other than the output terminal to be measured is set to the high resistance output state, and the high resistance control register 9 is used as a circuit for actively controlling only the group of output terminals to be measured. The output control means can also be realized by setting the terminals to the high resistance output state and inputting a signal for activating only the output terminal group to be measured.
[0068]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
[0069]
(1) A voltage value of a gradation voltage wiring of a D / A converter included in a semiconductor integrated circuit that outputs for each output terminal based on input digital data such as image data is set to predetermined binary data and 2 Since the binarization means for binarizing at a predetermined timing by the binarized data output control signal is provided, the gradation voltage wiring to be selected in the D / A converter and the other gradation voltage wiring are Since the binarized data is converted into different binary data at a predetermined timing and the output from each output terminal is also binarized accordingly, the D / A converter is used when the semiconductor integrated circuit is inspected. Whether or not a gradation voltage wiring corresponding to the digital data input to the semiconductor integrated circuit is selected inside, for example, a function test using a digital comparator It can be detected at high speed with a simple configuration of.
[0070]
(2) The voltage values of the plurality of gradation voltage wirings are binarized at a predetermined timing based on the predetermined binarized data and the binarized data output control signal, so that the output from the output terminal of the semiconductor integrated circuit A circuit for binarizing an output of an operational amplifier of an output voltage source of a D / A converter, wherein the binarizing means for binarizing the output allows a multi-value voltage to be freely output step by step; and the binarized data And a tristate buffer for controlling the output timing of the binarized data stored in the register to the plurality of gradation voltage wirings based on a binarized data output control signal Since it can be realized by adding to the circuit, the binarization means of the present invention can be provided at low cost while suppressing the complexity of the circuit configuration of the semiconductor integrated circuit.
[0071]
(3) A predetermined gradation voltage is output from each output terminal in accordance with the input predetermined digital gradation data, and at the time of the test, based on the predetermined binary data and the binary data output control signal A semiconductor integrated circuit test apparatus capable of outputting binarized data from each output terminal at a predetermined timing corresponds to digital gradation data indicating a predetermined gradation voltage value and the predetermined gradation voltage value. The binarized data for making only the gradation voltage wiring to be different from other gradation voltage wirings is input to the semiconductor integrated circuit, and the digital gradation data and the binarized data are read. The semiconductor integrated circuit includes determination means for determining the quality of the D / A converter based on the binarized values output from the plurality of output terminals with the same timing. It is possible to test devices simplify the configuration required for eliminating the test device itself equip a DC voltmeter or the like, can be tested of the semiconductor integrated high speed.
[0072]
(4) Output control means for dividing a plurality of output terminals provided in a semiconductor integrated circuit to be tested by a test apparatus into a predetermined number of output terminal groups and determining a gradation output voltage for each output terminal group For example, by binarizing all gradation voltage wirings corresponding to all output terminals, the binarizing means requires a high current drive capability for the tristate buffer. It is possible to prevent the increase in cost for realizing the binarization means.
[0073]
(5) A predetermined gradation voltage wiring is selected from a plurality of gradation voltage wirings provided in accordance with input predetermined digital gradation data and connected to the output terminal, whereby a predetermined gradation voltage wiring is selected from each output terminal. A binarization step for binarizing a voltage value of the predetermined gradation voltage wiring differently from other gradation voltage wirings when testing a semiconductor integrated circuit that outputs the gradation voltage; A determination step of determining whether or not the semiconductor integrated circuit is acceptable by detecting whether or not a gradation voltage wiring to be selected is selected based on the digital gradation data indicating a predetermined gradation voltage value. Therefore, the quality of the semiconductor integrated circuit can be determined at high speed and inexpensively without using a DC voltage measuring device or the like.
[0074]
Therefore, it is possible to provide a semiconductor integrated circuit, a semiconductor integrated circuit testing apparatus, and a semiconductor integrated circuit testing method capable of determining the quality of a semiconductor integrated circuit at high speed and low cost with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a diagram showing a basic configuration of a liquid crystal driving semiconductor integrated circuit.
FIG. 2 is a diagram showing a configuration of a conventional semiconductor integrated circuit test apparatus.
FIG. 3 is a diagram showing a configuration of a semiconductor integrated circuit for driving a liquid crystal according to the present invention.
FIG. 4 is a diagram showing a configuration of a liquid crystal driving semiconductor integrated circuit according to the first embodiment.
FIG. 5 is a diagram illustrating a configuration of a semiconductor integrated circuit for driving a liquid crystal according to a second embodiment.
FIG. 6 is a timing chart showing the operation of the present invention.
FIG. 7 is a diagram showing a configuration of a semiconductor integrated circuit for driving a liquid crystal according to a third embodiment.
FIG. 8 is a timing chart showing an operation in the third embodiment.
[Explanation of symbols]
1-Liquid crystal drive semiconductor integrated circuit
2-DAC circuit
3-Grayscale voltage operational amplifier
4-2 Binarization control register
5-TEST terminal
6 (6a, 6b) -2 value output buffer
7-LOAD register
8-tone data decoder circuit
9-High resistance control register
10-gradation voltage output terminal
11-clock input terminal
12-gradation data input terminal

Claims (5)

For a plurality of gradation voltages having different voltage values in stages according to the input of digital gradation data indicating the gradation voltage value to be output from each output terminal of a semiconductor integrated circuit having a plurality of gradation voltage output terminals. A wiring for gradation voltage corresponding to the gradation voltage value to be output is selected from the wiring and connected to the output terminal, and the gradation voltage of the gradation voltage value to be output is output for each output terminal. A semiconductor integrated circuit comprising a D / A converter
Binary data for making the gradation voltage wiring indicating the first gradation voltage value and the other gradation voltage wirings of the plurality of gradation voltage wirings different from each other, and the binary data The gradation voltage wiring indicating the first gradation voltage value at a predetermined timing based on a binary data output control signal for controlling the timing at which the gradation voltage wiring is supplied to the gradation voltage wiring is set to a first value, A semiconductor integrated circuit comprising binarizing means for setting other gradation voltage wirings to a second value . The binarizing means is a circuit for electrically disconnecting an operational amplifier of the output voltage source of the D / A converter and the gradation voltage wiring, which can freely output a multi-valued voltage step by step, and the binarized data And a tristate buffer for controlling the output timing of the binarized data stored in the register to the plurality of gradation voltage wirings based on the binarized data output control signal The semiconductor integrated circuit according to claim 1. A semiconductor integrated circuit test apparatus applied to a test of a semiconductor integrated circuit according to claim 1 or 2,
The digital gradation data indicating the first gradation voltage value, the gradation voltage wiring corresponding to the first gradation voltage value are set to the first value, and the other gradation voltage wirings are set to the second value. And binarized data to be input to the semiconductor integrated circuit, and based on whether or not the first value is output from the output terminal to which the first value is to be output among the plurality of output terminals. A test apparatus for a semiconductor integrated circuit, comprising: determination means for determining whether the D / A converter is good or bad. The output control means for dividing the plurality of output terminals into a predetermined number of output terminal groups and sequentially performing the determination based on a gradation output voltage for each output terminal group. Semiconductor integrated circuit testing equipment. A test method for a semiconductor integrated circuit applied to the test for a semiconductor integrated circuit according to claim 1,
The digital gradation data indicating the first gradation voltage value, the gradation voltage wiring corresponding to the first gradation voltage value are set to the first value, and the other gradation voltage wirings are set to the second value. Binarizing data to be input to the semiconductor integrated circuit;
A determination step of determining pass / fail of the D / A converter based on whether or not a first value is output from an output terminal that should output a first value among the plurality of output terminals ;
A method for testing a semiconductor integrated circuit, comprising:

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