KR101055193B1 - LCD and its driving method - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof, which can easily repair an error of a stage, comprising: a liquid crystal panel having a plurality of gate lines and a plurality of data lines perpendicular to each other; And a gate shift register for selecting any one of a plurality of gate driving pulses according to the logic of the input selection signal and outputting one of the gate driving pulses to one end of each gate line.

LCD, Repair, Redundancy, Stage, Shift Register

Description

The liquid crystal display device and the method for driving the same}

1 is a block diagram showing a driving circuit of a general liquid crystal display device

2 is a schematic configuration diagram of a liquid crystal display device to which a conventional redundancy structure is applied;

3 is a schematic structural diagram of a liquid crystal display according to a first embodiment of the present invention

4 is a schematic structural diagram of a gate shift register of FIG. 3;

5 is a circuit diagram illustrating a first stage, a second stage, and a selection unit provided in the stage unit of FIG. 4.

6 is a schematic configuration diagram of a liquid crystal display device according to a second embodiment of the present invention.

7 is a schematic diagram of a general data driver

8 is a schematic configuration diagram of a data shift register in a liquid crystal display according to a third embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

190: liquid crystal panel 160a: display area

160b: non-display area 150: stage portion

151: Gate Shift Register 170: Date Driver

170: selection signal line G: gate line                 

D: data line

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof that can easily repair a stage in which an error occurs without a separate repair process.

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness and low power consumption, and mobile type such as notebook computer monitor. In addition, it is being developed in various ways such as a television for receiving and displaying a broadcast signal, a monitor of a computer.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.                         

Therefore, in order to use a liquid crystal display as a general screen display device in various parts, development of high quality images such as high definition, high brightness, and large area is required while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

Such a liquid crystal display device may be broadly divided into a liquid crystal display panel displaying an image and a driving unit for applying a driving signal to the liquid crystal display panel, wherein the liquid crystal display panel has a predetermined space and is joined to each other. It consists of a liquid crystal layer injected between the glass substrate and the said 1st, 2nd glass substrate.

The first glass substrate (TFT array substrate) may include a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing a gate line and a data line, and a plurality of thin films which are switched by signals of the gate line to transfer the signal of the data line to each pixel electrode Transistors are formed.

The second glass substrate (color filter substrate) includes a black matrix layer for blocking light in portions other than the pixel region, an R, G, B color filter layer for expressing color colors, and a common electrode for implementing an image. Is formed.

The first and second glass substrates are bonded to each other by a seal material having a predetermined space by a spacer and having a liquid crystal injection hole, so that the liquid crystal is injected between the two substrates.                         

Hereinafter, a driving circuit of a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a driving circuit of a general liquid crystal display device.

As shown in FIG. 1, a plurality of gate lines G and a data line D are arranged in a direction perpendicular to each other to have a matrix-type pixel region, and the liquid crystal display panel 21. ) Is divided into a driving circuit unit 22 for supplying a driving signal and a data signal, and a backlight 28 for providing a constant light source to the liquid crystal display panel 21.

Here, the driving circuit unit 22 drives a gate to the data driver 21b for inputting a data signal to each data line of the liquid crystal display panel 21 and the gate lines G of the liquid crystal display panel 21. A gate driver 21a for applying a pulse, display data R, G, and B input from a driving system 27 of a liquid crystal display panel, vertical and horizontal synchronization signals Vsync, Hsync, a clock signal DCLK, and the like. A timing controller that receives a control signal and formats and outputs each display data, a clock, and a control signal at a timing suitable for each data driver 21b and the gate driver 21a of the liquid crystal display panel 21 to reproduce a screen. 23, a power supply unit 24 for supplying a voltage required for the liquid crystal display panel 21 and each part, and a digital input from the data driver 21b by receiving power from the power supply unit 24; A gamma reference voltage unit 25 for supplying a reference voltage necessary for converting data into analog data, a constant voltage VDD used in the liquid crystal display panel 21 using the voltage output from the power supply unit 24, DC / DC converter 26 for outputting a gate high voltage VGH, a gate low voltage VGL, a reference voltage Vref, a common voltage Vcom, and an inverter 29 for driving the backlight 28. ) Is configured.

The operation of the driving circuit of the general liquid crystal display device configured as described above is as follows.

That is, the timing controller 23 controls the display data R, G, and B, and the control signals such as the vertical and horizontal synchronization signals Vsync and Hsync and the clock signal DCLK, which are input from the driving system 27 of the liquid crystal display panel. Since the data driver 21b and the gate driver 21a of the liquid crystal display panel 21 provide the display data, the clock, and the control signal at a timing suitable for reproducing the screen, the gate driver 21a A gate driving pulse is applied to each gate line G of the liquid crystal display panel 21 and the data driver 21b inputs a data signal to each data line D of the liquid crystal display panel 21 in synchronization with the gate driving pulse. Display the input video signal.

The gate driver includes a plurality of integrated gate drive ICs, and each gate drive IC includes a shift register for sequentially supplying a scanning signal to each gate line.

As will be described in detail later, the shift register includes a plurality of stages, and each stage sequentially outputs a gate driving pulse to each gate line.

That is, the first stage of the stage receives the start pulse, the supply voltage and the clock signal and outputs the gate driving pulse to the first gate line of the gate line and outputs the gate driving pulse to the second stage.                         

Then, the second stage outputs the gate driving pulse to the second gate line by using the output (gate driving pulse), the supply voltage and the clock signal of the first stage.

Here, the gate driving pulse output to the second gate line is delayed by one period than the gate driving pulse output to the first gate line.

In this way, the remaining third to nth stages also receive the outputs (gate driving pulses) of the previous stages and output gate driving pulses delayed by one period from the gate driving pulses output from the previous stages, respectively. To the line.

Thus, each gate line is driven sequentially.

However, due to such a driving method, when an error occurs in one stage, all lower stages that use the output of the errored stage as an input also cause a malfunction.

In order to repair such an error, a liquid crystal display device having a redundancy structure has been developed.

2 is a schematic configuration diagram of a liquid crystal display device to which a conventional redundancy structure is applied.

As shown in FIG. 2, a liquid crystal display device having a conventional redundancy structure includes a plurality of gate lines G arranged in one direction and a plurality of data lines arranged in a direction perpendicular to the gate lines G. As shown in FIG. The first and second gate drivers and the data lines provided in the liquid crystal panel 90 and the non-display area 60b of the liquid crystal panel 90 to drive the gate lines G. It comprises a data driver 70 for.

Here, the first gate driver includes a first shift register 51a including a plurality of first stages 50a, and the second gate driver includes a second shift register including a plurality of second stages 50b. 51b is provided.

Specifically, each of the first stages 50a is connected to one side of each gate line G to supply gate driving pulses from one side of each gate line G, and each of the second stages 50b is It is connected to the other side of each gate line G, and supplies a gate drive pulse from the other side of each gate line G. As shown in FIG.

Here, the first shift register 51a and the second shift register 51b receive the same start pulse, supply voltage, and clock signal, and thus, the first and second stages provided in the shift registers 51a and 51b. 50a and 50b all work the same.

In addition, as described above, the first stages 50a provided in the first shift register 51a receive the output of the first stage 50a of each previous stage as an input and drive gates required for each gate line G. The pulses are sequentially supplied, and the second stages 50b also receive the output of each previous stage second stage 50b as an input and sequentially supply gate driving pulses required for each gate line G.                         

Here, as shown in FIG. 2, it is assumed that an error has occurred in any one of the second stages 50b provided in the second shift register 51b.

That is, if an error occurs in the second second stage 50b, the lower stages using the output of the second second stage 50b as an input due to the second second stage 50b in which the error occurs. That is, all of the third to nth second stages 50b also malfunction.

At this time, the output line of the second stage 50b in which the error occurs, that is, the output line of the second stage 50b connected to the other side of the second gate line G, is disconnected using laser equipment. (X mark in Fig. 2) prevents the output (gate drive pulse) of the second second stage 50b in which the error occurs from being applied to the second gate line G.

Then, the second gate in which the normal output (gate driving pulse) output from the second first stage 50a connected to one side of the second gate line G is separated from the output terminal of the second first stage 50a By flowing along the line G, the second gate line G is normally driven and input to the third second stage 50b.

Accordingly, the third second stage 50b to the nth second stage 50b all operate normally.

However, the liquid crystal display device having the conventional redundancy structure is repaired by the laser equipment as described above, and thus has the following problems.

First, since the expensive laser equipment as described above is required, a lot of costs are generated.

Second, when there are many stages in which errors occur, the repair process becomes complicated and the process becomes complicated.

Third, particles generated during laser irradiation may penetrate the peripheral pixel region and the driving circuit to cause a short circuit between circuits.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and includes a shift register that can select any one of a plurality of gate driving pulses and apply it to each gate line according to the logic of the selection signal, thereby generating an error. It is an object of the present invention to provide a liquid crystal display device and a driving method thereof, which can simply replace a stage with a normal stage by changing only the logic of the selection signal.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal panel having a plurality of gate lines and a plurality of data lines perpendicular to each other; And a gate shift register configured to select any one of a plurality of gate driving pulses according to the logic of an input selection signal and output the one end of each of the gate lines.

The gate shift register may include a stage unit including a pair of first and second stages configured to output the gate driving pulses corresponding to each gate line; And a selector configured to select and output one of the gate driving pulses of the first and second stages according to the input selection signal.

And a buffer for amplifying the gate driving pulses output from the selector and applying the gate driving pulses to the gate lines.

The second to nth stage portions except for the first stage portion of each stage portion included in the shift register may receive a gate driving pulse output from the stage of the previous stage as a start pulse.

And a gate shift register connected to the other end of each gate line and having a plurality of third stages.

A data driver for driving the data line is further provided, and the data driver includes a data shift register for selecting and outputting any one of a plurality of dot clock signals according to a logic of an input selection signal. do.

The data shift register may include a plurality of stage units including a pair of first and second stages for outputting the dot clock signal corresponding to each data line; And a selector configured to select and output one of the dot clock signals of the first and second stages according to the input selection signal.

Each of the selectors may receive a selection signal simultaneously through one selection signal line.

The selection unit is characterized in that for using a multiplexer.                     

In addition, the driving method of the liquid crystal display device according to the present invention configured as described above includes a plurality of gate lines and a plurality of data lines perpendicular to each other. Selecting one of the gate driving pulses and applying the same to a gate line according to a selection signal; And selecting another gate driving pulse from among the plurality of gate driving pulses and applying the same to the gate line in response to a second tanning signal when an error occurs in the selected gate driving pulse.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic configuration diagram of a liquid crystal display according to a first exemplary embodiment of the present invention, FIG. 4 is a schematic configuration diagram of the gate shift register of FIG. 3, and FIG. It is a circuit block diagram of a 1st stage, a 2nd stage, and a selection part.

In the liquid crystal display according to the first exemplary embodiment of the present invention, as shown in FIG. 3, a plurality of gate lines G arranged in one direction and a plurality of data arranged perpendicularly to the gate lines G are arranged. It is connected to the liquid crystal panel 190 having a line D and one side of each gate line G, and selects any one of a plurality of gate driving pulses according to the logic of the input selection signal SEL. The gate shift register 151 which outputs to the line G is comprised.

In detail, as illustrated in FIG. 4, the gate shift register 151 includes a plurality of stage units 150 for outputting a gate driving pulse to each gate line G. 150 includes a pair of first and second stages 150a and 150b for outputting the gate driving pulses.

That is, each stage unit 150 includes the first and second stages 150a and 150b as a pair, and the pair of first and second stages 150a and 150b are connected to one gate line G. Correspondingly, the gate driving pulse is output.

In addition, each stage unit 150 receives a selection signal SEL and gate driving pulses of the first and second stages 150a and 150b, and according to the logic of the selection signal SEL, the stage unit ( And a selector 150c for selecting and outputting any one of the gate driving pulses of the first stage 150a and the second stage 150b of the 150.

That is, when the selection unit 150c of each stage unit 150 receives the high logic selection signal SEL through the selection signal line 170, the input first and second stages 150a and 150b may be used. The gate driving pulse of the first stage 150a is selected and output from among the gate driving pulses of.

On the other hand, when the selector 150c receives the low logic selection signal SEL through the select signal line 170, the selector 150c may select one of the gate driving pulses of the first and second stages 150a and 150b. The gate driving pulse of the second stage 150b is selected and output.

Here, the selector 150c may be configured using a multiplexer.                     

The liquid crystal display further includes a buffer 180 that receives and amplifies the gate driving pulses output from the selectors 150c and supplies them to the gate lines G.

Here, each stage unit 150 uses the output (gate driving pulse) of the stage unit 150 at the front end as an input, and the gate driving is delayed by one period than the output (gate driving pulse) of the stage unit 150 at each front end. Output a pulse.

Therefore, the gate driving pulses output from the stage units 150 are supplied to the gate lines G, and the gate lines G are sequentially scanned.

As described above, the first and second stages 150a and 150b of each stage unit 150 apply a circuit configuration diagram as shown in FIG. 5 to sequentially apply the gate driving pulses to the respective gate lines G. FIG. Have

Here, since the first stage 150a and the second stage 150b of each stage unit 150 have the same circuit configuration, only the first stage 150a will be described.

As illustrated in FIG. 5, the first stage 150a is turned on or turned off according to the logic of the first clock signal CLKA, and when the first stage 150a is turned on, the first pulse 150 conducts a first pulse. The first PMOS transistor T1 to charge the node P1 and the first clock signal CLKA are turned on or turned off according to the logic of the first PMOS transistor T1 and the first supply voltage VDD is turned on when the first PMOS transistor T1 is charged. It is turned on or turned off according to the logic of the second PMOS transistor T2 that charges the second node P2 and the start pulse SP charged in the first node P1. The second PMOS transistor T3 supplies the second clock signal CLKB to the output line 200 and is turned on by the first supply voltage VDD charged in the second node P2. And a fourth PMOS transistor T4 that supplies the second supply voltage VSS to the output line 200.

In addition, the first stage 150a is turned on or turned off according to the logic of the start pulse SP charged in the first node P1, and the turn-on turns on the second supply voltage VSS. A second supply voltage which is turned on or turned off according to the logic of the fifth PMOS transistor T5 and the second clock signal CLKB, and is turned on through the fifth PMOS transistor T5 when turned on And a sixth PMOS transistor T6 which conducts (VSS) and charges the second node P2.

Here, the first supply voltage VDD or the second supply voltage VSS may be charged in the second node P2, and the first supply voltage VDD having low logic at the second node P1 may be charged. ) Is charged, the fourth PMOS transistor T4 connected to the second node P2 through the gate is turned on, and the second supply voltage VSS having the high logic at the second node P1 is When charged, the fourth PMOS transistor T4 is turned off.

The first stage 150a configured as described above outputs a gate driving pulse as an output and outputs the gate driving pulse to the source of the first NMOS transistor T8 of the selector 150c. The second stage 150a is configured in the same manner as the first stage 150a. The stage 150b outputs the gate driving pulse as an output and outputs the gate driving pulse to the source of the seventh PMOS transistor T7 of the selector 150c.

At this time, the selection signal SEL is applied to the gate of the first NMOS transistor T8 and the gate of the seventh PMOS transistor T7 through the selection signal line 170, and the selection signal SEL is high logic. In this case, the first NMOS transistor T8 is turned on, and the seventh PMOS transistor T7 is turned off so that the selector 150c passes through the turned on first NMOS transistor T8. The gate driving pulse of the first stage 150a is output.

On the contrary, when the selection signal SEL is low logic, the first NMOS transistor T8 is turned off and the seventh PMOS transistor T7 is turned on so that the selection unit 150c turns the turn on. The gate driving pulse of the second stage 150b is output through the turned-on seventh PMOS transistor T7.

On the other hand, the gate driving pulse of the first stage 150a or the second stage 150b output through the selection unit 150c and the buffer 180 is applied to the gate line G corresponding to the current stage unit 150. It is used as the gate driving pulse and at the same time as the start pulse SP of the next stage unit 150.

That is, the star pulse SP is applied only to the first and second stages 150a and 150b provided in the first stage unit 150, and the second SP is provided in the second to nth stage units 150. The first and second stages 150a and 150b receive the outputs of the first and second stages 150a and 150b provided in the previous stage unit 150 as start pulses SP.

In summary, the liquid crystal display device according to the first embodiment of the present invention does not require a separate repair apparatus such as a laser used in the related art, and merely changes the logic of the selection signal SEL to provide a necessary gate driving pulse. You can print

This will be described in more detail with an example.

First, assume that each gate line G of the liquid crystal display shown in FIG. 2 is driven by a gate driving pulse output by the high logic selection signal SEL.

That is, each gate line G of the liquid crystal display device receives a gate driving pulse output from the first stage 150a of each stage unit 150.

In this case, as shown in FIG. 2, it is assumed that an error occurs in any one of the stage units 150 (the second stage unit 150).

Specifically, assume that an error occurs in the first stage 150a of the second stage unit 150.

In this case, since each stage unit 150 uses the output of the stage unit 150 of the front end as an input, all of the third to nth stage units 150 including the second stage unit 150 are incorrect. The gate driving pulse is output.

In this case, if only the selection signal SEL is changed from high logic to low logic, the selection unit 150c may cause the second stage unit 150 in which the error occurs according to the changed selection signal SEL. The normal gate driving pulses output from the second stage 150b of each stage unit 150 instead of the error-produced gate driving pulses output from all stages 150a of the stage unit 150. Selected to apply to each gate line (G).                     

Meanwhile, another gate shift register 151 may be further provided in the non-display area 160b opposite to the gate shift register 151.

FIG. 6 is a schematic configuration diagram of a liquid crystal display according to a second exemplary embodiment of the present invention. Compared to the first exemplary embodiment of FIG. 5, a third stage is further provided.

For convenience of description, the gate shift register 151 provided in the left non-display area 160b based on the display area 160a of the liquid crystal panel 190 of FIG. 6 is referred to as a first gate shift register 151. The gate shift register 152 provided in the right non-display area 160b based on the display area 160a of the liquid crystal panel 190 will be referred to as a second gate shift register 152.

As described above, the first gate shift register 151 is provided with a plurality of stages 150 having a pair of first and second stages 150a and 150b, each stage 150 being a respective one. The gate line G is connected to one side of each gate line G.

The second gate shift register 152 is provided with a plurality of third stages 155, and the third stage 155 corresponds to each gate line G, respectively. It is connected to the other side of.

The third stage 155 also has the same circuit configuration as the first stage 150a and the second stage 150b provided in the stage unit 150, and the start pulse SP, the first and the second The supply voltages VDD and VSS and the first and second clock signals CLKA and CLKB are supplied.                     

Here, the start pulse SP, the first and second supply voltages VDD and VSS, and the first and second clock signals CLKA and CLKB are the first, second and third stages 150a and 150b. , 155 at the same time.

In this configuration, each of the gate lines G is driven by gate driving pulses input from one side and the other of both sides of the gate lines G, so that the gate driving pulses flowing along the respective gate lines G Delay can be prevented.

In addition, the stage unit 150 may be provided in a data shift register of a data driver.

7 is a schematic block diagram of a general data driver, and FIG. 8 is a schematic block diagram of a data shift register in a liquid crystal display according to a third exemplary embodiment of the present invention.

As illustrated in FIG. 7, the data driver 175 includes a data shift register unit 210 for shifting and outputting a dot clock signal Dot CLK, and R, G, and B digital image signals to the data shift register unit. A first latch 220 latched and output by a dot clock signal Dot CLK outputted at 210, and a digital R of each pixel output from the first latch 220 by an external latch clock signal; A second latch 230 for latching and outputting the G and B video signals again; a level shift 240 for outputting a voltage corresponding to the digital R, G, and B video signals output from the second latch 230; And a digital / analog converter 250 for outputting the digital video signal as an analog video signal according to the voltage output from the level shift 240.                     

Here, the data shift register 210 is for selecting and outputting any one of a plurality of dot clock signals Dot CLK. As shown in FIG. 8, the dot shift signal 210 may be connected to the first latch 220. And a plurality of stage units 350 for outputting the dot CLK, and each stage unit 350 pairs the first and second stages 350a and 350b for outputting the dot clock signal Dot CLK. Equipped with.

In addition, the stage unit 350 receives a selection signal SEL and a dot clock signal Dot CLK of the first and second stages 350a and 350b, and applies logic to the selection signal SEL. Accordingly, the apparatus further includes a selector 380 configured to select and output one of the dot clock signals Dot CLK of the first stage 350a and the second stage 350b included in each stage 350. It is.

That is, when the selection unit 380 of each stage unit 350 receives a high logic selection signal through the selection signal line 370, the dot clocks of the first and second stages 350a and 350b are input. The dot clock signal Dot CLK of the first stage 350a is output among the signals Dot CLK.

On the other hand, when the selector 380 receives the low logic selection signal SEL through the selection signal line 370, the dot clock signals of the first and second stages 350a and 350b are input. Of the dot CLK, the dot clock signal Dot CLK of the second stage 350b is output.

Here, the selector 380 may be configured using a multiplexer.

By changing the logic of the selection signal SEL, the data shift register 210 also blocks the output of the stage in which an error occurs, and can easily repair the stage in which the error occurs by supplying the output of the normal stage. have.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the liquid crystal display device and the driving method thereof according to the present invention have the following effects.

First, the repair process is simplified since the logic of the selection signal can be changed to replace a stage in which an error occurs with a normal stage.

Second, since there is no need for a conventional laser repair equipment, it is possible to reduce the cost according to the repair, it is possible to prevent a short circuit between the circuit by the particles generated during the laser irradiation.

Claims (10)

A liquid crystal panel having a plurality of gate lines and a plurality of data lines perpendicular to each other; A gate shift register having a plurality of gate stages for selecting any one of a plurality of gate driving pulses and outputting one of the plurality of gate driving pulses according to a logic of an input selection signal; Each gate stage unit includes a plurality of gate stages for outputting a plurality of gate driving pulses corresponding to a corresponding gate line, and a selection unit for selecting and outputting gate driving pulses from any one of the plurality of gate stages according to an input selection signal. Liquid crystal display device comprising a. The method of claim 1, And a plurality of gate stages included in each gate stage portion is a pair of first and second gate stages. The method of claim 2, And a plurality of buffers which amplify the gate driving pulses output from the selector of each gate stage unit and apply them to the respective gate lines. The method of claim 2, And the second to nth gate stage portions except for the first gate stage portion among the gate stage portions provided in the shift register receive the gate driving pulses output from the gate stage of the previous stage as start pulses. The method of claim 1, And a gate shift register connected to the other end of each gate line and having a plurality of third stages. The method of claim 1, A data driver for driving the plurality of data lines is further provided; The data driver comprises a data shift register having a plurality of data stages for selecting and outputting any one of a plurality of dot clock signals in accordance with logic of an input selection signal; Each data stage unit selects and outputs a plurality of data stages for outputting a plurality of dot clock signals corresponding to a corresponding data line, and selects and outputs dot clock signals from any one of the plurality of data stages according to an input selection signal. A liquid crystal display device comprising a portion. The method of claim 6, And a plurality of data stages included in each of the data stage units is a pair of first and second data stages. The method of claim 6, A plurality of selection units provided in the plurality of gate stage units receive selection signals simultaneously through one selection signal line; And a plurality of selection units provided in the plurality of data stage units to receive selection signals simultaneously through one selection signal line. The method according to claim 1 or 6, And a plurality of selectors provided in the plurality of gate stage units and a plurality of select units provided in the plurality of data stage units. In the driving method of a liquid crystal display device comprising a plurality of gate lines and a plurality of data lines perpendicular to each other, Selecting one of the gate driving pulses and applying the same to a gate line according to a first selection signal among a plurality of gate driving pulses; And selecting another gate driving pulse from among the plurality of gate driving pulses and applying the same to the gate line in response to a second tanning signal when an error occurs in the selected gate driving pulse. .

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