KR101137850B1 - A gate driver and a method for repairing the same - Google Patents

Abstract

The present invention relates to a gate driving circuit capable of repairing a failure of a stage and a repair method thereof, comprising: a first shift register having a plurality of first output lines connected to one end of a plurality of conductive lines; A second shift register having a plurality of second output lines connected to the other ends of the conductive lines; A signal amplifier for amplifying and outputting a signal supplied from the outside; At least one first repair line connected to an input terminal of the signal amplifier and arranged to intersect the first output lines; At least one second repair line connected to the output terminal of the signal amplifier and arranged to intersect the first output lines; At least one third repair line connected to the input terminal of the signal amplifier and arranged to intersect the second output lines; And at least one fourth repair line connected to the output terminal of the signal amplifier and arranged to intersect the second output lines.

Description

Gate driver circuit and repair method thereof {A gate driver and a method for repairing the same}

1 is a view showing a conventional gate driving circuit

2 illustrates a gate driving circuit according to an embodiment of the present invention.

3 is a view illustrating a signal attenuator connected to the signal amplifier of FIG.

FIG. 4 is a diagram for describing a method of recovering a gate driving circuit when a third stage included in the first shift register of FIG. 2 is inoperable.

* Explanation of symbols on the main parts of the drawings

ST201_L to ST20n_L: 1st to nth stage

ST201_R to ST20n_R: first to nth stage

ST20n + 1_L: dummy stage ST20n + 1_R: dummy stage

SR_L: First Shift Register SR_R: Second Shift Register

270: signal amplifier

CLK1 to CLK4: first to fourth clock pulses

GL1 to GLn: first to nth gate lines

241a to 241c: first to third output lines

200: display unit 222a_L: first repair line

222b_L: second repair line 222a_R: third repair line

222b_R: fourth repair line Vst: start pulse

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving circuit, and more particularly, to a gate driving circuit capable of repairing defects of a stage and a repair method thereof.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line so that a data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying control signals for controlling the gate driver and the data driver, and a liquid crystal display. It is provided with a power supply for supplying various drive voltages used in the device.

The timing controller controls the driving timings of the gate driver and the data driver and supplies a pixel data signal to the data driver. The power supply unit boosts or depressurizes the input power source to generate driving voltages such as a common voltage VCOM, a gate high voltage signal VGH, and a gate low voltage signal VGL required by the liquid crystal display device. The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driver includes a gate driving circuit to sequentially output the scan pulses as described above. In general, the gate driving circuit includes a shift register.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a view showing a conventional gate driving circuit.

In the conventional gate driving circuit, as shown in FIG. 1, the first shift register SR_L connected to one end of the gate lines GL1 to GLn provided in the display unit 100 and the gate lines GL1. And the second shift register SR_R connected to the other end of GLn).

Here, the first shift register SR_L includes a plurality of stages ST101_L to ST10n + 1_L that are connected to each other dependently. The remaining stages ST101_L to ST10n_L except the dummy stages ST101n + 1_L sequentially output scan pulses and supply the scan pulses to the gate lines GL1 to GLn provided in the display unit 100.

On the other hand, each stage ST101_L to ST10n + 1_L is enabled by receiving scan pulses from the stage located at the front end thereof, and is disabled by receiving the scan pulses from the stage located at the next stage.

For this operation, each stage ST101_L to ST10n_L has three output lines 141a_L, 141b_L, and 141c_L.

That is, each first output line 141a_L electrically connects between the stage and the corresponding gate line, and each second output line 141b_L electrically connects between the first output line 141a_L and the next stage. Each third output line 141c_L electrically connects the first output line 141a_L and the previous stage.

The second shift register SR_R also has the same configuration as the first shift register SR_L.

Meanwhile, when one of the stages ST101_L through ST10n + 1_L and ST101_R through ST10n + 1_R in the first and second shift registers SR_L and SR_R fails and is inoperable, the inoperative state All stages located behind the in stage will not be able to generate output.

For example, as illustrated in FIG. 1, when the third stage ST103_L in the first shift register SR_L is defective and the third stage ST103_L is inoperable, the third stage ( Scan pulses are not output from ST103_L).

Here, the fourth stage ST104_L located immediately after the third stage ST103_L is enabled by receiving the scan pulse from the third stage ST103_L as a start pulse. Thus, the third stage ST103_L ) Becomes inoperable, the fourth stage ST104_L is not enabled. Therefore, the fourth stage ST104_L also cannot output the scan pulse.

In addition, the fifth stage located immediately after the fourth stage ST104_L is enabled by receiving the scan pulse from the fourth stage ST104_L as a start pulse. Thus, the fourth stage ST104_L is scanned. Since the pulse is not outputted, the fifth stage is also not enabled.

In this manner, all the sixth to nth stages ST10n_L cannot output scan pulses.

Accordingly, the third to nth gate lines GL3 to GLn connected to the nth stage ST10n_L from the third stage ST103_L where the failure occurs may not be driven.

Of course, when all of the stages ST401_R to ST40n + 1_R provided in the second shift register SR2 operate normally, scan pulses output from the respective stages ST401_R to ST40n_R of the second shift register SR2 It is normally supplied to each gate line GL1 to GLn. That is, all of the gate lines GL1 to GLn are driven.

However, although the first and second gate lines GL1 and GL2 are supplied with scan pulses from the first and second shift registers SR1 and SR2, the first and second gate lines GL3 to n-th gate lines GL3 may be applied. Since GLn is supplied with only the scan pulse from the second shift register SR2, the difference between the first and second gate lines GL1 and GL2 and the third to nth gate lines GL3 to GLn varies in the charging speed. Indicates. Therefore, a luminance deviation may occur between the pixel cells connected to the first and second gate lines GL1 and GL2 and the pixel cells connected to the third to nth gate lines GL3 to GLn.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is operated by amplifying a scan pulse output from a normally driving stage and supplying the amplified scan pulses to both sides of a gate line to which a stage which is inoperable is connected. It is an object of the present invention to provide a gate driving circuit and a repair method thereof that can recover a stage in a disabled state.

According to an aspect of the present invention, there is provided a gate driving circuit including: a first shift register having a plurality of first output lines connected to one end of a plurality of conductive lines; A second shift register having a plurality of second output lines connected to the other ends of the conductive lines; A signal amplifier for amplifying and outputting a signal supplied from the outside; At least one first repair line connected to an input terminal of the signal amplifier and arranged to intersect the first output lines; At least one second repair line connected to the output terminal of the signal amplifier and arranged to intersect the first output lines; At least one third repair line connected to the input terminal of the signal amplifier and arranged to intersect the second output lines; And at least one fourth repair line connected to the output terminal of the signal amplifier and arranged to intersect the second output lines.

Here, the first shift register is characterized in that it comprises a plurality of stages for outputting a scan pulse through each of the first output line.

One end of the n th output line is connected to the n th stage and the other end is connected to the n th conductive line.

and a third output line for supplying scan pulses from the n−1 (n is a natural number greater than 2) stage to the nth stage.

The third output line may connect the first output line connected to the n−1 th stage and the n th stage.

and a fourth output line for supplying scan pulses from the n + 1th stage to the nth stage.

The fourth output line is connected between an n + 1th stage and a first output line connected to the nth stage.

The second shift register may include a plurality of stages for outputting a scan pulse through each of the second output lines.

One end of the n th output line is connected to the n th stage, and the other end thereof is connected to the n th conductive line.

and a third output line for supplying scan pulses from the n−1 (n is a natural number greater than 2) stage to the nth stage.

The third output line may connect the first output line connected to the n−1 th stage and the n th stage.

and a fourth output line for supplying scan pulses from the n + 1th stage to the nth stage.

The fourth output line is connected between an n + 1th stage and a first output line connected to the nth stage.

One end of the first and third repair lines may be connected to each other and commonly connected to an input terminal of the signal amplifier.

And a signal attenuator connected between one end of the first and third repair lines and an input terminal of the signal amplifier.

One end of the second and fourth repair lines may be connected to each other and commonly connected to an output terminal of the signal amplifier.

A first intersection point between any first output line and the second repair line is connected; A second intersection point between any second output line and the third repair line is connected; A third intersection point between the second arbitrary output line and the fourth repair line is connected; And a portion of the second output line located between the second intersection point and the third intersection point is disconnected.

The arbitrary first output line and the second optional second output line are connected to the same conductive line.

A first intersection point between any first output line and the second repair line is connected; a second intersection point between any second output line and the third repair line; A third intersection point between the second arbitrary output line and the fourth repair line is connected; A portion of the second output line located between the second intersection point and the third intersection point is disconnected; In addition, any stage provided in the first shift register may be electrically separated from the first output line.

The arbitrary first output line and the second optional second output line are connected to the same conductive line.

In addition, the repair method of the gate driving circuit according to the present invention for achieving the above object, the first shift register having a plurality of first output lines connected to one end of the plurality of conductive lines, and the other end of the conductive lines A second shift register having a plurality of connected second output lines, a signal amplifier for amplifying and outputting an externally supplied signal, and an input terminal connected to an input terminal of the signal amplifier and intersecting the first output lines Connected to at least one first repair line, an output terminal of the signal amplifier and at least one second repair line arranged to intersect the first output lines, and an input terminal of the signal amplifier. At least one third repair line arranged to intersect the second output lines, and an output terminal of the signal amplifier part; A repair method of a gate driving circuit including at least one fourth repair line connected to a ruler and arranged to intersect the second output lines, the repair method comprising: a first between an arbitrary first output line and the second repair line; Connecting the intersections; Connecting a second intersection point between any second output line and the third repair line: connecting a third intersection point between the second optional output line and the fourth repair line; Disconnecting a portion of the second output line located between the second intersection point and the third intersection point; And electrically separating an arbitrary stage provided in the first shift register from the first output line.

Here, the arbitrary first output line and the second optional second output line are connected to the same conductive line.

In addition, the repair method of the gate driving circuit according to the present invention for achieving the above object, the first shift register having a plurality of first output lines connected to one end of the plurality of conductive lines, and the other end of the conductive lines A second shift register having a plurality of connected second output lines, a signal amplifier for amplifying and outputting an externally supplied signal, and an input terminal connected to an input terminal of the signal amplifier and intersecting the first output lines Connected to at least one first repair line, an output terminal of the signal amplifier and at least one second repair line arranged to intersect the first output lines, and an input terminal of the signal amplifier. At least one third repair line arranged to intersect the second output lines, and an output terminal of the signal amplifier part; A repair method of a gate driving circuit including at least one fourth repair line connected to a ruler and arranged to intersect the second output lines, the repair method comprising: a first between an arbitrary first output line and the first repair line; Connecting the intersections; Connecting a second intersection point between the arbitrary first output line and the second repair line; Connecting a third intersection point between any second output line and the fourth repair line; Disconnecting a portion of the first output line located between the first intersection point and the second intersection point; And electrically separating an arbitrary stage provided in the second shift register from the second output line.

Here, the arbitrary first output line and the second optional second output line are connected to the same conductive line.

Hereinafter, a gate driving circuit according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a gate driving circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a gate driving circuit according to an exemplary embodiment of the present invention may include first and second shift registers SR_R having a plurality of first output lines 241a_L, and the first shift registers. First and second repair lines arranged to intersect the first output lines of SR_L, and third and fourth repair lines arranged to intersect the first output lines of the second shift register SR_R. do.

Here, the configuration of the first shift register SR_L will be described in more detail as follows.

The first shift register SR_L is connected to one end of the gate lines provided in the display unit through the first output lines.

The shift register SR includes first to nth stages ST201_L to ST20n_L and dummy stages ST20n + 1_L. Each of the stages ST201_L to ST20n + 1_L sequentially outputs scan pulses in order from the first stage ST201_L to the dummy stage ST20n + 1_L and supplies them to the display unit 200 of the liquid crystal panel. Here, the first to nth stages ST201_L to ST20n_L except the dummy stages ST20n + 1_L supply scan pulses outputted from the dummy stages ST20n + 1_L to the corresponding gate lines of the display unit 200. Therefore, the gate lines GL1 to GLn are sequentially driven in order from the first gate line GL1 to the nth gate line GLn.

These stages ST201_L to ST20n + 1_L are enabled in response to scan pulses from the stage positioned at the front end from the stage, and disabled in response to the scan pulses from the stage positioned at the rear end from the stage. Each enabled stage ST201_L to ST20n + 1_L receives one of at least two clock pulses having a phase difference, and supplies the same to the corresponding gate line as a scan pulse. In contrast, each disabled stage ST201_L to ST20n + 1_L outputs an off voltage source and supplies it to the corresponding gate line, thereby inactivating the corresponding gate line.

For example, the second stage ST202_L is enabled in response to the first scan pulse from the first stage ST201_L and is disabled in response to the third scan pulse from the third stage ST203_L. The enabled second stage ST202_L receives a second clock pulse CLK2 among the first to fourth clock pulses CLK1 to CLK4 having a phase difference, and scans the second clock line CL2 to a second gate line GL2. Supply as a pulse.

For this operation, each stage ST202_L to ST20n_L except for the first stage ST201_L and the dummy stage ST20n + 1_L has first to third output lines 241a_L to 241c_L.

That is, each first output line 241a_L electrically connects between the stage and the corresponding gate line, and each second output line 241b_L electrically connects between the first output line 241a_L and the next stage. Each third output line 241c_L electrically connects the first output line 241a_L and the previous stage.

For example, the first output line 241a_L of the second stage ST202_L electrically connects the second stage ST202_L and the first gate line GL1 to form the first output line of the second stage ST202_L. The second output line 241b_L electrically connects the first output line 241a_L and the third stage ST203_L of the second stage ST202_L to the third output line 241c_L of the second stage ST202_L. ) Electrically connects the first output line 241a_L and the first stage ST201_L of the second stage ST202_L.

Here, since no stage exists in front of the first stage ST201_L, the first stage ST201_L has first and second output lines 241a_L and 241b_L. That is, the first stage does not have a third output line 241c_L.

Since the stage does not exist at the rear end of the dummy stage ST20n + 1_L, and as described above, the dummy stage ST20n + 1_L does not supply scan pulses to the gate line. ST20n + 1_L has a third output line 241c_L. That is, the dummy stage ST20n + 1_L does not have the first and second output lines 241a_L and 241b_L.

Although not shown in the drawing, each stage ST201_L to ST20n_L may be disabled by receiving any one of the above-described clock pulses. In this case, each stage ST201_L to ST20n_L may be the first and second. Only the output line 241b_L is provided. That is, each stage ST201_L to ST20n_L need not have the third output line 241c_L. Therefore, in this case, the first shift register SR_L does not have a dummy stage ST20n + 1_L, and the nth stage ST20n_L provided in the first shift register SR_L has a first output line 241a_L. ) Only.

The second shift register SR_R also has the same configuration as the above-described first shift register SR_L.

However, each stage ST201_R to ST20n_R provided in the second shift register SR_R is connected to the other ends of the gate lines GL1 to GLn. Therefore, the first output lines 241a_R of the stages ST201_R to ST20n_R are also connected to the other ends of the gate lines GL1 to GLn.

The stages ST401_L to ST40n_n provided in the first shift register SR_L sequentially output scan pulses to sequentially drive the gate lines GL1 to GLn, and the second shift register SR_R. The stages ST401_R to ST40n_R included in the output driving pulses sequentially drive the gate lines GL1 to GLn sequentially. In this case, the pair of stages connected to the same gate line outputs a scan pulse at the same time to drive the gate line.

For example, the first stage ST401_L of the first shift register SR_L and the first stage ST401_R of the second shift register SR_R simultaneously output the first scan pulse to open the first gate line GL1. Drive it.

Meanwhile, the first and second repair lines 222a_L and 222b_L and the first output lines 241a are arranged to cross each other, and the first and second repair lines 222a_L and 222b_L and the first output lines are intersected. Since an insulating film is formed between 241a_L, the first and second repair lines 222a_L and 222b_L and the first output lines 241a_L are electrically separated from each other.

Of course, since an insulating film is formed between the third and fourth repair lines 222a_R and 222b_R and the first output lines 241a_R, the third and fourth repair lines 222a_R and 222b_R and the first output. The lines 241a_R are electrically separated from each other.

The first to fourth repair lines 222a_L, 222b_L, 222a_R, and 222b_R are connected to the signal amplifier 270.

The signal amplifier 270 receives a signal through its input terminal and amplifies the signal to a predetermined size. The amplified signal is then output through its output terminal.

One end of the first and third repair lines 222a_L and 222a_R is connected to an input terminal of the signal amplifier 270. In this case, one end of the first repair line 222a_L and one end of the third repair line 222a_R are connected to each other, and the connected portion is connected to an input terminal of the signal amplifier 270.

One end of the second and fourth repair lines 222b_L and 222b_R is connected to an output terminal of the signal amplifier 270. In this case, one end of the second repair line 222b_L and one end of the fourth repair line 222b_R are connected to each other, and the connected portion is connected to the output terminal of the signal amplifier 270.

On the other hand, the gate driving circuit according to an embodiment of the present invention may further include a signal attenuator.

3 is a view illustrating a signal attenuator connected to the signal amplifier of FIG. 2.

That is, in the gate driving circuit according to the exemplary embodiment of the present invention, as shown in FIG. 3, one end of the first and third repair lines 222a_L and 222a_R and the input terminal of the signal amplifier 270 are connected. A signal attenuating unit 370 connected to each other may be further provided.

The signal attenuator 370 reduces the magnitude of a signal to be supplied through the first and third repair lines 222a_L and 222a_R. The reason for reducing the signal as described above is that the magnitude of the signal applied to the first and third repair lines 222a_L and 222a_R is mostly larger than the signal that the signal amplification unit 270 can accept. to be.

Therefore, the signal amplification unit 270 may be stably operated by reducing the magnitude of the signal through the signal attenuation unit 370.

Here, the signal amplifier 270 may be replaced by a level shifter. The level shifter amplifies the magnitude of the clock pulses supplied from the timing controller to a size capable of driving the gate line, and the amplified clock pulses are transferred to the first and second shift registers SR_L and SR_R through the clock transmission line. In this role, the structure of the present invention can be satisfied by connecting the first to fourth repair lines 222a_L, 222b_L, 222a_R, and 222b_R to the level shifters.

When a failure occurs in one stage in the gate driving circuit according to the first embodiment of the present invention configured as described above, the method for recovering the gate driving circuit including the stage in which the operation is disabled will be described in detail as follows. same.

4 is a diagram for describing a method of recovering a gate driving circuit when a third stage included in the first shift register of FIG. 2 is inoperable.

As shown in FIG. 4, when the third stage ST203_L of the first shift register SR_L is inoperable, the third stage ST203_L generates no output.

That is, FIG. 4 illustrates a situation in which the first and second gate lines GL1 and GL2 are normally driven because the first and second stages ST201_L and ST202_L operate normally. Specifically, the third stage ST203_L Deactivates and indicates that the scan pulse cannot be output from the third stage ST203_L and the fourth stage ST204_L located at the rear end of the third stage ST203_L to the dummy stage ST20n + 1_L.

Therefore, the third to nth gate lines GL3 to GLn connected to the third to nth stages ST203_L to ST20n_L shown in FIG. 4 do not receive scan pulses.

In order to recover such a gate driving circuit, first, the first output line 241a_L and the second repair line 222b_L connected to the stage in the inoperable state, that is, the third stage ST203_L are electrically connected.

This electrical connection is performed by using a laser to the first output line 241a_L connected to the second repair line 222b_L and the first output line 241a_L (the third stage ST203_L of the first shift register SR_L). This can be achieved by welding the intersection 281a between

Subsequently, a stage for outputting a scan pulse to the third gate line GL3 connected to the third stage ST203_L in an inoperable state, that is, a first output connected to the third stage ST203_R of the second shift register SR_R. The line 241a_R and the fourth repair line 222b_R are electrically connected to each other.

The electrical connection is performed by using a laser to the first output line 241a_R connected to the fourth repair line 222b_R and the first output line 241a_R (the third stage ST203_R of the second shift register SR_R). This can be achieved by welding the intersection 281b between

Next, a stage for outputting a scan pulse to the third gate line GL3 connected to the third stage ST203_L in an inoperable state, that is, a first stage connected to the third stage ST203_R of the second shift register SR_R. The output line 241a_R and the third repair line 222a_R are electrically connected to each other.

This electrical connection is performed by using a laser to the first output line 241a_R connected to the third repair line 222a_R and the first output line 241a_R (the third stage ST203_R of the second shift register SR_R). This can be achieved by welding the intersection 281c between

Next, a stage for outputting a scan pulse to the third gate line GL3 connected to the third stage ST203_L that is in an inoperable state, that is, a third stage ST203_R and the third of the second shift register SR_R. The gate lines GL3 are electrically separated from each other.

To this end, a part of the first output line 241a_R connected to the third stage ST203_R of the second shift register SR_R is disconnected. In this case, the disconnection portion 299 is connected to a first output line 241a_R (a first stage ST203_R of the second shift register SR_R) positioned between the intersection 281b and the intersection 281c. Part of the output line 241a_R. Here, a part of the first output line 241a_R located between the intersections 281b and 281c is disconnected, so that the third repair line 222a_R and the fourth repair line 222b_R which are connected to the same first output line 241a_R are disconnected. ) Are electrically separated from each other.

Next, the third stage ST203_L which is in an inoperable state and the first output line 241a_L connected to the third stage ST203 are electrically disconnected. That is, the contact 399 between the output terminal of the third stage ST203 and the first output line 241a_L is disconnected.

In this way, the second repair line 222b_L electrically connects one end of the third gate line GL3 and an output terminal of the signal amplifier 270, and the fourth repair line 222b_R connects the third gate. The other end of the line GL3 and the output terminal of the signal amplifier 270 are electrically connected. As a result, the output terminals of the signal amplifier 270 are connected to both sides of the third gate line GL3.

The third repair line 222a_R includes a first output line 241a_R (a first output line connected to the third stage ST203_R of the second shift register SR_R) and an input terminal of the signal amplifier 270. Connect kerning electrically.

When the gate driving circuit according to the first embodiment of the present invention thus restored is operated, first stage ST201_L provided in the first shift register SR_L is enabled in response to the start pulse Vst. In this enabled state, the first clock pulse CLK1 is supplied from the first clock transmission line and outputs the first clock pulse CLK1 as a first scan pulse. The first scan pulse is supplied to the first gate line GL1 through its first output line 241a_L, and the second stage (via its first and second output lines 241a_L and 241b_L). ST202_L).

Of course, at this time, the first stage ST201_R provided in the second shift register SR_R also operates in the same manner as the first stage ST201_L provided in the first shift register SR_L.

Subsequently, the second stage ST202_L included in the first shift register SR_L is enabled in response to the first scan pulse from the first stage ST201_L, and transmits the second clock in the enabled state. The second clock pulse CLK2 is supplied from the line and output as the second scan pulse. Then, the second scan pulse is supplied to the second gate line GL2 through its first output line 241a_L and through the first and second output lines 241a_L and 241b_L of the third stage. ST203_L is supplied to the first stage ST201_L through its first and third output lines 241b_L and 241c_L.

Of course, at this time, the second stage ST202_R provided in the second shift register SR_R also operates in the same manner as the second stage ST202_L provided in the first shift register SR_L.

Since the third stage ST203_L provided in the first shift register SR_L is in an inoperable state, the third scan pulse is not output even though the second scan pulse is supplied from the second stage ST202_L. can not do it.

Meanwhile, the third stage ST203_R provided in the second shift register SR_R is enabled in response to the second scan pulse, and receives the third clock pulse from the third clock transmission line in the enabled state. It outputs as a 3rd scan pulse. The third scan pulse is supplied to the fourth stage ST204_R through its first and second output lines 241a_R and 241b_R. Therefore, the fourth to nth stages ST204_R to ST20n_R of the second shift register SR_R are sequentially driven.

In addition, the third stage ST203_R included in the second shift register SR_R transmits the third scan pulse to its first output line 241a_R, the first output line 241a_R and the third repair line It is supplied to the input terminal of the signal amplifier 270 through the intersection 281c between the 222a_R and the third repair line 222a_R.

Then, the signal amplifier 270 amplifies the third scan pulse and supplies the amplified third scan pulse to the second and fourth repair lines 222b_L and 222b_R through its output terminal. The third scan pulse supplied to the second repair line 222b_L is transmitted to the third gate line GL3 through one end of the third gate line GL3 and supplied to the fourth repair line 222b_R. The third scan pulse is transmitted to the third gate line GL3 through the other end of the third gate line GL3.

That is, the third gate line GL3 is driven by third scan pulses transmitted in both directions.

The third scan pulse output from the signal amplifier 270 may include a third stage of the second repair line 222b_L, the intersection 281a, and the first output line 241a_L (first shift register SR_L). The first output line 241a_L connected to the ST203_L, and the second output line 241b_L (the second output line 241b_L connected to the third stage ST203_L of the first shift register SR_L). The fourth stage ST204_L is supplied to the fourth stage ST204_L. Therefore, the fourth stage ST204_L may be enabled.

Accordingly, scan pulses may be sequentially output from the fourth stage ST204_L provided to the first shift register SR_L to the dummy stage ST20n + 1_L.

Although not shown in the drawings, when the third stage ST203_R included in the second shift register SR_R is in an inoperable state, the first repair line 222a_L and the first output line 241a_L (first). The intersection between the first output line 241a_L connected to the third stage ST203_L of the shift register SR_L is electrically connected, and the second repair line 222b_L and the first output line 241a_L (first shift) The intersection between the first output line 241a_L connected to the third stage ST203_L of the register SR_L is electrically connected to the fourth repair line 222b_R and the first output line 241a_R (second shift register). Electrically connect intersections between the first output lines 241a_R connected to the third stage ST203_R of SR_R, and first output lines 241a_L located between the intersections (the first shift register SR_L). A part of the first output line 241a_L connected to the third stage ST203_L of the By selecting the wire, the gate driving circuit can be restored.

On the other hand, in order to prepare for the case where the number of stages in an inoperable state is two or more, the gate driving circuit of the present invention includes two or more first repair lines 222a_L, two or more second repair lines 222b_L, and two The third repair line 222a_R and two or more fourth repair lines 222b_R may be provided.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the gate driving circuit and the repair method thereof according to the present invention have the following effects.

The gate driving circuit according to the present invention amplifies the scan pulse output from the stage of normal driving, and supplies the amplified scan pulse to both sides of the gate line to which the stage which is inoperable is connected to recover the inoperable state. Can be.

Claims (24)

A first shift register having a plurality of first output lines connected to one end of the plurality of conductive lines; A second shift register having a plurality of second output lines connected to the other ends of the conductive lines; A signal amplifier for amplifying and outputting a signal supplied from the outside; At least one first repair line connected to an input terminal of the signal amplifier and arranged to intersect the first output lines; At least one second repair line connected to the output terminal of the signal amplifier and arranged to intersect the first output lines; At least one third repair line connected to the input terminal of the signal amplifier and arranged to intersect the second output lines; And, And at least one fourth repair line connected to an output terminal of the signal amplifier and arranged to intersect the second output lines. The method of claim 1, And the first shift register includes a plurality of stages for outputting a scan pulse through each of the first output lines. The method of claim 2, and one end of the n th output line is connected to the n th stage and the other end thereof is connected to the n th conductive line. The method of claim 2, and a third output line for supplying scan pulses from the n-1 (n is a natural number greater than 2) stage to the nth stage. The method of claim 4, wherein And the third output line connects the first output line connected to the n-1th stage and the nth stage. The method of claim 4, wherein and a fourth output line for supplying scan pulses from the n + 1th stage to the nth stage. The method of claim 6, And the fourth output line connects an n + 1th stage and a first output line connected to the nth stage. The method of claim 1, And the second shift register includes a plurality of stages for outputting a scan pulse through each of the second output lines. The method of claim 8, and one end of the n th output line is connected to the n th stage and the other end thereof is connected to the n th conductive line. The method of claim 8, and a third output line for supplying scan pulses from the n-1 (n is a natural number greater than 2) stage to the nth stage. 11. The method of claim 10, And the third output line connects the first output line connected to the n-1th stage and the nth stage. 11. The method of claim 10, and a fourth output line for supplying scan pulses from the n + 1th stage to the nth stage. 13. The method of claim 12, And the fourth output line connects an n + 1th stage and a first output line connected to the nth stage. The method of claim 1, One end of the first and third repair lines are connected to each other and commonly connected to an input terminal of the signal amplifier. The method of claim 8, And a signal attenuator connected between one end of the first and third repair lines and an input terminal of the signal amplification part. The method of claim 1, One end of the second and fourth repair lines are connected to each other and commonly connected to an output terminal of the signal amplifier. The method of claim 1, A first intersection point between any first output line and the second repair line is connected; A second intersection point between any second output line and the third repair line is connected; A third intersection point between the second arbitrary output line and the fourth repair line is connected; A portion of the second output line located between the second intersection point and the third intersection point is disconnected; And, And any stage provided in the first shift register is electrically separated from the first output line. The method of claim 17, And the arbitrary first output line and the optional second output line are connected to the same conductive line. The method of claim 1, A first intersection point between any first output line and the first repair line is connected; A second intersection point between the arbitrary first output line and the second repair line is connected; A third intersection point between any second output line and the fourth repair line is connected; And, And a part of the first output line located between the first intersection point and the second intersection point is disconnected. The method of claim 19, And the arbitrary first output line and the second optional second output line are connected to the same conductive line. Amplifying a first shift register having a plurality of first output lines connected to one end of the plurality of conductive lines, a second shift register having a plurality of second output lines connected to the other ends of the conductive lines, and a signal supplied from the outside And a signal amplifier for outputting the signal amplifier, at least one first repair line arranged to intersect the first output lines and connected to an input terminal of the signal amplifier, and an output terminal of the signal amplifier. At least one second repair line arranged to intersect one output line, at least one third repair line connected to an input terminal of the signal amplification unit and arranged to intersect the second output lines, and the signal At least one fourth repair connected to the output terminal of the amplifier and arranged to intersect the second output lines. In the repair process of the gate driving circuit comprising a phosphorus, Connecting a first intersection point between any first output line and the second repair line; Connecting a second intersection point between any second output line and the third repair line: Connecting a third intersection point between the second arbitrary output line and the fourth repair line; Disconnecting a portion of the second output line located between the second intersection point and the third intersection point; And, And electrically separating between an arbitrary stage provided in the first shift register and the first output line. The method of claim 21, And the arbitrary first output line and the second optional second output line are connected to the same conductive line. Amplifying a first shift register having a plurality of first output lines connected to one end of the plurality of conductive lines, a second shift register having a plurality of second output lines connected to the other ends of the conductive lines, and a signal supplied from the outside And a signal amplifier for outputting the signal amplifier, at least one first repair line arranged to intersect the first output lines and connected to an input terminal of the signal amplifier, and an output terminal of the signal amplifier. At least one second repair line arranged to intersect one output line, at least one third repair line connected to an input terminal of the signal amplification unit and arranged to intersect the second output lines, and the signal At least one fourth repair connected to the output terminal of the amplifier and arranged to intersect the second output lines In a repair method of a gate driving circuit including a line, Connecting a first intersection point between any first output line and the first repair line; Connecting a second intersection point between the arbitrary first output line and the second repair line; Connecting a third intersection point between any second output line and the fourth repair line; And, Disconnecting a portion of the first output line located between the first intersection point and the second intersection point; And, And electrically separating between an arbitrary stage provided in the second shift register and the second output line. 24. The method of claim 23, And the arbitrary first output line and the second optional second output line are connected to the same conductive line.

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