KR101666583B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of solving the problem of a shift register incorporated in a liquid crystal panel by using external gate drive integrated circuits and a liquid crystal panel for displaying an image, A plurality of gate drive integrated circuits connected to one end of the gate lines of the liquid crystal panel and a shift register which is connected to the other end of the gate lines of the liquid crystal panel, .

A liquid crystal display device, a gate drive integrated circuit, a shift register

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display capable of solving the problem of a shift register built in a liquid crystal panel by using external gate drive integrated circuits.

A liquid crystal display includes a plurality of gate lines connected to pixels. These gate lines are driven by a gate drive integrated circuit mounted outside the liquid crystal panel. Recently, a method of incorporating a shift register in a liquid crystal panel to reduce the number of gate drive integrated circuits has been developed. However, such a built-in shift register is vulnerable to defects such as static electricity and disconnection / short-circuit.

SUMMARY OF THE INVENTION The present invention has been conceived in order to solve the above-mentioned problems, and it is an object of the present invention to provide a liquid crystal display device in which gate drive integrated circuits of an external type are provided on one side of a liquid crystal panel and a shift register is built on the other side of the liquid crystal panel, And it is an object of the present invention to provide a liquid crystal display device capable of driving gate lines using drive integrated circuits.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal panel for displaying an image; a liquid crystal panel connected to one side of the liquid crystal panel through a gate tape carrier package, And a shift register which is embedded in the other side of the liquid crystal panel and connected to the other end of the gate lines of the liquid crystal panel.

The shift register includes a plurality of stages connected to the other end of each gate line, each stage being enabled in response to a scan pulse from the preceding stage and being disabled in response to a scan pulse from the succeeding stage .

A timing controller for generating various control signals necessary for driving the gate drive integrated circuits, the data drive ICs, and the shift registers; a source printed circuit board mounted with the timing controller; Wherein each data drive integrated circuit is mounted on a data tape carrier package, the data tape carrier package connecting the liquid crystal panel and the source printed circuit board to each other .

The timing controller generates a start pulse and supplies it to any one of the gate drive integrated circuits or any one of the stages through one of the data tape carrier packages. The timing controller outputs the start pulse Is supplied to one of the gate drive ICs and the one of the stages.

Wherein the timing controller is responsive to a select signal of a high logic value to a gate drive integrated circuit mounted on the most upstream positioned gate tape carrier package through a data tape carrier package located at the leftmost position and a gate tape carrier package located at the uppermost position, Wherein the timing controller provides the start pulse to a stage located at the uppermost position via a data tape carrier package located at the rightmost position in response to a select signal of a low logic value.

When the timing controller is supplied with a selection signal of a high logic value, the shift register and the gate lines are separated from each other, and when the timing controller is supplied with a selection signal of a low logic value, Are separated from each other.

A first selector connected between the output terminals of the gate drive integrated circuits and one ends of the gate lines, and a second selector connected between the output terminals of the shift register and the other ends of the gate lines Wherein the first selector connects the output terminals of the gate drive integrated circuits and one ends of the gate lines to each other in response to the selection signal of the high logic value, Wherein the second selection unit separates the output terminals of the gate drive integrated circuits and one end of the gate lines from each other in response to the select signal of the logic low value, In response to the select signal of the high logic value The output terminals of the shift register and the other ends of the gate lines are separated from each other.

The liquid crystal display device according to the present invention has the following effects.

In the present invention, when a shift register is defective, gate lines can be driven through gate drive integrated circuits instead of a shift register.

1 is a view illustrating a liquid crystal display device according to a first embodiment of the present invention.

1, the liquid crystal display according to the first embodiment of the present invention includes a liquid crystal panel (PN) for displaying an image, and a liquid crystal panel (PN) via a gate tape carrier package (G-TCP) A plurality of gate drive ICs GD-ICs connected to one side of the liquid crystal panel PN and connected to one end of the gate lines GL of the liquid crystal panel PN, And a shift register SR connected to the other end of the gate lines GL of the liquid crystal panel PN.

The liquid crystal panel PN includes a display portion DP on which a plurality of pixels are formed and a non-display portion formed around the display portion DP.

The liquid crystal display according to the first embodiment of the present invention generates various control signals required for driving the gate drive ICs (GD-ICs), the data drive ICs (DD-ICs), and the shift register SR A source PCB (S-PCB) on which the timing controller (TC) is mounted, and a plurality of data lines for supplying pixel voltages to data lines (DL) of the liquid crystal panel (PN) Drive integrated circuits (DD-ICs).

Each data drive IC (DD-IC) is mounted on a data tape carrier package (D-TCP), and the data tape carrier package (D-TCP) S-PCB) to each other.

The timing controller TC generates a data control signal and a gate control signal using a horizontal synchronizing signal, a vertical synchronizing signal, and a clock signal input from the system, and outputs the data control signal and the gate control signal to the data drive ICs (DD-ICs) GD-ICs). The data control signal includes a dot clock, a source shift clock, a source enable signal, a polarity reversal signal, and the like.

The gate control signal is a signal including a gate start pulse (start pulse), a gate shift clock, a gate output enable, and the like, and the gate control signal is input to the gate drive ICs (GD-ICs).

The data drive ICs (DD-ICs) sample the image data according to the data control signal from the timing controller TC, and then store the sampled image data in the horizontal periods (1H, 2H, ...) And supplies analog pixel voltages corresponding to the latched image data to the data lines DL. That is, the data drive ICs (DD-ICs) convert the image data from the timing controller TC into analog pixel voltages using the gamma voltage input from the power generator, and supply them to the data lines DL.

The gate drive ICs GD-ICs sequentially supply scan pulses to one end of the gate lines GL in response to a gate control signal from the timing controller TC.

The shift register SR sequentially supplies scan pulses to the other end of the gate lines GL in response to a gate control signal from the timing controller TC.

2 is a detailed configuration diagram of the shift register SR of FIG.

The shift register SR includes a plurality of stages ST1 to STn and a dummy stage STn + 1 connected to the other end of each gate line GL, as shown in Fig. Each stage ST1 to STn is enabled in response to a scan pulse from the front stage and is disabled in response to a scan pulse from the rear stage. The enabled stage supplies a clock pulse from the outside to the corresponding gate line GL as a scan pulse.

The scan pulse output from the dummy stage STn + 1 is not supplied to the gate line GL but is supplied to the last stage STn connected to the last gate line GL. That is, this dummy stage STn + 1 is a stage for disabling the last stage STn. On the other hand, the first stage ST1 located at the top of the stages is enabled by the start pulse Vst from the timing controller TC. Similarly, the gate drive integrated circuit (GD-IC) located at the uppermost one of the plurality of gate drive integrated circuits (GD-IC) is enabled by the start pulse Vst from the timing controller TC.

Each of the stages ST1 to STn and the dummy stage STn + 1 includes a plurality of switching elements, and the semiconductor layers of the switching elements are fabricated using hydrogenated silicon oxide (amorphous-silicon).

The timing controller TC generates a start pulse Vst and supplies it to either one of the gate drive ICs GD-IC or any one of the stages via one of the data tape carrier packages D-TCP . At this time, the timing controller TC supplies the start pulse Vst to one of the gate drive IC (GD-IC) and the one of the stages according to a selection signal from the outside. This start pulse Vst is a start signal for operating the gate drive ICs (GD-ICs) and the shift register SR, and the start pulse Vst is applied to the gate drive IC (GD-IC) or a shift register (SR).

For example, the timing controller TC responds to a select signal of a high logic value to generate a first data tape carrier package (D-TCP) located at the leftmost position and a first gate tape carrier package (G-TCP) IC to the first gate drive integrated circuit (GD-IC) mounted on the first gate tape carrier package (G-TCP). On the other hand, the timing controller TC provides the start pulse Vst to the first stage located at the uppermost position via the last data tape carrier package (D-TCP) located at the rightmost position in response to the select signal of the low logic value do.

At this time, when the timing controller TC receives a selection signal having a high logic value, the shift register SR and the gate lines GL are separated from each other. On the other hand, when the timing controller TC selects a logic low value The gate drive integrated circuits (GD-ICs) and the gate lines GL are separated from each other.

3 is a view showing that the shift register SR and the gate lines GL are separated from each other.

As shown in FIG. 3, the shift register SR and the gate lines GL may be separated from each other by applying a laser to the other ends of the gate lines GL connected to the shift register SR.

4 is a view showing that the gate drive ICs (GD-ICs) and the gate lines GL are separated from each other.

4, a ranger is applied to one ends of the gate lines GL connected to the gate drive ICs GD-ICs and the gate drive ICs GD-ICs, GL can be separated from each other.

On the other hand, the gate drive ICs (GD-ICs) and the shift register SR can be selectively connected to the gate lines GL by using the following non-laser selection unit.

5 is a view illustrating a liquid crystal display device according to a second embodiment of the present invention.

As shown in FIG. 5, the liquid crystal display according to the second embodiment of the present invention further includes a first selector SEL1 and a second selector SEL2 as compared with the first embodiment.

The first selector SEL1 is connected between the output terminals of the gate drive ICs (GD-ICs) and one ends of the gate lines GL. The first selector SEL1 connects the output terminals of the gate drive ICs GD and the one ends of the gate lines GL in response to the select signal having the high logic value, And separates the output terminals of the gate drive integrated circuits (GD-ICs) and one ends of the gate lines (GL) from each other in response to a select signal of a logic low value. To this end, the first selector SEL1 includes switching elements connected between each output terminal of each gate drive integrated circuit (GD-IC) and one end of each gate line GL. Each switching element is turned on or off according to the logic of the selection signal to connect or disconnect the output terminal of each gate drive integrated circuit (GD-IC) and the corresponding gate line (GL).

The second selection unit SEL2 is connected between the output terminals of the shift register SR and the other ends of the gate lines GL. The second selector SEL2 couples the output terminals of the shift register SR and the other ends of the gate lines GL in response to the selection signal of the logic low value, And the output terminals of the shift register SR and the other ends of the gate lines GL are separated from each other in response to the selection signal.

In the present invention, both the gate drive ICs (GD-ICs) and the shift registers (SR) supply a start pulse (Vst) to both the gate drive ICs It can be operated at the same time.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1 is a view illustrating a liquid crystal display device according to a first embodiment of the present invention;

Fig. 2 is a detailed configuration diagram of the shift register of Fig.

3 is a view showing that the shift register and the gate lines are separated from each other

4 is a view showing that gate drive integrated circuits and gate lines are separated from each other;

5 is a view illustrating a liquid crystal display device according to a second embodiment of the present invention

Claims (7)

A liquid crystal panel for displaying an image; A plurality of gate drive integrated circuits connected to one side of the liquid crystal panel through a gate tape carrier package and connected to one end of gate lines of the liquid crystal panel; And And a shift register which is embedded in the other side of the liquid crystal panel and connected to the other end of the gate lines of the liquid crystal panel. The method according to claim 1, The shift register including a plurality of stages connected to the other end of each gate line; And, Each stage being enabled in response to a scan pulse from the front stage and being disabled in response to a scan pulse from the rear stage. 3. The method of claim 2, A timing controller for generating various control signals necessary for driving the gate drive integrated circuits, the data drive ICs, and the shift registers; A source printed circuit board on which the timing controller is mounted; Further comprising a plurality of data drive integrated circuits for supplying pixel voltages to the data lines of the liquid crystal panel; Each data drive integrated circuit is mounted on a data tape carrier package; And, And the data tape carrier package connects the liquid crystal panel and the source printed circuit board to each other. The method of claim 3, The timing controller generates a start pulse and supplies it to either one of the gate drive integrated circuits or to one of the stages via any one of the data tape carrier packages; And, Wherein the timing controller supplies the start pulse to one of the gate drive ICs and the one of the stages in accordance with a selection signal from the outside. 5. The method of claim 4, Wherein the timing controller is responsive to a select signal of a high logic value to a gate drive integrated circuit mounted on the most upstream positioned gate tape carrier package through a data tape carrier package located at the leftmost position and a gate tape carrier package located at the uppermost position, Providing a start pulse; Wherein the timing controller provides the start pulse to a stage located at the uppermost one of the stages of the shift register through a data tape carrier package located at the rightmost position in response to a select signal of a low logic value. 6. The method of claim 5, The shift register and the gate lines are separated from each other when the timing controller is supplied with a selection signal having a high logic value; And the gate drive integrated circuits and the gate lines are separated from each other when the timing controller is supplied with a selection signal of a logic low value. The method according to claim 6, A first selector connected between output terminals of the gate drive integrated circuits and one ends of the gate lines; And a second selector connected between the output terminals of the shift register and the other ends of the gate lines; The first selector connects the output terminals of the gate drive integrated circuits and one ends of the gate lines to each other in response to the selection signal of the high logic value, Separating output terminals of the integrated circuits and one ends of the gate lines from each other; Wherein the second selector connects the output terminals of the shift register and the other ends of the gate lines to each other in response to the select signal of the logic low value while the output of the shift register in response to the select signal of the high logic value, And the other ends of the gate lines are separated from each other.

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