JP3160171B2 - Scanning circuit and image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning circuit used for a driving circuit of a matrix type display device and an image display device using the scanning circuit.

[0002]

2. Description of the Related Art FIG. 15 shows an example of a scanning circuit used for a driving circuit of a matrix type display device.

The scanning circuit includes a shift register 15-5.
, And AND circuits 15-6-1, 15-6-2,... The shift register 15-5 shifts the pulse signal input from the start pulse signal line 15-2 in one direction based on the clock signal input from the clock signal line 15-1, as shown in FIG. Output signal lines 15-3-1 and 15 of the shift register 15-5
-3-2 ... are sequentially output.

The odd-numbered output signal lines 15-3-1, 15
-3-3 and 15-3-5 output a signal synchronized with the rising edge of the signal on the clock signal line 15-1, and the even-numbered output signal lines 15-3-2, 15-3-4, and 15--5. 3-
6, a signal synchronized with the falling of the signal on the clock signal line 15-1 is output. Therefore, the pulses of the adjacent output signal lines 15-3-i and 15-3- (i + 1) overlap. Here, i = 1, 2,....

Therefore, adjacent output signal lines 15-3-i,
The AND of the signals on 15-3- (i + 1) is determined by the AND circuit 1
5-6-i, and outputs it to the output signal line 15-4-i. As a result, a scanning signal composed of non-overlapping pulses is obtained.

[0006]

SUMMARY OF THE INVENTION Shift register 15
Specifically, -5 is a circuit in which inverters are connected in series as shown in FIG. For this reason, there is a problem that if a failure occurs in the transistor constituting the shift register 15-5, a circuit subsequent to the failed transistor does not operate normally.

It is assumed that the shift register 15-5 has ten transistors per output stage and one AND circuit 15-6-i has six transistors. It is also assumed that the probability that one transistor is a non-defective product is P (0 ≦ P ≦ 1).

In this case, the output signal of the L-th stage of the scanning circuit,
That is, the output signal of the output signal line 15-4-L is the logical product of the signals of the output signal lines 15-3-L and 15-3- (L + 1). Is
It is necessary for the shift register 15-5 to operate normally up to the (L + 1) th stage. Therefore, the probability of obtaining the output signal of the L-th stage of the scanning circuit is ^{P10 * (L + 1) +6} .

Therefore, as the number of output stages of the shift register 15-5 increases, the probability that the scanning circuit operates normally decreases. In particular, in the case where the display panel and the drive circuit are integrated using a polycrystalline Si thin film, a transistor is likely to be defective due to variations in characteristics and electrostatic breakdown, so that the non-defective rate of the scan circuit is significantly reduced. .

Since an image display device such as a three-plate type projector requires a scanning circuit capable of bidirectional scanning, a shift register 15-5 'capable of bidirectional shifting is provided as shown in FIG. Will be needed. In this case, since 16 transistors are required for one output stage of the shift register 15-5 ', the probability of obtaining the output signal of the L stage of the scanning circuit is P ^{16 * (L + 1) +6} become. Therefore, the probability is even smaller than the probability in a scanning circuit that performs one-way scanning.

Therefore, in the method disclosed in Japanese Patent Publication No. Hei 2-13316, two identical scanning circuits are provided in parallel, and the wiring of the scanning circuit in which the defect occurs is cut off.

However, according to this method, the size of the scanning circuit is doubled, and the number of locations where a problem occurs is also doubled. Further, a step of identifying a circuit in which a defect has occurred and cutting the wiring of the scanning circuit is also required.
As a result, a long time is required for inspection and correction, which causes a new problem that productivity is reduced.

Further, when the display panel and the driving circuit are integrated using a polycrystalline Si thin film, the operation speed of the thin film transistor is slow, so that the display panel cannot be driven sufficiently. ing.

Therefore, in the method disclosed in Japanese Patent Publication No. 5-22917, a display panel can be driven by a thin-film transistor having a low operation speed by providing a plurality of shift registers.

However, according to this method, the circuit area is significantly increased.

Further, the HDTV standard (1840 horizontal scanning lines × 1035 vertical scanning lines) is used.
Image display device that displays images of the television standard)
As shown in FIG. 19, for example, 1024 horizontal scanning lines ×
If you want to display an image of XGA standard (extended graphic array standard) with 768 vertical scanning lines,
It is necessary to scan a portion of the display panel where the upper, lower, left, and right images are not displayed to a position where the next display data is displayed during the retrace period. For this reason, it is necessary to perform scanning at an operating frequency faster by the flyback period. In addition, when displaying an image at a normal operating frequency, as shown in FIG. 20, it is necessary to add a selector capable of selecting a start pulse input location in order to control a first signal input location to be displayed. . As a result, there is a problem that the driving circuit is also large in scale.

Therefore, ISSCC94 (1994 IEEE Int.
National Solid-State Circuits Conference) PA
PAR TA9.1 proposes a scanning circuit with a decoder circuit. However, in this method, since the number of transistors is large, the circuit scale becomes large.

[0018]

According to a first aspect of the present invention, there is provided a scanning circuit comprising 2 m signals composed of m signals and m inverted signals obtained by inverting the m signals. The decoder circuit includes a decoder circuit that outputs a scan pulse based on the plurality of address signals, and the decoder circuit includes first to L-th decode circuits that sequentially output the scan pulse to L output signal lines satisfying a condition of L ≦ 2 ^m And each decoding unit includes a first transistor, and second to (m + 1) th transistors having polarities opposite to the polarity of the first transistor, and the first to (m + 1) th transistors. ), The drain and the source of which are connected in series, the scan pulse is output from the connection point of the first and second transistors, and the level of the address signal is applied to the gate of the first transistor. High level and the reset signal to turn on the first transistor is input when changing from the low level or a low level to a high level from
The above-described address signal is input to the gates of the second to (m + 1) th transistors.

According to a second aspect of the present invention, there is provided a scanning circuit based on 2m address signals including m signals and m inverted signals obtained by inverting the m signals. Including a decoder circuit for outputting a scanning pulse,
The above-described decoder circuit includes first to L-th decoding units that sequentially output a scanning pulse to L output signal lines satisfying a condition of L ≦ 2 ^m . Each decoding unit includes a first transistor, A second to a (m + 2) th transistor having a polarity opposite to the polarity of the first transistor, and a drain of the first to a (m + 2) th transistor;
Sources are connected in series, and the scan pulse is output from a connection point of the first and second transistors;
A reset signal for turning on the first transistor and turning off the second transistor when the level of the address signal changes from high level to low level or from low level to high level is applied to the gates of the first and second transistors. Are input, and the address signals are input to the gates of the third to (m + 2) th transistors.

According to a third aspect of the present invention, there is provided a scanning circuit according to the first or second aspect, wherein the polarity of a transistor to which an inversion signal is input as an address signal is changed to the first. The polarity is changed to the same as that of the first transistor, and a non-inverted signal is input to the gate of the changed transistor instead of the inverted signal as an address signal.

According to a fourth aspect of the present invention, there is provided a scanning circuit according to the first or second aspect, wherein the gate of the first transistor of the first to L-th decoding units is provided. Are characterized in that a scan pulse from a connection point of the first and second transistors of the second to L-th and first decoding units is input as a reset signal, respectively.

According to a fifth aspect of the present invention, there is provided a scanning circuit according to the first or second aspect, wherein a capacitor for holding the level of each output signal line is provided. It is characterized in that it is connected to each output signal line.

According to a sixth aspect of the present invention, there is provided a scanning circuit according to the first, second or fourth aspect of the present invention, wherein the first level is used to hold the level of each output signal line. , A second inverting circuit is provided, the first inverting circuit is inserted in series with the output signal line, and the input and the output of the second inverting circuit are respectively connected to the output and the input of the first inverting circuit. It is characterized by being connected.

According to a seventh aspect of the present invention, there is provided a scanning circuit according to the first, second, fifth, or sixth aspect of the present invention, wherein the fixed period immediately before the level of the address signal changes. An address signal in which the level of all the address signals becomes a high level or a low level is input to a decoder circuit.

According to an eighth aspect of the present invention, there is provided a scanning circuit according to the second aspect, wherein:
The reset signal is input to the decoder circuit for a certain period immediately before the level of the address signal changes.

According to a ninth aspect of the present invention, there is provided a scanning circuit according to the first, second, or fourth aspect, wherein the next reset signal is input to the output signal line. It is characterized by having a capacity that can maintain the non-selection level up to that point.

According to a tenth aspect of the present invention, there is provided an image display device comprising:
In order to solve the above problem, a video signal is sampled in synchronization with a first scanning pulse, the sampled video signal is sent to a data signal line, and a scanning signal line is selected in synchronization with a second scanning pulse. Thus, in a matrix-type image display device that displays an image on a display unit including pixels arranged in a matrix, a first scanning circuit that generates a first scanning pulse and a second scanning circuit that generates a second scanning pulse And a scanning circuit according to claim 1, 2, 4, 5, or 6 is used as the first scanning circuit and the second scanning circuit.

[0028]

According to the configuration of the first aspect, the scanning signal is obtained by decoding the address signal by the first to L-th decoder units of the decoder circuit. In addition, since each decoder section is independent, even if one decoder section is defective, scan pulses from the other decoder sections can be obtained. On the other hand, in a conventional scanning circuit using a shift register, if one output stage of the shift register is defective, a scanning pulse from a subsequent output stage cannot be obtained. Therefore, the scanning circuit of the present invention has a much higher probability of operating normally than the conventional scanning circuit.

Further, when the level of the address signal changes from the high level to the low level or from the low level to the high level, the reset signal turns on the first transistor. Therefore, by setting any of the address signals to a low level, the level of the scan pulse can be reset to the drain voltage of the first transistor. Thus, malfunctions such as glitches due to non-uniformity of electric characteristics of the first to (m + 1) -th transistors and dispersion of delay time in scan pulses can be eliminated. In addition, since the decoder section is of a dynamic type, it is possible to reduce the size and power consumption of the scanning circuit.

Further, in the scanning circuit of the present invention, since each decoder section is independent, the operation speed is higher than that of the shift register. Further, various scanning signals can be easily obtained only by changing the address signal.

According to the configuration of the second aspect, the same operation as that of the first aspect is obtained, and when the level of the address signal changes from the high level to the low level or from the low level to the high level, the reset signal is output. This turns on the first transistor and turns off the second transistor. Thereby, regardless of the level of the address signal,
The level of the output signal line can be reset to the level of the drain of the first transistor.

According to the configuration of claim 3, in addition to the function of claim 1 or 2, the polarity of the transistor to which the inverted signal is input as the address signal is changed to the same polarity as the first transistor, and the changed transistor is changed. Since the non-inverted signal is input to the gate of the gate instead of the inverted signal as the address signal, the inverted signal is not required as the address signal. Thereby, the scanning circuit can be simplified.

According to the configuration of claim 4, in addition to the function of claim 1 or 2, the first transistors of the first to L-th decoding units are connected to the second to L-th decoding units of the first decoding unit. It is sequentially turned on by a scanning pulse from the connection point of the first and second transistors. This eliminates the need for an external reset signal and reduces the number of address signal lines.

According to the configuration of claim 5, in addition to the function of claim 1, 2, or 4, after the level of the output signal line is reset, the level of the output signal line is maintained until the next scan pulse is output. Can be reliably held.

According to the configuration of claim 6, the same operation as in claim 5 is obtained.

According to the configuration of claim 7, claims 1, 2,
In addition to the operation of 5 or 6, in addition to the fact that the address signals in which the levels of all the address signals are at the high level or the low level are input to the decoder circuit for a certain period immediately before the level of the address signals change, all the signals are output during that period. The output signal line goes to the non-selection level. As a result, malfunctions such as glitches due to non-uniformity of transistor characteristics and dispersion of delay time in scan pulses can be eliminated.

According to the configuration of claim 8, in addition to the function of claim 2, the reset signal is input to the decoder circuit for a certain period immediately before the level of the address signal changes.
During that period, all output signal lines are at the non-selection level.
As a result, malfunctions such as glitches due to non-uniformity of transistor characteristics and dispersion of delay time in scan pulses can be eliminated.

According to the ninth aspect, in addition to the function of the first, second or fourth aspect, the output signal line has a capacity capable of maintaining the non-selection level until the next reset signal is input. Therefore, an output signal line that does not output a scanning pulse can be reliably set to a non-selection level.

According to the structure of claim 10, claim 1,
Since any one of 2, 4, 5, or 6 scanning circuits is used, the probability that the image display device operates normally is much higher. Moreover, since various scanning signals can be easily obtained only by changing the address signal, images having different standards can be easily displayed.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1, the scanning circuit of this embodiment is a dynamic decoder circuit 1-4 for decoding address signals from the address signal lines 1-1-1 to 1-1-4.
And an inverter circuit 1-which inverts a signal from the decoder circuit 1-4 and outputs the inverted signal to output signal lines 1-3-1 to 1-3-4.
5-1 to 4-1.

The decoder circuit 1-4 has four decoding units 1-4-1 to 4-4.
4 are the drain and source of one P-type transistor 1-4-A and the two N-type transistors 1-4-B
The structure is such that the drain and source of C are connected in series from the power supply side to the GND (ground) side.

The gates of the P-type transistors 1-4-A of all the decoding units 1-4-1 to 4-4 are connected to the reset signal line 1
-2.

The gate of the N-type transistor 1-4-C of the decoding section 1-4-1 is connected to the address signal line 1-1-1. The gate of the N-type transistor 1-4-B is connected to the address signal line. 1-1-3.

The gate of the N-type transistor 1-4-C of the decoding section 1-4-2 is connected to the address signal line 1-1-2, and the gate of the N-type transistor 1-4-B is connected to the address signal line. 1-1-3.

The gate of the N-type transistor 1-4-C of the decoding section 1-4-3 is connected to the address signal line 1-1-1. The gate of the N-type transistor 1-4-B is connected to the address signal line. 1-1-4.

The gate of the N-type transistor 1-4-C of the decoding section 1-4-4 is connected to the address signal line 1-1-2, and the gate of the N-type transistor 1-4-B is connected to the address signal line. 1-1-4.

The outputs of the decoders 1-4-1 to 1-4 (that is, the connection between the P-type transistor 1-4-A and the N-type transistor 1-4-B) are respectively connected to the inverter circuits 1-5. Connected to inputs 1-4. Outputs of the inverter circuits 1-3-1 to 4 are connected to output signal lines 1-3-1 to 4 respectively.

In the above configuration, the address signal line 1-
An address signal is input to 1-1 to 1-4, and a reset signal is input to a reset signal line 1-2.

As shown in FIG. 2, the reset signal is set so as to be at a low level for a certain period t _res immediately before the level of an arbitrary address signal line 1-1-1-4 changes to a high level. I have.

The address signals during the scanning period, two of the address signal lines 1-1-1～4 but are set to sequentially become high level, the above period t _res All address signal lines 1-1-1-4 are set to be reset to a low level. Address signal line 1-1
2, 1-1-4 are applied to the address signal line 1--1.
1-1 and 1-1-3 are inverted signals. Therefore, four address signal lines 1-1-
Half (two) of 1-4 are independent.

The decoding section 1-4 of the decoder circuit 1-4
-1 and the inverter circuit 1-5-1 output the logical product of the signals of the address signal lines 1-1-1 and 1-1-3 to the output signal line 1-3-1. Decoding section 1-4-2 of decoder circuit 1-4 and inverter circuit 1-5-2
Outputs the logical product of the signals of the address signal lines 1-1-2 and 1-1-3 to the output signal line 1-3-2. The decoding unit 1-4-3 and the inverter circuit 1-5-3 of the decoder circuit 1-4 are connected to the address signal lines 1-1-1 and 1-1-1.
4 and outputs the logical product of the signals to the output signal line 1-3-3.
The decoding section 1-4-4 and the inverter circuit 1-5-4 of the decoder circuit 1-4 are connected to the address signal line 1-1-
The logical product of the signals 2 and 1-1-4 is output to the output signal line 1-3-4.
Output to

As a result, a scanning signal composed of pulses for sequentially setting the output signal lines 1-3-1 to 4 to the high level is obtained.

Further, during a certain period t _res immediately before the level of the address signal lines 1-1-1 to 1-1-4 changes to the high level, all the decoding sections 1-4 of the decoder circuit 1-4 are set.
At the same time as the P-type transistors 1-4-4-A of -1 to 4 are turned on by the reset signal, the N-type transistors 1-4-B and 1-4-C are turned off by the address signal.
Therefore, all the output signal lines 1-3-1 to 4 become low level. As a result, it is possible to eliminate malfunctions such as glitches due to non-uniformity of element characteristics of the scanning circuit and dispersion of delay time in the scanning pulse. Further, since the dynamic decoder circuit 1-4 is employed, the size of the scanning circuit can be reduced and the power consumption can be reduced.

Moreover, the four output stages comprising the decoding section 1-4-i (where i = 1, 2, 3, 4) of the decoder circuit 1-4 and the inverter circuit 1-5-i are independent of each other. Thus, each output stage can be composed of five transistors. Therefore, when the non-defective rate of one transistor is P, the probability that each output stage operates normally is P ⁵
become. Therefore, in this embodiment, the probability that the scanning circuit operates normally becomes extremely high as compared with the conventional scanning circuit using the shift register.

As a specific example of the scanning circuit of this embodiment, Ha
A scanning circuit of an image display device of an ifVGA (semi-video graphics array) specification will be described, and a probability that the scanning circuit normally operates will be estimated.

The scanning circuit of the half VGA specification image display device requires 18 address signal lines and 320 output stages. However, half (9) of the 18 address signal lines are independent.

Each output stage is composed of a decoding section composed of one P-type transistor and nine N-type transistors as many as the number of independent address signal lines, and an inverter circuit. That is, each output stage can be composed of eleven transistors. Therefore, the probability that each output stage operates normally becomes P ^11.

As shown in FIG. 3, the output stage includes three three-input dynamic NAND circuits and one three-input NAND circuit.
It can also be configured with an input NOR circuit.

When the three-input dynamic NAND circuit shown in FIG. 4A is used, the output stage is composed of 18 transistors (12 N-type transistors and 6 P-type transistors). Therefore, the probability that each output stage operates normally becomes P ^18.

According to the dynamic method, the number of transistors is larger than that in the output stage, and the probability of normal operation is lower than that in the scanning circuit. However, since the number of N-type transistors connected in series is reduced to one third, the operating speed can be increased.

When the three-input dynamic NOR circuit shown in FIG. 4B is used, the output stage is composed of 16 transistors (10 N-type transistors and 6 P-type transistors). Therefore, the probability that each output stage operates normally becomes P ^16. Note that a dynamic NAND circuit and a dynamic NOR circuit are:
It is necessary to invert the polarity of the reset signal.

On the other hand, in the conventional scanning circuit using the shift register, the probability that the output of the L-th stage is operable is P ^{10 * (L + 1) +6.} probability of operation is P ^26, the probability of 320 stage to operate correctly P
³²¹⁶ .

Since P ¹¹ ≧ P ¹⁶ ≧ P ¹⁸ ≧ P ²⁶ ≧ P ³²¹⁶ , the probability that the scanning circuit of this embodiment normally operates is much higher than that of the conventional scanning circuit. In addition, the probability that the scanning circuit operates normally does not depend on the number of output stages. For this reason, even if a polycrystalline Si thin film transistor, which is liable to cause variations in electric characteristics and electrostatic breakdown, is used for the scanning circuit,
A high non-defective rate can be secured.

Further, according to the scanning circuit of this embodiment, only by changing the address signal input to the address signal line,
Bidirectional scanning can be performed. Therefore, the probability that each output stage operates normally in bidirectional scanning is equal to the probability that each output stage operates normally in one-way scanning. For this reason, if the scanning circuit of the present embodiment is adopted, a high non-defective product rate can be ensured even in an image display device such as a three-panel projector that requires bidirectional scanning, as in a one-way scanning image display device. it can.

On the other hand, in the conventional bidirectional scanning circuit,
Since the probability that the output of the L-th stage is operable is P ^{16 * (L + 1) +6} , the probability that the first stage operates normally is P ³⁸ ,
The probability that the twentieth stage operates normally is ^P5142 . That is, the probability that each output stage operates normally in bidirectional scanning is even smaller than the probability that each output stage operates normally in one-way scanning.

Therefore, when bidirectional scanning is performed, the probability of the normal operation of the scanning circuit of this embodiment is much higher than that of the conventional scanning circuit.

When the scanning circuit of this embodiment is employed in the data signal driving circuit and the scanning signal driving circuit of the active matrix type image display device shown in FIG.
When the scanning circuit of the present embodiment is adopted in a pair of the same data signal driving circuits arranged on the upper and lower sides of the display unit and a pair of the same scanning signal driving circuits arranged on the left and right sides of the display unit, Even if a failure occurs in one of the drive circuits, a normal image can be displayed on the other drive circuit. Also, even if a failure occurs in one output stage of the other drive circuit,
There is no effect on lines other than the line corresponding to the output stage.

On the other hand, when a conventional scanning circuit using a shift register is employed in the above-mentioned driving circuit, if a problem occurs in an output stage of the remaining driving circuit, all of the lines following the line corresponding to the output stage are deleted. The line cannot be displayed.

Further, according to the scanning circuit of the present embodiment, as described above, the scanning signals of the different standard images (for example, the HDTV standard image and the XGA standard image) are output only by changing the address signal. can do. Therefore,
By simply changing the address signal, it is possible to display images of different standards. As a result, the selector required to display a plurality of images of different standards in the conventional scanning circuit becomes unnecessary in the scanning circuit of the present embodiment.

Further, since each output stage is independent in the scanning circuit of this embodiment, it is not affected by the delay of the signal from the previous output stage or the load of the subsequent output stage. Therefore, high-speed operation is possible as compared with a conventional scanning circuit using a shift register affected by these factors.
Therefore, it is possible to sufficiently cope with the case where the display panel and the drive circuit are integrated using the polycrystalline Si thin film transistor. As a result, the scanning circuit can be simplified as compared with a conventional scanning circuit that requires the use of a plurality of shift registers, and the area occupied by the scanning circuit can be reduced. As a result, it is possible to provide a smaller and less expensive image display device than before.

In the above embodiment, in order to obtain a scanning signal composed of pulses for sequentially setting the L output signal lines to the high level, m independent address signals satisfying the condition of L ≦ 2 ^m must be input. I just need. Here, the independent address signal is an address signal obtained by not counting an address signal and an inverted address signal in an overlapping manner. The scanning circuit is composed of one decoder circuit and L inverters, and the decoder circuit is composed of L decoding units. Each decoding unit of the decoder circuit has one
And transistors connected in series with m transistors of opposite polarities.

The second embodiment of the present invention will be described below with reference to FIGS. 6 and 7. In addition,
For convenience of explanation, members having the same functions as those shown in the drawings of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 6, the scanning circuit of the present embodiment comprises decoding sections 1-4-1 to 1-4-4 of a decoder circuit 1-4.
Is different from the above embodiment.

Each of the decoding units 1-4-1 to 4-4 has one P
Drain and source of the type transistor 2-4-A and 3
Drains of two N-type transistors 2-4-A ′ to C,
The source and the source are connected in series from the power supply side to the GND side.

The gates of the P-type transistors 2-4-A and the gates of the N-type transistors 2-4-A 'of all the decoding units 2-4-1 to 4--4 are connected to the reset signal line 1-2.

The outputs of the decoding units 2-4-1 to 2-4-1 (that is, the connection between the P-type transistor 2-4-A and the N-type transistor 2-4-A ') are respectively connected to the inverter circuits 1-5. Connected to inputs -1 to -4. Outputs of the inverter circuits 1-3-1 to 4 are connected to output signal lines 1-3-1 to 4 respectively.

Other connections are the same as in the above embodiment.

In the above configuration, address signal line 1-
An address signal is input to 1-1 to 1-4, and a reset signal is input to a reset signal line 1-2. This allows
A scanning signal composed of a pulse for sequentially setting the output signal lines 1-3-1 to 4 to high level is obtained.

In the scanning circuit of this embodiment, as shown in FIG. 7, there is no need to reset the address signal in synchronization with the reset signal. Therefore, a scanning signal can be obtained only by inputting an address signal having a simple waveform.

[0081] By applying the scanning circuit of the present embodiment the scanning circuit of the image display apparatus HalfVGA specifications, the probability that the scanning circuit to operate normally becomes P ^20. Therefore, as in the above embodiment, the probability that the scanning circuit operates normally is much higher than that of the conventional scanning circuit. In addition, the probability that the scanning circuit operates normally does not depend on the number of output stages. For this reason,
Even when a polycrystalline Si thin film transistor that easily causes variations in electrical characteristics and electrostatic breakdown is used for a scanning circuit, a high yield rate can be ensured.

The third embodiment of the present invention will be described below with reference to FIGS. In addition,
For convenience of explanation, members having the same functions as those shown in the drawings of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 8, the scanning circuit of this embodiment is different from the scanning circuit of the above-mentioned embodiment in that the address signal lines 1-1 to 1-1 are provided.
2, 1-1-4 are omitted, and address signal lines 1-1-2,
The configuration is such that the gates of the transistors connected to 1-1-4 are connected to address signal lines 1-1-1 and 1-1-3, and the transistors are changed from N-type to P-type. .

In the above configuration, address signal line 1-
An address signal is input to 1-1 and 1-1-3, and a reset signal is input to a reset signal line 1-2. As a result, a scanning signal composed of pulses for sequentially setting the output signal lines 1-3-1 to 4 to the high level is obtained.

In the scanning circuit of this embodiment, as shown in FIG. 9, there is no need to reset the address signal in synchronization with the reset signal, as in the above embodiment. Therefore, a scanning signal can be obtained only by inputting an address signal having a simple waveform. In addition, the address signal line 1 of the above embodiment is used.
-1-1 to 4-5 are half of the address signal lines 1-1-1 and 1-1-1.
Since the number of scanning circuits can be reduced to -1-3, the size of the scanning circuit can be reduced.

In the scanning circuit of the present embodiment, a P-type transistor is used for the input portion of the address signal.
When the transistor is turned on, the potential between the gate and the source becomes almost zero. As a result, the fall time becomes longer. In order to avoid this, the potential input to the gate may be set lower than the source potential by at least the threshold value of the P-type transistor. As a result, the fall time can be shortened, and a high-speed operation can be performed.

Since the number of transistors required for the scanning circuit of this embodiment is the same as that of the above embodiment, the probability that the scanning circuit operates normally is the same as that of the above embodiment.

The fourth embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 10, the scanning circuit of this embodiment is different from the scanning circuit of the first embodiment in that the reset signal line 1
-2 is omitted, and the gates of the P-type transistors 1-4-A of the decoding units 1-4-1, 2, 3, and 4 connected to the reset signal line 1-2 are connected to the decoding unit 1-4-2. 3,
4, 1 (that is, P-type transistor 1-4)
(The connection portion between A and N-type transistor 1-4-B).

In the above configuration, the address signal line 1-
Address signals are input to 1-1 to 1-4. When the output signal line 1-3-i goes high, the decoding section 1-4
The (i-1) P-type transistor 1-4-A is turned on. Therefore, the output signal line 1-3- (i-1) becomes low level. Thereby, similarly to the first embodiment,
As shown in FIG. 11, a scanning signal composed of pulses for sequentially setting the output signal lines 1-3-1 to 4 to high level is obtained.

In the scanning circuit of this embodiment, since the reset signal line 1-2 of the first embodiment can be omitted, the circuit can be simplified and the circuit scale can be reduced. In addition,
The scanning circuit of this embodiment is dedicated to one-way scanning.

Since the number of transistors required for the scanning circuit of this embodiment is the same as that of the first embodiment, the probability that the scanning circuit operates normally is the same as that of the first embodiment.

The fifth embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 12, the scanning circuit of this embodiment is different from the scanning circuit of the above-described embodiment in that the address signal lines 1-1 to 1-1 are provided.
2, 1-1-4 are omitted, and address signal lines 1-1-2,
The configuration is such that the gates of the transistors connected to 1-1-4 are connected to address signal lines 1-1-1 and 1-1-3, and the transistors are changed from N-type to P-type. .

In the above configuration, address signal line 1-
Address signals are input to 1-1 and 1-1-3. Thereby, similarly to the embodiment, as shown in FIG.
A scanning signal composed of a pulse for sequentially setting the output signal lines 1-3-1 to 4 to high level is obtained.

In the scanning circuit of this embodiment, since the address signal lines 1-1-2 and 1-1-4 of the above embodiment can be omitted, the scanning circuit can be further simplified and the circuit scale can be further reduced. . Note that the scanning circuit of this embodiment is dedicated to one-way scanning.

Since the number of transistors required for the scanning circuit of this embodiment is the same as that of the above embodiment, the probability that the scanning circuit operates normally is the same as that of the above embodiment.

In the scanning circuits of the first to third embodiments, the decoding section 1-4-i of the decoder circuit 1-4 which does not output a low level after the reset signal is in a high impedance state. become. In the scanning circuits of the fourth and fifth embodiments, the decoding unit 1-4-i performs one scanning after receiving the reset signal from the decoding unit 1-4 (i + 1) of the decoding circuit 1-4. After the period elapses, a high impedance state is maintained until the next address signal is input.

When the decoding section 1-4-i enters a high impedance state, the output signal line 1-3-i enters a floating state. For this reason, until the next reset signal or the next address signal is input, the output signal lines 1-3 are output.
In some cases, the off-state voltage cannot be maintained due to the wiring capacity and load capacity of -i. In this case, as shown in FIG. 14A, a capacitor 11-1 is connected between the output signal line 1-3-i and a portion where the voltage is constant for at least one horizontal scanning period such as GND. Alternatively, as shown in FIG. 7B, the latch circuit 12- is connected in series to the output signal line 1-3-i.
Providing 1 is effective in maintaining the off-state voltage.

[0100]

As described above, the scanning circuit according to the first aspect of the present invention scans based on 2m address signals composed of m signals and m inverted signals obtained by inverting the m signals. A decoder circuit for outputting a pulse; the decoder circuit includes first to L-th decoding units for sequentially outputting scan pulses to L output signal lines satisfying a condition of L ≦ 2 ^m ; The part comprises: a first transistor;
A second transistor having a polarity opposite to the polarity of the first transistor; and a drain and a source of the first to (m + 1) th transistors are connected in series. And the scanning pulse is output from the connection point of the second transistor and the first transistor when the level of the address signal changes from high level to low level or from low level to high level at the gate of the first transistor. Is input, and the above-described address signal is input to the gates of the second to (m + 1) th transistors.

According to this, since the probability that the scanning circuit operates normally is high, the manufacturing yield of the scanning circuit is increased.
In addition, there is an effect that the size of the scanning circuit can be reduced and the power consumption can be reduced. Further, since various scanning signals can be easily obtained only by changing the address signal, if the scanning circuit of the present invention is applied to an image display device, images having different standards can be easily displayed. It also has an effect.

As described above, the scanning circuit according to the second aspect of the present invention generates a scanning pulse based on 2m address signals composed of m signals and m inverted signals obtained by inverting the m signals. The decoder circuit includes first to L-th decoding units that sequentially output scanning pulses to L output signal lines satisfying a condition of L ≦ 2 ^m , and each decoding unit includes: , The first transistor and the second to (m) having polarities opposite to the polarities of the first transistor.
+2) transistors, and the first to (m)
+2) The drain and source of the transistor are connected in series, the above-mentioned scanning pulse is output from the connection point of the first and second transistors, and the level of the address signal is applied to the gates of the first and second transistors. Turns on the first transistor when the signal changes from high level to low level or from low level to high level,
, A reset signal for turning off the third transistor is input, and the above-mentioned address signal is input to the gates of the third to (m + 2) th transistors.

According to this, the same effect as that of the first aspect is obtained, and the level of the output signal line can be reset to the level of the drain of the first transistor irrespective of the level of the address signal. Therefore, there is an effect that malfunction of the scanning circuit can be easily prevented.

As described above, the scanning circuit according to the third aspect of the present invention is the scanning circuit according to the first or second aspect, wherein the polarity of the transistor to which the inverted signal is input as the address signal is set to the first transistor. In this configuration, the polarity is changed to the same, and a non-inverted signal is input to the gate of the changed transistor instead of the inverted signal as an address signal.

According to this, in addition to the effect of claim 1 or 2, an inverted signal is not required as an address signal. This has the effect of simplifying the scanning circuit.

As described above, the scanning circuit according to the invention of claim 4 is the scanning circuit of claim 1 or 2, wherein
A scan pulse from a connection point of the first to second transistors of the second to L-th decoding units is input as a reset signal to gates of the first transistors of the L-th decoding unit, respectively. Configuration.

According to this, in addition to the effects of the first or second aspect, the first transistors of the first to L-th decoding units are connected to the second to L-th decoding units and the first and second of the first decoding unit. Are sequentially turned on by the scanning pulse from the connection point of the transistors. This has the effect of eliminating the need for an external reset signal.

The scanning circuit according to a fifth aspect of the present invention is the scanning circuit according to the first, second or fourth aspect, wherein a capacitor for holding the level of each output signal line is provided for each output signal line. It is the structure connected to.

According to this, in addition to the effects of the first, second or fourth aspect, after the level of the output signal line is reset, the level of the output signal line is securely held until the next scanning pulse is output. It has the effect that it can be done.

As described above, the scanning circuit according to the invention of claim 6 is the scanning circuit of claim 1, 2 or 4, wherein the first and second scanning circuits are used to hold the level of each output signal line. An inverting circuit is provided, the first inverting circuit is inserted in series with the output signal line, and the input and output of the second inverting circuit are connected to the output and input of the first inverting circuit, respectively. Configuration.

According to this, the same effect as that of the fifth aspect can be obtained.

The scanning circuit according to the seventh aspect of the present invention is the scanning circuit according to the first, second, fifth or sixth aspect of the present invention, wherein
The configuration is such that address signals in which the level of all address signals becomes high level or low level are input to the decoder circuit.

According to this, claims 1, 2, 5, or 6
In addition to the effect of the above, all output signal lines are at the non-selection level for a certain period immediately before the level of the address signal changes, so that malfunctions such as glitches due to non-uniformity of transistor characteristics and delay time in scan pulses are caused. There is an effect that dispersion can be eliminated.

As described above, the scanning circuit according to the invention of claim 8 is the scanning circuit of claim 2, wherein the reset signal is input to the decoder circuit for a certain period immediately before the level of the address signal changes. Configuration.

According to this, in addition to the effect of the second aspect, all the output signal lines are at the non-selection level for a certain period immediately before the level of the address signal changes. This has the effect of eliminating malfunctions such as glitches due to non-uniformity of transistor characteristics and dispersion of delay time in scan pulses.

According to a ninth aspect of the present invention, there is provided the scanning circuit according to the first, second, or fourth aspect, wherein the output signal line is not selected until the next reset signal is input. This is a configuration having a capacity that can maintain the level.

According to this, in addition to the effects of the first, second, or fourth aspect, there is an effect that the level of the output signal line that does not output the scanning pulse can be reliably set to the non-selection level.

An image display device according to a tenth aspect of the present invention
As described above, the first scanning circuit that generates the first scanning pulse and the second scanning circuit that generates the second scanning pulse are provided, and the first scanning circuit and the second scanning circuit are provided as claims 1 and 2. The configuration is provided with the scanning circuit described in 2, 4, 5, or 6.

According to this, since any of the scanning circuits of claims 1, 2, 4, 5, and 6 is used, the probability that the image display device operates normally is much higher. In addition, since various scanning signals can be easily obtained only by changing the address signal, it is possible to easily display images having different standards.

[Brief description of the drawings]

FIG. 1, showing a first embodiment of the present invention, is a circuit diagram illustrating a configuration of a scanning circuit.

FIG. 2 is a waveform chart showing an operation of the scanning circuit of FIG.

FIG. 3 is a circuit diagram showing a specific example of an output stage of the scanning circuit of FIG. 1;

FIG. 4A is a circuit diagram showing an internal configuration of a three-input dynamic NAND circuit in FIG. 3;
FIG. 3B is a circuit diagram showing the internal configuration of the three-input dynamic NOR circuit shown in FIG.

FIG. 5 is a block diagram illustrating a schematic configuration of an active matrix type image display device.

FIG. 6 illustrates a second embodiment of the present invention, and is a circuit diagram illustrating a configuration of a scanning circuit.

FIG. 7 is a waveform chart showing an operation of the scanning circuit of FIG. 6;

FIG. 8 illustrates a third embodiment of the present invention, and is a circuit diagram illustrating a configuration of a scanning circuit.

FIG. 9 is a waveform chart showing an operation of the scanning circuit of FIG. 8;

FIG. 10 illustrates a fourth embodiment of the present invention, and is a circuit diagram illustrating a configuration of a scanning circuit.

FIG. 11 is a waveform chart showing an operation of the scanning circuit of FIG. 10;

FIG. 12 illustrates a fifth embodiment of the present invention, and is a circuit diagram illustrating a configuration of a scanning circuit.

FIG. 13 is a waveform chart showing an operation of the scanning circuit of FIG.

14 shows an example of a circuit for holding the voltage of the output signal line of the scanning circuit of FIGS. 1, 6, 8, 10, and 12, and FIG. 14A is a circuit diagram using a capacitor. And (b) is a circuit diagram using a latch circuit.

FIG. 15 is a circuit diagram showing a configuration of a conventional scanning circuit.

FIG. 16 is a waveform chart showing an operation of the scanning circuit of FIG.

FIG. 17 is a circuit diagram showing a configuration of a shift register in the scanning circuit of FIG.

FIG. 18 is a circuit diagram illustrating a configuration of a shift register capable of bidirectional shift.

FIG. 19 is an explanatory diagram showing a state in which an XGA standard image is displayed on a HDTV standard image display device.

FIG. 20 is a block diagram showing an image display device capable of displaying an HDTV standard image and an XGA standard image.

[Explanation of symbols]

 1-1-i Address signal line 1-2 Reset signal line 1-3-i Output signal line 1-4 Decoder circuit 1-4-A P-type transistor 1-4-B N-type transistor 1-4-C N-type Transistor 1-4-i Decoding unit 1-5-i Inverter circuit 2-4-A P-type transistor 2-4-A'N-type transistor 2-4-B N-type transistor 2-4-C N-type transistor 11- 1 Capacitor 12-1 Latch circuit

Continuation of the front page (56) References JP-A-2-239226 (JP, A) JP-A-8-101669 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1 / 133 G09G 3/36

Claims (10)

(57) [Claims] 1. A decoder circuit for outputting a scanning pulse based on 2m address signals composed of m signals and m inverted signals obtained by inverting m signals, wherein the decoder circuit has L ≦ It comprises first to L-th decoding units for sequentially outputting scan pulses to L output signal lines satisfying the condition of 2 ^m , and each decoding unit includes a first transistor and a polarity of the first transistor. Is the second of the opposite polarity
And an (m + 1) th transistor.
The drain and source of the (m + 1) -th transistor are connected in series, the above-described scanning pulse is output from the connection point of the first and second transistors, and the gate of the first transistor has the address signal level. A reset signal for turning on the first transistor when the level changes from the high level to the low level or from the low level to the high level is input, and the above-described address signal is input to the gates of the second to (m + 1) th transistors. A scanning circuit, which is inputted. 2. A decoder circuit for outputting a scanning pulse based on 2m address signals composed of m signals and m inverted signals obtained by inverting the m signals, wherein the decoder circuit has L ≦ It comprises first to L-th decoding units for sequentially outputting scan pulses to L output signal lines satisfying the condition of 2 ^m , and each decoding unit includes a first transistor and a polarity of the first transistor. Is the second of the opposite polarity
And an (m + 2) -th transistor.
The drain and the source of the (m + 2) th transistor are connected in series, and the above-described scanning pulse is output from the connection point of the first and second transistors, and the first and second transistors are output.
When the level of the address signal changes from a high level to a low level or from a low level to a high level, a reset signal for turning on the first transistor and turning off the second transistor is input to the gates of the transistors. A scanning circuit, wherein the address signal is input to gates of third to (m + 2) th transistors. 3. The polarity of a transistor to which an inverted signal is input as an address signal is changed to the same polarity as the first transistor, and a non-inverted signal is input to the gate of the changed transistor instead of the inverted signal as an address signal. 3. The scanning circuit according to claim 1, wherein: 4. The scanning of the gates of the first transistors of the first to Lth decoding units from the connection point of the first and second transistors of the second to Lth and first decoding units, respectively. 3. The scanning circuit according to claim 1, wherein a pulse is input as a reset signal. 5. The scanning circuit according to claim 1, wherein a capacitor for holding the level of each output signal line is connected to each output signal line. 6. A first and a second inverting circuit are provided for holding the level of each output signal line, and the first inverting circuit is inserted in series with the output signal line, and a second inverting circuit is provided. The input and output of the inverting circuit are connected to the output and input of the first inverting circuit, respectively.
A scanning circuit according to claim 1. 7. The decoder circuit according to claim 1, wherein an address signal in which all of the address signals have a high level or a low level is input to a decoder circuit for a certain period immediately before the level of the address signal changes. , 5 or 6
A scanning circuit according to claim 1. 8. The scanning circuit according to claim 2, wherein a reset signal is input to the decoder circuit for a certain period immediately before the level of the address signal changes. 9. The scanning circuit according to claim 1, wherein the output signal line has a capacity capable of maintaining a non-selection level until a next reset signal is input. 10. A matrix signal is sampled by synchronizing with a first scanning pulse, sending the sampled video signal to a data signal line, and selecting a scanning signal line in synchronism with a second scanning pulse. In a matrix type image display device for displaying an image on a display unit including pixels arranged in a matrix, a first scanning circuit for generating a first scanning pulse and a second scanning circuit for generating a second scanning pulse are provided. Wherein the first and second scanning circuits are used as the first and second scanning circuits.
An image display device, wherein the scanning circuit according to 5 or 6 is used.