JP5786294B2 - Integrated circuit device and electronic apparatus - Google Patents

Description

  The present invention relates to an integrated circuit device, an electronic device, and the like.

  Conventionally, an integrated circuit device for driving an electro-optical panel such as an EPD (Electrophoretic Display) panel is known. For example, as a prior art of an EPD panel, there is a technique disclosed in Patent Document 1.

  In driving such an EPD panel (electrophoresis panel), the drive voltage may be changed sequentially. In this case, an integrated circuit device such as a display driver that drives the EPD panel supplies a driving voltage that changes sequentially to the EPD panel.

  However, if a control device such as an MPU provided outside the integrated circuit device executes the selection instruction of the drive voltage that changes sequentially, the processing load of the control device becomes heavy.

  An EPD panel, an ECP (Electrochromics Display) panel, an NCD (Nanochromics Display) panel, and the like can also be referred to as an electronic paper panel. To support multiple electronic paper panels (electro-optical panels in a broad sense) with different driving methods, it is necessary to prepare multiple integrated circuit devices each driving one electronic paper panel, which increases development costs Resulting in.

JP 2009-53639 A

  According to some embodiments of the present invention, it is possible to provide an integrated circuit device, an electronic device, and the like that can reduce development costs.

One aspect of the present invention is a drive voltage output unit that outputs a drive voltage supplied to a segment electrode of an electro-optical panel to an output terminal;
A display data storage unit for storing at least first display data and second display data;
Drive waveform for outputting drive waveform information when the display state at the segment electrode changes from the first display state corresponding to the first display data to the second display state corresponding to the second display data Including an information output unit,
The drive voltage output unit is
A drive signal generation unit that generates a drive signal specified by the first display data and the second display data from the display data storage unit and the drive waveform information from the drive waveform information output unit;
A first output stage for outputting the drive voltage based on the drive signal at a first voltage level;
A second output stage for outputting the drive voltage based on the drive signal at a second voltage level;
A first level shifter that shifts the first voltage level to the second voltage level;
One of the output voltage of the first output stage and the output voltage of the second output stage is output to the output terminal.

  According to one aspect of the present invention, the drive voltage output unit can output the drive voltage at the first voltage level or the second voltage level according to the driving method of the electro-optical panel. Further, since the display data storage unit and the drive waveform information output unit can be made common to the plurality of electro-optical panels, the development cost can be reduced.

  In addition, the first and second display data and the drive waveform information when changing from the first display state corresponding to the first display data to the second display state corresponding to the second display data. A drive voltage (drive signal in a broad sense) is specified, and the electro-optical panel is driven by the specified drive voltage. In this way, when changing (shifting) from the first display state to the second display state, it becomes possible to automatically change the drive voltage sequentially, reducing the processing load on the control device, etc. Can be realized.

  In the aspect of the invention, the drive voltage output unit may include a second level shifter that shifts a third voltage level that is a voltage level of the drive signal to the first voltage level.

  In this way, the drive signal can be handled at the third voltage level.

In one embodiment of the present invention, the integrated circuit device may further include a power supply circuit that supplies the first voltage level and the second voltage level.
The power supply circuit may generate a set voltage, and the range of the set voltage may have the first voltage level and the drive signal level.

  In this way, the power supply circuit can generate not only the first voltage level but also the level of the drive signal.

In one embodiment of the present invention, the integrated circuit device may further include a power supply circuit that supplies the third voltage level.
The third voltage level may be supplied to the first voltage level.

  In this way, the first output stage can output the drive voltage at the third voltage level. Therefore, the drive voltage output unit can output the drive voltage at the first voltage level, the second voltage level, or the third voltage level according to the driving method of the electro-optical panel.

In one aspect of the present invention, the drive waveform information may include N × N (N is an integer of 2 or more) drive waveform signals SWV (1, 1) to SWV (N, N).
The drive waveform information output unit
May have registers RT1 to RTM (M is an integer of 2 or more),
The registers RTk (1 ≦ k ≦ M) among the registers RT1 to RTM correspond to the drive waveform signals SWV (1, 1) to SWV (N, N) in the basic period Tk among the basic periods T1 to TM. A register value specifying the signal level may be stored,
The drive waveform information output unit
You may have the output part which outputs the said register value from the said register | resistor RTk in the said basic period Tk.

  In this way, when changing from the first display state to the second display state, the output drive waveform signal selected from the drive waveform signals SWV (1, 1) to SWV (N, N) is changed. The electro-optical panel can be driven with the driving voltage based on the driving voltage. Further, the signal levels of the drive waveform signals SWV (1, 1) to SWV (N, N) in each basic period are set by register values, and the drive waveform signals SWV (1, 1) to SWV (N , N) can be varied. Accordingly, it is possible to generate drive waveform signals SWV (1, 1) to SWV (N, N) having various waveforms according to the drive method and display characteristics of the electro-optical panel. Furthermore, since not only the signal level in each basic period but also the length of each basic period of the drive waveform signals SWV (1, 1) to SWV (N, N) can be variably set, various drive waveform signals SWV can be set. (1, 1) to SWV (N, N) can be generated.

In one aspect of the present invention, the drive waveform information output unit includes:
It may have a register for storing a designated period for designating at least one of the basic periods T1 to TM and the number of repetitions of the designated period,
The output unit of the drive waveform information output unit may output the drive waveform information specified by the basic periods T1 to TM, the specified period, and the number of repetitions.

  In this way, when generating the drive waveform information (drive waveform signals SWV (1, 1) to SWV (N, N) in a narrow sense) by repeating the basic period, the number of registers RT1 to RTM is reduced, The storage capacity of the registers RT1 to RTM as a whole can be reduced. In addition, drive waveform information (drive waveform signals SWV (1, 1) to SWV (N, N) in a narrow sense) is easily generated, and as a result, it is easy to support a plurality of drive methods.

In one embodiment of the present invention, the drive waveform information may include identification information for setting the output terminal to a high impedance state.
The drive waveform information output unit may output a setting signal based on the identification information.

  In this way, the high impedance state of the output terminal can be set with the identification information.

  In the aspect of the invention, the driving voltage output unit may include a logic circuit that outputs a logic signal based on the driving signal and the setting signal, and is based on the logic signal reflecting the driving signal. The drive voltage may be output to the output terminal, and the output terminal may be set to a high impedance state based on the logic signal reflecting the setting signal.

  In this way, it is possible to control whether or not the output terminal is set to the high impedance state by the logic circuit.

  Another aspect of the invention relates to an electronic device including any one of the integrated circuit devices described above and the electro-optical panel.

1 is a configuration example of an integrated circuit device according to an embodiment. FIG. 2A to FIG. 2C are explanatory diagrams of integrated circuit devices of first and second comparative examples. 2 is a detailed configuration example of an integrated circuit device according to the present embodiment. Explanatory drawing of the method of providing a drive voltage output part in each I / O cell. The drive waveform example for demonstrating the operation | movement of this embodiment. 6A and 6B show examples of register value setting for generating a drive waveform. The drive waveform example for demonstrating the operation | movement of this embodiment. FIGS. 8A and 8B show setting examples of register values for generating drive waveforms. 2 shows a configuration example of a drive circuit. The other example of a structure of a drive circuit. FIG. 11A and FIG. 11B are configuration examples of a power supply circuit. The structural example of a drive waveform information output part. 6 shows a modified example of the drive waveform of FIG. 6 shows a first modification of the integrated circuit device according to the present embodiment. 6 shows a second modification of the integrated circuit device according to the present embodiment. 1 is a configuration example of an electronic apparatus according to an embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration FIG. 1 shows a configuration example of an integrated circuit device according to this embodiment. The integrated circuit device of this embodiment has a drive waveform generation function for driving the electro-optical panel 100. Specifically, it has a function of generating a sequential drive waveform necessary for changing the display of the electro-optical panel 100. The waveform information for generating the drive waveform is stored in, for example, a programmable storage unit (nonvolatile memory, ROM, register, etc.), and the drive waveform generation function is realized based on the waveform information stored in this programmable storage unit Is done.

  In order to realize such a drive waveform generation function, the integrated circuit device of this embodiment includes a drive voltage output unit 10, a display data storage unit 20, and a drive waveform information output unit 30.

  Taking an electrophoretic display (EPD) panel as an example, the electro-optical panel 100 can include a substrate, a counter substrate, and an electrophoretic layer provided between the substrate and the counter substrate. . The electrophoretic layer (electrophoretic sheet) is composed of a large number of microcapsules having an electrophoretic substance. This microcapsule, for example, disperses positively charged black positively charged particles (electrophoretic substance) and negatively charged white negatively charged particles (electrophoretic substance) in a dispersion, Realized by encapsulating in a capsule.

  Taking a passive EPD panel as an example, a substrate made of glass or transparent resin is provided with, for example, segment electrodes (drive electrodes, pixel electrodes). Further, a top plane electrode (common electrode) is provided on the counter substrate (electrophoresis sheet). In addition, an electrophoretic sheet may be formed by forming a top plane electrode with a transparent conductive material on a transparent resin layer, and applying an adhesive or the like thereon to adhere the electrophoretic layer.

  When an electric field is applied between the segment electrode and the top plane electrode, the positively charged particles (black) and the negatively charged particles (white) encapsulated in the microcapsule have an electrostatic force in the direction corresponding to the positive or negative charge. Works. For example, when the segment electrode has a higher potential than the top plane electrode, the positively charged particles (black) move to the top plane electrode side, so that the pixel is displayed in black. On the other hand, when the top plane electrode has a higher potential than the segment electrode, white display is performed.

  The electro-optical panel 100 is not limited to an EPD panel, and may be an ECD (electrochromic display) panel or the like. The ECD panel is a panel that realizes a display operation by utilizing a phenomenon that, when a voltage is applied, a substance is colored or a light transmittance is changed due to an oxidation-reduction reaction.

  The electro-optical panel 100 may be an electronic paper panel such as an ECP (Electrochromics Display) panel or an NCD (Nanochromics Display) panel. The integrated circuit device can correspond to a plurality of electro-optical panels, and one electro-optical panel 100 of the plurality of electro-optical panels can be connected to the drive voltage output unit 10 as shown in FIG. Hereinafter, an example of the driving voltage output unit 10 (integrated circuit device in a broad sense) connected to one electro-optical panel 100 will be described, and the driving voltage output unit 10 common to a plurality of electro-optical panels having different driving methods will be described. A specific configuration will be described later in “4. Other detailed configurations”.

  The drive voltage output unit 10 (drive unit) outputs a drive voltage VD (drive signal) supplied to the electro-optical panel 100. For example, the drive voltage VD supplied to the segment electrode (icon electrode, drive electrode, pixel electrode) of the electro-optical panel 100 is output. Thereby, driving of a passive type EPD panel or the like can be realized.

  The display data storage unit 20 (image data storage unit) stores display data DSEG (image data). The display data storage unit 20 can be realized by a register such as a flip-flop or a memory such as an SRAM.

  The drive waveform information output unit 30 outputs drive waveform information IDWV (drive waveform pattern information, drive voltage information). For example, the display state (gradation) at the segment electrode of the electro-optical panel 100 is changed from the first display state (first gradation, one of white display and black display) corresponding to the first display data DL to the second. Drive waveform information IDWV at the time of changing to the second display state corresponding to the display data DP (second gradation, the other of white display and black display) is output. Here, for example, the first display data DL is the previous display data, and the second display data DP is the current display data. The drive waveform information IDWV is information that defines a change in the drive waveform between the first and second display states when, for example, the display state changes from the first display state to the second display state. For example, the drive voltage VD in each of a plurality of change periods is specified by the drive waveform information IDWV.

  The drive voltage VD may be binary (for example, 0V, 15V) or ternary (for example, 0V, + 15V, -15V, or 0V, 15V, 30V). Alternatively, it may be four or more. Various values can be adopted as the value of the drive voltage VD depending on the type of the electro-optical panel 100 and the like.

  Further, the amount of current flowing through the segment electrode may be adjusted by adjusting the length of the period during which the drive voltage VD (for example, 15 V) is applied. Various methods can be adopted as the method of applying the drive voltage VD depending on the type of the electro-optical panel 100 and the like.

  The drive voltage output unit 10 includes first display data DL and second display data DP that are display data DSEG (segment data) output from the display data storage unit 20, and drive from the drive waveform information output unit 30. A drive voltage VD specified by the waveform information IDWV is output. For example, based on the first and second display data DL and DP, an output drive waveform signal is selected from a plurality of drive waveform signals of the drive waveform information IDWV, and drive specified (set) by the selected output drive waveform signal The voltage VD is output to the segment electrode of the electro-optical panel 100.

  FIG. 2A shows a configuration example of an integrated circuit device of a first comparative example of this embodiment. The integrated circuit device includes a drive voltage output unit 510, a host I / F (interface) 520, and a power supply circuit 530 (DC-DC converter).

  The drive voltage output unit 510 outputs a binary or ternary drive voltage from a terminal of EQ [123: 0] in order to directly drive the electro-optical panel 100 such as a passive EPD panel. For example, in the case of binary driving, either 0V (= GND) or 15V is output.

  The power supply circuit 530 (DC-DC converter) boosts the external power supply voltage MVDD to generate the drive power supply voltage HVDD. For example, when the external power supply voltage MVDD is a power supply voltage of 3 V from a lithium battery, the voltage is boosted 6 times by a charge pump method to generate a drive power supply voltage HVDD of about 15 to 18 V, and the drive voltage output unit 510 To supply. As a result, binary driving of 0V and 15V becomes possible. The power supply circuit 530 generates a voltage of 18V higher than 15V in consideration of the voltage drop due to the influence of the driving load of the EPD. The driving power supply voltage HVDD may be supplied from the outside.

  The drive voltage output unit 510 is supplied with the drive power supply voltage HVDD from the power supply circuit 530, selects either 0V or 15V drive voltage, and outputs the selected drive voltage to each terminal of EQ [123: 0]. 100 segment electrodes are driven. This drive voltage selection function is realized by the host I / F 520 (MPUI / F).

  For example, the logic power supply voltage LVDD is supplied to the host I / F 520. Then, a chip select signal XCS, a serial clock SCK, an output enable signal SEN, and data SDAT [3: 0] are input from an external control device such as an MPU (MCU). In this case, the data is meaningful so that the logic level “0” is 0V drive and the logic level “1” is 15V drive, and the drive information (0V, 15V) is received from the external control device via the host I / F 520. Then, as shown in FIG. 2B, on / off control of the output of the drive voltage from the terminal of EQ [123: 0] is performed by the output enable signal SEN.

  FIG. 2C shows a configuration example of the integrated circuit device of the second comparative example of the present embodiment. This integrated circuit device includes a drive voltage output unit 560, a latch circuit 570, a shift register 580, and a power supply circuit 590 (DC-DC converter). DATAIN serially input from an external control device is input to the shift register 580 in synchronization with the clock CKIN. When data corresponding to all the driver terminals EQ1, EQ2,... Is input to the shift register 580 as drive information, the drive information is latched by the latch circuit 570 by the latch signal LATCH. Then, a driving voltage of 0V or 15V corresponding to the latched driving information is output from the driving voltage output unit 560 to the driver terminals EQ1, EQ2,... To drive the segment electrodes of the electro-optical panel. Then, after the drive information is latched in the latch circuit 570, the next data is input to the shift register 580, and the drive information from the shift register 580 is latched again in the latch circuit 570, and 0V is applied to the driver terminals EQ1, EQ2,. Alternatively, a driving voltage of 15V is output.

  As described above, in the first and second comparative examples shown in FIGS. 2A to 2C, the external control device such as the MPU performs the sequential repetitive processing to change the display of the EPD panel. A drive waveform necessary for the generation is generated. Specifically, when the drive waveform is changed sequentially in order to change from the first display state (for example, black display) to the second display state (for example, white display), the control device has a plurality of sequential change periods. In each period, data is input to the host I / F and the shift register, and the output enable signal is activated (H level). For example, when the driving waveform is changed 10 times, the control device repeatedly executes the process of inputting data and activating the output enable signal 10 times. Therefore, the processing load on the control device becomes heavy, causing problems such as hindering other processes.

  On the other hand, in the integrated circuit device of this embodiment shown in FIG. 1, sequential drive waveforms necessary for changing the display of the electro-optical panel 100 are automatically generated. That is, the drive waveform information output unit 30 uses, as drive waveform information IDWV, drive waveforms for a plurality of periods when the display changes from the first display state (for example, black display) to the second display state (for example, white display). Output. Then, the drive voltage output unit 10 generates a plurality of periods based on the previous display data DL corresponding to the first display state, the current display data DP corresponding to the second display state, and the drive waveform information IDWV. Drive voltage VD is output. Therefore, the control device such as the MPU does not need to repeatedly execute the process of inputting the drive information data and the process of activating the output enable signal. For example, a sequential drive waveform for changing the display from the first display state to the second display state is automatically generated only by inputting a second display data set and a trigger signal by the control device. Therefore, the processing load of the control device can be remarkably reduced as compared with the first and second comparative examples of FIGS. 2 (A) and 2 (C).

2. Detailed Configuration FIG. 3 shows a detailed configuration example of the integrated circuit device of this embodiment. This integrated circuit device includes a host I / F (interface) 50 in addition to the drive voltage output unit 10, the display data storage unit 20, and the drive waveform information output unit 30. A power supply circuit 70, a clock selection circuit 80, and a clock generation circuit 82 can be included. Various modifications may be made such as omitting some of these components or adding other components.

  In the configuration example of FIG. 3, the drive waveform information output unit 30 has 2 × 2 = 4 (N × N in a broad sense; N is an integer of 2 or more) drive waveform signals SWV (1, 1) to SWV ( 2, 2) (SWV (1, 1) to SWV (N, N) in a broad sense) is output. Here, among the drive waveform signals SWV (1, 1) to SWV (2, 2), the drive waveform signal SWV (i, j) is the second when the first display state is the i state (1 ≦ i ≦ N). Is a drive waveform signal when the display state is j state (1 ≦ j ≦ N).

  For example, the first display state has two states, black display and white display, and the second display state also has two states, black display and white display. SWV (1, 1) is a drive waveform signal when the first and second display states are both black display (B), and SWV (1, 2) is the first display state being black display. This is a drive waveform signal when (B) and the second display state is white display (W). Similarly, SWV (2, 1) is a drive waveform signal when the first display state is white display (W) and the second display state is black display (B), and SWV (2, 2). These are drive waveform signals when the first and second display states are both white display (W).

  The drive voltage output unit 10 selects the output drive waveform signal SWQ from the drive waveform signals SWV (1, 1) to SWV (2, 2) based on the first display data DL and the second display data DP. To do. The voltage specified by the output drive waveform signal SWQ is output as the drive voltage VDm.

  For example, when the first display data DL corresponding to the first display state is black display data and the second display data DP corresponding to the second display state is black display data, the drive waveform When the signal SWV (1, 1) is selected and DL is black display data and DP is white display data, SWV (1, 2) is selected. Similarly, when DL is white display data and DP is black display data, SWV (2, 1) is selected. When DL and DP are both white display data, SWV (2, 2) is selected. ) Is selected.

  In the above, the case where each state of the first and second display states has two gradations (two states) of black display and white display has been described, but each of these states has three gradations or more. May be. For example, when each state has N gray levels, the drive waveform information output unit 30 outputs N × N drive waveform signals SWV (1, 1), SWV (1, 2)... SWV (1, N ), SWV (2, N), SWV (3, N)... SWV (N, N) are output.

  The drive voltage output unit 10 includes a drive circuit DR, a selector SEL, and a drive waveform selection circuit CSL. The drive circuit DR outputs a binary drive voltage VDm such as 0V and 15V, for example. The drive voltage VDm is output to the electro-optical panel via the pad PDm (terminal) of the integrated circuit device, and the segment electrode of the electro-optical panel is driven.

  The pad PDm (terminal) of the integrated circuit device can also be called an output terminal of the drive circuit DR.

  The drive voltage VDm may be three or more, and the voltage value of VDm is appropriately set according to the type of electro-optical panel (EPD panel or ECD panel). Further, for example, the drive circuit DR is provided with a level shifter, and this level shifter uses the drive power supply voltage (for example, 15V) from the power supply circuit 70 to change the voltage level (for example, 3V) of the output drive waveform signal SWQ to the voltage of VDm. Convert to level (for example, 15V).

  Further, when the high impedance state setting signal SHZ from the drive waveform information output unit 30 becomes active, the drive circuit DR sets its output terminal to the high impedance state. Thereby, on / off control of the drive of the segment electrode becomes possible. This kind of drive on / off control function is provided in the EPD panel and ECD panel types in the process of the drive sequence, not only in the specific drive voltage of binary or ternary, but also in the high level. This is because an impedance state may be necessary.

  The selector SEL is a circuit for switching between the sequential mode and the direct mode. For example, when the direct mode selection signal SDIR becomes active, the operation mode is set to the direct mode, and the display data DP signal from the current display data storage unit 22 is selected and output to the drive circuit DR. Thereby, as in the comparative example of FIG. 2A, a direct mode in which a control device such as an external MPU directly sets a sequential drive voltage is realized.

  On the other hand, when the signal SDIR becomes inactive, the output drive waveform signal SWQ from the drive waveform selection circuit CSL is selected and output to the drive circuit DR. This realizes a sequential mode in which a sequential drive waveform is automatically generated by the integrated circuit device.

  Based on the display data DL and DP from the display data storage unit 20, the drive waveform selection circuit CSL outputs the drive waveform signals SWV (1, 1) to SWV (2, 2) is selected and output as an output drive waveform signal SWQ. For example, suppose that DL = 0 and DP = 0 correspond to black display, and DL = 1 and DP = 1 correspond to white display. Then, when DL = 0 and DP = 0, SWV (1, 1) is selected. When DL = 0 and DP = 1, SWV (1, 2) is selected. When DL = 1 and DP = 0, SWV (2, 1) is selected. 1) is selected. When DL = 1 and DP = 1, SWV (2, 2) is selected.

  The display data storage unit 20 includes a current display data storage unit 22 that stores current display data DP and a previous display data storage unit 24 that stores previous display data DL. The current display data storage unit 22 has the same function as, for example, the shift register 580 in FIG. 2C, and the previous display data storage unit 24 has the same function as the latch circuit 570 in FIG. .

  For example, display data from the host is input and held in the current display data storage unit 22 via the host I / F 50. For example, when the number of segment electrodes is 124, 124 pieces of display data (segment data) are inputted and held in the current display data storage unit 22. All display data (124 pieces) is input to the current display data storage unit 22 and when the display based on the display data is completed, the display data held in the current display data storage unit 22 is the previous display data storage unit 24. And is held (latched). The display data storage unit 20 may be realized by a flip-flop or a memory such as an SRAM.

  The drive waveform information output unit 30 includes a drive waveform generation unit 32 and a timing control unit 34. The drive waveform generator 32 includes registers RT1 to RTM (M is an integer of 2 or more) and a register selection circuit RSEL. The timing control unit 34 includes a timing set counter 36 and a wait timer 38.

  The registers RT1 to RTM have the signal levels of the drive waveform signals SWV (1, 1) to SWV (2, 2) (SWV (1, 1) to SWV (N, N)) in each of the periods T1 to TM. Store the specified register value. Specifically, the registers RTk (1 ≦ k ≦ M) of the registers RT1 to RTM are driven waveform signals SWV (1, 1) to SWV (2, 2) in the period Tk of the periods T1 to TM. A register value for specifying the signal level of is stored. For example, the register RT1 stores a register value that specifies the signal level in the period T1 of SWV (1, 1) to SWV (2, 2), and the register RT2 stores SWV (1, 1) to SWV (2, SWV (1, 2). A register value specifying the signal level in the period T2 of 2) is stored. The same applies to the registers RT3 to RTM. The register values of these registers RT1 to RTM are input via the host I / F 50 and written to the registers RT1 to RTM.

  Note that each of the periods T1 to TM can also be referred to as a basic period.

  The register selection circuit RSEL selects a register value from any of the registers RT1 to RTM based on the selection signal SRSEL from the timing control unit 34. For example, the register value from the register RT1 is selected in the period T1, and the register value from the register RT2 is selected in the period T2. The same applies to the periods T3 to TM. As a result, the drive waveform information output unit 30 can output the register values from the registers RT1 to RTM in each of the periods T1 to TM. Specifically, the drive waveform information output unit 30 outputs the register value from the register RTk among RT1 to RTM in the period Tk. For example, in the period T1, the signal level register value from the register RT1 is output, and in the period T2, the signal level register value from the register RT2 is output. The same applies to the periods T3 to TM.

  In addition to the signal level register values of the drive waveform signals SWV (1, 1) to SWV (2, 2), the registers RT1 to RTM are, for example, period lengths for specifying the lengths of the periods T1 to TM. Register values can be stored. For example, the register RTk among RT1 to RTM stores a period length register value for setting the length of the period Tk.

  Then, the drive waveform information output unit 30 sets the length of the period Tk based on the period length register value from the register RTk. For example, the length of the period T1 is set based on the period length register value from the register RT1, and the length of the period T2 is set based on the period length register value from the register RT2. The same applies to the setting of the length of the periods T3 to TM.

  Specifically, the period length register values from the registers RT1 to RTM are input to the timing control unit 34 as the signal SWT via the register selection circuit RSEL. The wait timer value is set in the wait timer 38 by the signal SWT. Then, the timing set counter 36 outputs a signal SRSEL obtained based on the wait timer value to the drive waveform generation unit 32. Thereby, the length of each period of T1-TM is adjusted.

  The registers RT1 to RTM may store register values for setting the output terminal of the drive circuit DR to a high impedance state. For example, when the output terminal of the drive circuit DR is set to the high impedance state in the period Tk, a setting bit (bit 13 in FIG. 6A described later) of the high impedance state of the register RTk corresponding to the period Tk is set. For example, it is set to “1”. Thereby, the setting signal SHZ in the high impedance state becomes active in the period Tk.

  The host I / F 50 performs interface processing with the host (CPU, MPU, control device). The host accesses control registers such as a display setting register 52, a trigger register 54, an interrupt register 56, and a power supply setting register 58 via the host I / F 50.

  For example, the display setting register 52 includes instructions for selecting clocks used by the various timers of the timing control unit 34, instructions for reversing the display from the display state of the electro-optic panel, instructions for displaying all black and all white, direct mode and sequential mode. This register is used to set the selection instruction. The trigger register 54 is a register for issuing a trigger for starting a drive waveform generation operation. The interrupt register 56 is a register in which an interrupt flag and an interrupt mask that are generated after the end of the drive waveform generation operation are set. The power supply setting register 58 is a register for performing various controls such as ON / OFF instruction of the power supply circuit 70, setting of a constant voltage circuit (regulator), setting of a boosting factor, and fine adjustment (contrast and trimming) of the boosting voltage. .

  The power supply circuit 70 generates a drive power supply voltage necessary for driving the electro-optical panel based on the power supply voltage supplied from the power supply terminal. For example, in the case of binary drive of 0V / 15V, the power supply voltage from the VDD terminal is boosted to generate a drive power supply voltage of, for example, HVDD = 15V and supplied to the drive circuit DR of the drive voltage output unit 10. The drive circuit DR outputs the drive voltage VDm using HVDD = 15V and VSS = 0V from the VSS terminal.

  Note that a drive power supply voltage may be supplied to the HVDD terminal from an external power supply IC or the like of the integrated circuit device. For example, when the electro-optical panel is large and a load current higher than the specification of the built-in power supply circuit 70 is required during driving, the drive power supply voltage HVDD may be supplied from the external power supply IC or the like in this way. .

  The clock generation circuit 82 includes an oscillation circuit 84 and a frequency dividing circuit 86, and generates clocks CK having various frequencies. The clock selection circuit 80 supplies the clock CKS selected from the clocks CK of the clock generation circuit 82 to the timing control unit 34 and the like.

  When the integrated circuit device has a plurality of I / O cells (input / output cells), the drive voltage output unit 10 of FIG. 3 is provided for each I / O cell of the plurality of I / O cells. It is desirable. Here, the I / O cell is an input / output cell connected to a pad (terminal) of the integrated circuit device and having at least one of an input buffer and an output buffer.

  For example, in FIG. 4, the drive voltage output unit 10 is provided for each of the I / O cells IO1 to IOm. The driving voltages VD1 to VDm output from the driving voltage output unit 10 of the I / O cells IO1 to IOm are output to the segment electrodes SEG1 to SEGm of the electro-optical panel via the pads PD1 to PDm.

  Drive waveform signals SWV (1, 1) to SWV (2, 2) from the drive waveform information output unit 30 and a high impedance setting signal SHZ are supplied to the I / O cells IO1 to IOm. These SWV (1, 1) to SWV (2, 2) and SHZ signal lines are wired on the chip core side region (region opposite to the pad) of the I / O cell or on the I / O cell. SWV (1, 1) to SWV (2, 2) and SHZ signals are supplied from the signal line to each I / O cell. The display data (DL, DP) of DSEG1 to DSEGm from the display data storage unit 20 is supplied to the I / O cells IO1 to IOm.

  As shown in FIG. 4, if a hard macro I / O cell provided with the drive voltage output unit 10 is provided, the layout efficiency can be improved and the chip size of the integrated circuit device can be reduced. The logic circuit portion of the drive voltage output unit 10 may be formed by automatic placement and wiring in a logic circuit block including a gate array and standard cells together with other logic circuits.

3. Drive Waveform Next, a specific example of the drive waveform generation method according to the present embodiment will be described with reference to FIGS.

  For example, in EPD, white display or black display is performed depending on the polarity of the drive bias applied between the segment electrode (data electrode) and the top plane electrode (common electrode). It is also possible to insert a color filter to give white display a color. In this case, the white display white can be replaced with a filter color.

  In order to maintain the display quality of EPD at a high quality, it is not sufficient to simply apply a bias having a driving polarity necessary for white display or black display. For example, when changing the display of the EPD, not only a necessary bias is applied to the segment to be changed, such as white to black or white to black, but for example black to black or white to white. As described above, it is desirable to apply a sequential drive bias in which a positive polarity bias and a negative polarity bias are mixed to all segments including a segment that is not a display change target. Note that this is not the case when display quality is not an issue.

  A sequential drive bias pattern in which a positive polarity bias and a negative polarity bias are mixed is set in response to changes in display states from black to white, white to black, black to black, and white to white. In this embodiment, such a pattern is called a drive waveform.

  FIG. 5 shows an example of such a drive waveform. “0” in the figure means, for example, 0V driving, and “1” means, for example, 15V driving.

  In FIG. 5, the binary driving waveform supplied to the top plane electrode common to all segments is TP. Drive waveform when the display state changes from black to black, BW from black to white, WB from white to black, and WW from white to white (from the first display state to the second display state) It is. These BB, BW, WB, and WW correspond to the drive waveform signals SWV (1, 1), SWV (1, 2), SWV (2, 1), and SWV (2, 2) in FIG.

  For example, in the idle state of A1 in FIG. 5, the high impedance state is set. In the charge removal period A2, TP = 0 and BB = 0, so that no bias is applied and black display is maintained. In A3, since TP = 1 and BB = 0, a positive polarity bias is applied, and the display changes from black display to white display. In A4, since TP = 0 and BB = 1, a negative bias is applied, and the display changes from white display to black display. In A5, since TP = 1 and BB = 0, the bias is positive, and the display changes from black display to white display. In A6, TP = 0 and BB = 1, and the memory contents are displayed, resulting in black display. That is, since BB is a driving waveform when the first display state is black display and the second display state is black display, A6 corresponds to the second display state (display data DP). Black display. Thereafter, charge removal shown in A7 is performed, and an idle state shown in A8 is entered.

  Similarly, in the drive waveform BW, as shown by B1, B2, B3, B4, and B5, an idle state, charge removal, white display, black display, and white display are performed. At B6, TP = 0 and BW = 0 are non-biased, and the white display set at B5 is maintained, so that the memory contents are displayed. That is, since BW is a driving waveform when the first display state is black display and the second display state is white display, BW corresponds to the second display state (display data DP). White display. Thereafter, charge removal shown in B7 is performed, and an idle state shown in B8 is entered. The same applies to the drive waveforms WB and WW.

  In C1, C2, C3, C4, C5, and C6, the length of each period of T1, T2, T3, T4, T5, and T6 is set. In other words, a time timing for changing the drive waveform is set.

  As shown in Fig. 5, high-quality display quality of EPD is achieved by repeating white display and black display in each period set to various lengths before displaying the actual memory contents (waveform information). Can be realized. That is, in the EPD, unlike the LCD, when changing from the first display state corresponding to the previous display data (DL) to the second display state corresponding to the current display data, over a plurality of periods. The drive waveform is changed sequentially. For example, in A2 to A6 of FIG. 5, when the black display that is the first display state is changed to the black display that is the second display state, the drive waveform is changed for each of a plurality of periods. Similarly, in B2 to B6, when the black display that is the first display state is changed to the white display that is the second display state, the drive waveform is changed for each of a plurality of periods. In this way, display quality can be improved by sequentially changing the drive waveform.

  FIG. 6A shows an example of register values set in the registers RT1 to RTM in FIG. 3 in order to realize the drive waveform in FIG. In FIG. 6A, T1 to T12 correspond to the registers RT1 to RT12, and a 16-bit register value is set in each register. Then, bits 12, 11, 10, 9, and 8 of each register store information on driving waveforms of TP, BB, BW, WB, and WW, respectively. Bits 7 to 0 are set with length information for each period (the number of counts used by the wait timer of the timing control unit).

  Bit 15 of each register is an EOW bit, which indicates the end of the drive waveform. In FIG. 6A, the EOW bit of the register RT6 corresponding to the period T6 is set to 1. Accordingly, in FIG. 5, the driving waveform ends in the period T6.

  Bits 12 to 8 of the register RT1 corresponding to the period T1 in FIG. 6A are all set to 0. Therefore, as shown in the drive waveform of FIG. 5, TP = BB = BW = WB = WW = 0, and charge removal is performed. Bits 7 to 0 representing the wait time of the register RT1 are set to (00000101). Therefore, as shown in FIG. 6B, the length of the period T1 is set to about 4.88 mS.

  Bits 12, 11, 10, 9, and 8 of the register RT2 corresponding to the period T2 in FIG. 6A are set to 1, 0, 0, 1, and 1, respectively. Therefore, as shown in the drive waveform of FIG. 5, in the period T2, TP = 1, BB = 0, BW = 0, WB = 1, and WW = 1, and all white display is performed. Bits 7 to 0 representing the wait time of the register RT2 are set to (10000011). Accordingly, as shown in FIG. 6B, the length of the period T2 is set to about 127.93 mS.

  The length of the period described above is merely an example, and can be arbitrarily changed by a register value set in the register RTk or a clock selection in the clock selection circuit 80.

  The drive waveform is not limited to that shown in FIG. 5, and the drive waveform can be changed as appropriate by changing the register value of the register RTk according to the type of EPD, the operating environment, and the like. For example, FIG. 7 shows another example of the drive waveform, and FIGS. 8A and 8B show examples of setting register values corresponding to the drive waveform of FIG.

  As described above, in this embodiment, based on the first and second display data DL and DP, the output drive waveform signal SWQ is selected from the plurality of drive waveform signals SWV (1, 1) to SWV (2, 2). Is selected, and the drive voltage VDm specified by the selected output drive waveform signal SWQ is output. Therefore, when changing from the first display state corresponding to the first display data DL to the second display state corresponding to the second display data DP, for example, with the drive voltage of the drive waveform signal that changes sequentially, The segment electrode of the electro-optical panel can be driven. Therefore, high quality display characteristics can be realized. In the present embodiment, such a sequential drive waveform signal is automatically generated, so that the processing load on the host (control device) can be reduced.

  In the present embodiment, each of the registers RT1 to RTM stores a register value that specifies the signal level of the drive waveform signal in each period. The register value from each register is output in each period. Therefore, the drive waveform signal can be changed by setting the signal level of each period of the drive waveform signal with the register value of each register. Therefore, drive waveform signals having various waveforms can be generated according to the display characteristics of the electro-optical panel.

  In the present embodiment, the length of each period can also be set based on the period length register value stored in each register. Accordingly, since not only the signal level in each period but also the length of each period of the drive waveform signal can be variably set, it is possible to generate a wider variety of drive waveform signals.

4). Other Detailed Configurations The drive voltage output unit 10, the power supply circuit 70, and the drive waveform information output unit 30 in FIG. 3 will be described below in order to support a plurality of electro-optical panels with different drive systems.

4.1. Drive Voltage Output Unit As described above, the drive voltage VDm in FIG. 3 is set to, for example, a binary value (for example, 0V, 15V) according to the type of the electro-optical panel. For example, an EPD panel can be driven with such a driving voltage (0 V, 15 V). However, when the drive voltage of the ECP panel is set to a binary value (for example, 0V, 3V), such an ECP panel cannot be driven with the drive voltage (0V, 15V). In this case, the first integrated circuit device in which the drive voltage VDm shown in FIG. 3 is set to a binary value (0V, 15V) and the drive voltage VDm shown in FIG. 3 is set to a binary value (0V, 3V). 2 integrated circuit devices need to be developed.

  Further, when the driving voltage of the NCD panel is set to, for example, a binary value (for example, 0 V, 1.5 V), the third integration in which the driving voltage VDm shown in FIG. It is also necessary to develop circuit devices. Therefore, the drive voltage output unit 10 shown in FIGS. 9 and 10 is useful for dealing with a plurality of electro-optical panels having different drive systems.

  FIG. 9 shows a configuration example of the drive circuit DR in the drive voltage output unit 10, and can also be called a specific example or a modification of the drive circuit DR in FIG. The combination of the drive waveform selection circuit CSL and the selector SEL (drive signal generator in a broad sense) in FIG. 3 can be used as it is. The drive waveform selection circuit CSL (drive signal generation unit in a broad sense) in FIG. 3 includes the first display data DL and the second display data DP from the display data storage unit 20 and the drive waveform signals SWV (1, 1) to SWV. An output drive waveform signal SWQ (drive signal in a broad sense) specified by SWV (2, 2) (drive waveform information from the drive waveform information output unit 30 in a broad sense) can be generated.

  When the direct mode selection signal SDIR becomes inactive, the selector SEL (drive signal generator in a broad sense) in FIG. 3 selects the output drive waveform signal SWQ from the drive waveform selection circuit CSL and outputs it to the drive circuit DR. . Note that the selector SEL in FIG. 3 may be omitted, and the drive circuit DR in FIG. 3 may always receive the output drive waveform signal SWQ.

  The drive circuit DR in FIG. 9 receives, for example, an output drive waveform signal SWQ (drive signal in a broad sense), and has a binary drive voltage VDm (first voltage level) such as 0V or 3V, or 0V or 15V. Any one of such binary drive voltages VDm (second voltage level) can be output. When the direct mode selection signal SDIR is active, the drive circuit DR in FIG. 9 may input the display data DP (drive signal in a broad sense) via the selector SEL instead of the output drive waveform signal SWQ. Good.

  Further, the drive circuit DR in FIG. 9 can also receive a high impedance setting signal SHZ (identification information in a broad sense). As described above, the registers RT1 to RTM in FIG. 3 may store a register value (identification information) for setting the output terminal of the drive circuit DR to a high impedance state. For example, when the output terminal of the drive circuit DR is set to the high impedance state in the period Tk, the setting bit (for example, bit 13 in FIG. 6A) of the register RTk corresponding to the period Tk is set to, for example, Set to “1”. Thereby, the setting signal SHZ in the high impedance state becomes active in the period Tk.

  As illustrated in FIG. 9, the drive circuit DR includes first output stages Tr_M1 and Tr_M2 that output a drive voltage based on the output drive waveform signal SWQ (drive signal in a broad sense) at a first voltage level. In addition, the drive circuit DR includes second output stages Tr_H1 and Tr_H2 that output a drive voltage based on the output drive waveform signal SWQ at a second voltage level. Further, the drive circuit DR includes first level shifters 12 and 13 that shift the first voltage level to the second voltage level.

  The drive circuit DR includes, for example, a switch SW, and one of the output voltages of the first output stages Tr_M1 and Tr_M2 and the output voltages of the second output stages Tr_H1 and Tr_H2 is output to the output terminal. When the drive circuit DR does not include the switch SW, for example, the outputs of the first output stages Tr_M1 and Tr_M2 and the output terminals so that only the output voltages of the first output stages Tr_M1 and Tr_M2 are always output to the output terminals. May be connected by, for example, wiring.

  In the example of FIG. 9, the drive circuit DR includes logic circuits 16 and 17 that output logic signals based on the output drive waveform signal SWQ and the setting signal SHZ. In the example of FIG. 9, in the first region, the logic level “0” is, for example, VSS = 0V, and the logic level “1” is, for example, the drive power supply voltage HVDD1 = 3V. In the second region, the logic level “1” is, for example, the drive power supply voltage HVDD2 = 15V.

  When the logic level of the output drive waveform signal SWQ indicates “1” and the logic level of the setting signal SHZ indicates “0”, the logic levels of the logic signals output from the logic circuits 16 and 17 indicate “0”. When the logic level of the output drive waveform signal SWQ indicates “0” and the logic level of the setting signal SHZ indicates “0”, the logic levels of the logic signals output from the logic circuits 16 and 17 indicate “1”. Thus, the output drive waveform signal SWQ is reflected on the logic signals output from the logic circuits 16 and 17. When the output voltage of the first output stage Tr_M1, Tr_M2 and the output terminal are connected and the logic level of the output drive waveform signal SWQ indicates “1”, the output voltage of the first output stage Tr_M1, Tr_M2 is 3V− 0V = 3V is output and output to the output terminal as the drive voltage VDm.

  When the logic level of the setting signal SHZ indicates “1”, the logic level of the first logic signal output from the first logic circuit 16 indicates “1”, and the second logic circuit 17 outputs the first logic signal. The logic level of the logic signal 2 indicates “0”. Thus, the setting signal SHZ is reflected in the first and second logic signals output from the first and second logic circuits 16 and 17. When the output voltage of the first output stage Tr_M1, Tr_M2 and the output terminal are connected and the logic level of the setting signal SHZ indicates “1”, the output terminal is set to a high impedance state.

  When the output voltage of the first output stage Tr_M1, Tr_M2 and the output terminal are connected, the drive circuit DR (drive voltage output unit 10 in a broad sense) is, for example, in binary drive of 0V / 3V or in a high impedance state. For example, an ECD panel can be driven.

  When the output voltage of the second output stage Tr_H1, Tr_H2 and the output terminal are connected, the logic signal output from the logic circuits 16, 17 is output to the second output via the first level shifters 12, 13. Input to stages Tr_H1 and Tr_H2. When the logic level of the output drive waveform signal SWQ indicates “1” and the logic level of the setting signal SHZ indicates “0”, the output voltages of the second output stages Tr_H1 and Tr_H2 indicate 15V−0V = 15V, The driving voltage VDm is output to the output terminal. When the output voltage of the second output stage Tr_H1, Tr_H2 and the output terminal are connected and the logic level of the setting signal SHZ indicates “1”, the output terminal is set to a high impedance state.

  When the output voltage of the second output stage Tr_H1, Tr_H2 and the output terminal are connected, the drive circuit DR (drive voltage output unit 10 in a broad sense) is, for example, in binary drive of 0V / 15V or in a high impedance state. For example, an EPD panel can be driven. As described above, for example, one of the EPD panel and the ECP panel, for example, can be selected by the switch SW, and the selected panel can be driven.

  FIG. 10 shows a configuration example of the drive circuit DR. When the voltage level of the output drive waveform signal SWQ is not the first voltage level but the third voltage level, the drive circuit DR shifts the third voltage level to the first voltage level. 14,15. In the example of FIG. 10, in the third region (Low Voltage region), the logic level “0” is, for example, VSS = 0V, and the logic level “1” is, for example, the logic circuits 16 and 17 and the inverters INV1, INV2, INV3. The drive power supply voltage (logic power supply voltage LVDD) of INV4 is 1.5V. The first voltage level of the first region (Mid Voltage region) is, for example, the driving power supply voltage HVDD1 = 3V, and the second voltage level of the second region (High Voltage region) is, for example, the driving power supply voltage HVDD2 = 15V.

4.2. Power Supply Circuit As shown in FIG. 9, when the drive circuit DR has two regions (first and second regions), the power supply circuit 70 in FIG. 3 has, for example, two constant voltage circuits (regulators). The first voltage level (for example, drive power supply voltage HVDD1 = 3 V) and the second voltage level (for example, drive power supply voltage HVDD2 = 15 V) are supplied to the drive circuit DR of the drive voltage output unit 10. As shown in FIG. 10, when there are three regions (third, first, and second regions) in the drive circuit DR, the power supply circuit 70 in FIG. 3 includes, for example, another constant voltage circuit (regulator). Further, a third voltage level (for example, drive power supply voltage (logic power supply voltage LVDD) = 1.5 V) can be further supplied.

  11A and 11B show configuration examples of the power supply circuit 70 that can correspond to the drive circuit DR in FIG. 9 and the drive circuit DR in FIG. The power supply circuit 70 in FIG. 11A has two constant voltage circuits REG1 and REG2, and the power supply circuit 70 in FIG. 11B has one constant voltage circuit REG1.

  In the example of FIG. 11A and the example of FIG. 11B, the power supply voltage VDD from the VDD terminal is 3V, for example, and when the switch SW2 is turned on, the constant voltage circuit REG1 outputs an output voltage of 3V, for example. The reference voltage Ref and the resistors R1, R2, and R3 are set so that the power supply voltage VDD from the VDD terminal is 2V, for example, and the constant voltage circuit REG1 outputs an output voltage of 1.5V, for example, when the switch SW1 is turned on. Can be set.

  The output voltage of the constant voltage circuit REG1 can also be referred to as a set voltage. When either the switch SW2 or the switch SW1 is turned on, the set voltage is set to either 3V or 1.5V. .

  When the output voltage of the constant voltage circuit REG1 is 3V, the drive power supply voltage HVDD1 of 3V can be generated by turning on the switch SW3. When the output voltage of the constant voltage circuit REG1 is 1.5V, the switch SW4 is turned on to generate a drive power supply voltage (logic power supply voltage LVDD) of 1.5V and a boost set to, for example, twice. A drive power supply voltage HVDD1 of 3V can be generated via the circuit 18.

  With the switches SW2 and SW3 turned on, the 3V drive power supply voltage HVDD1 (and 3V logic power supply voltage LVDD) can be supplied to the first region of the drive circuit DR in FIG. The 3V drive power supply voltage HVDD1 may be supplied to the logic circuits 16 and 17 and the inverters INV1, INV2, INV3, and INV4 of FIG. 9, and the 3V logic power supply voltage LVDD may be supplied to the logic circuits 16 and 17 and the inverter of FIG. It may be supplied to INV1, INV2, INV3, INV4. Further, in the state where the switches SW1 and SW4 are turned on, the 1.5V drive power supply voltage (logic power supply voltage LVDD) is supplied to the third region of the drive circuit DR in FIG. 10, and the 3V drive power supply voltage HVDD1 is shown. This can be supplied to the first region of the ten drive circuits DR.

  In the example of FIG. 11A, a power supply voltage of 21 V is supplied to the constant voltage circuit REG2 through the booster circuit 19 set to 7 times, for example. The resistors R4 and R5 can be set so that the constant voltage circuit REG2 outputs an output voltage of, for example, 15V. The drive power supply voltage HVDD2 of 15V can be supplied to the second region of the drive circuit DR shown in FIGS. In the example of FIG. 11B, the drive power supply voltage HVDD2 of 15 V can be supplied to the second region via the booster circuit 19 set to 5 times, for example.

  In the drive circuit DR of FIGS. 9 and 10, when the output voltage of the first output stage Tr_M1, Tr_M2 and the output terminal are connected, the second output stage Tr_H1, Tr_H2 does not need to operate. Therefore, for example, when the ECD panel is driven by the binary drive of 0V / 3V from the first output stage Tr_M1, Tr_M2, for example, the booster circuit 19 of FIG. 11A and FIG. The drive power supply voltage HVDD2 may not be generated. For example, when the booster circuit 19 is stopped, power consumption can be reduced.

  In the example of FIG. 11A and the example of FIG. 11B, when the switches SW2 and SW3 are turned on and the 3V drive power supply voltage HVDD1 is generated, the booster circuit 18 can be stopped. Further, in the example of FIG. 11A and the example of FIG. 11B, only the switch SW1 may be turned on. When only the switch SW1 is turned on, it is not necessary to generate the 1.5V drive power supply voltage (logic power supply voltage LVDD) and the 3V drive power supply voltage HVDD1. When the 3V drive power supply voltage HVDD1 is not generated, the 1.5V drive power supply voltage (logic power supply voltage LVDD) can be supplied to, for example, the first output stages Tr_M1 and Tr_M2 in FIGS.

  In the example of FIG. 9 and the example of FIG. 10, the driving power supply voltage HVDD1 (first voltage level) of the first output stage Tr_M1, Tr_M2 is set to 1.5V driving power supply voltage (logic power supply voltage LVDD, third voltage level). ) Is supplied, for example, 0V / 1.5V binary drive from the first output stage Tr_M1, Tr_M2, or an NCD panel can be driven in a high impedance state.

4.3. Drive Waveform Information Output Unit FIG. 12 shows a configuration example of the drive waveform information output unit 30, and can also be called a specific example or a modification of the drive waveform information output unit 30 in FIG. As illustrated in FIG. 12, the drive waveform information output unit 30 includes registers RL1 to RL3 (second storage unit) in addition to the registers RT1 to RTM (first storage unit).

  FIG. 13 shows a modification of the drive waveform of FIG. Since the drive waveform information output unit 30 in FIG. 12 includes the loop control unit 39 that uses the registers RL1 to RL3, for example, the periods T2 to T4 in the periods T1 to T6 in FIG. (See FIG. 13).

  The register RL1 of FIG. 12 can store (designate) one period (for example, the period T2 of FIG. 13) corresponding to the registers RT1 to RTM as the start period of the designated period. Further, the register RL2 can store (specify) one period of the periods T1 to TM (for example, the period T4 in FIG. 13) as the end period of the specified period. Furthermore, the register RL3 can store (specify) the number of repetitions (for example, twice in FIG. 13) of the specified period (from the start period to the end period).

  The timing control unit 34 in FIG. 12 can send the current period CTS selected by the register selection circuit RSEL to the loop control unit 39. The loop control unit 39 can determine the next period NTS based on the current period CTS, the start period, the end period, and the number of repetitions, and can send it to the timing control unit 34.

  The register selection circuit RSEL that outputs the register value from the register RTk among the registers RT1 to RTM to the drive voltage output unit 10 in the period Tk can be called an output unit. The register selection circuit RSEL (output unit of the drive waveform information output unit 30) has drive waveform information (for example, the drive shown in FIG. 13) specified by the periods T1 to TM, the specified periods (start period and end period in a narrow sense), and the number of repetitions. Waveform signals SWV (1, 1) to SWV (2, 2)) can be output.

  The host can access the registers RL1 to RL3 (second storage unit) via the host I / F 50. As the designated period, at least one period (basic period) among the periods T1 to TM can be set. By generating the drive waveform information by repeating the basic period, the number of registers RT1 to RTM can be reduced, and the storage capacity of the registers RT1 to RTM as a whole can be reduced. Also, drive waveform information (drive waveform signals SWV (1, 1) to SWV (N, N) in a narrow sense) is set according to the combination of the specified period and the number of repetitions, and corresponds to a plurality of electro-optical panels. You can also.

  The second storage unit can store a plurality of designated periods and a plurality of repetition times. Further, the registers RT1 to RTM (first storage unit) may be expanded to store at least one designated period and at least one number of repetitions in the registers RT1 to RTM.

5. Modified Examples Next, various modified examples of the present embodiment will be described. FIG. 14 shows a first modification of the integrated circuit device of this embodiment. The first modification is an application example to a microprocessor having a driver function. The integrated circuit device includes a processor 110, a memory controller 120, a memory 130, a driver unit 140, a serial I / F 150, a temperature detection unit 160, a power supply circuit 170, a clock selection circuit 180, and a clock generation circuit 182. Various modifications may be made such as omitting some of these components or adding other components.

  The processor 110 (CPU core, host) performs various control processes and arithmetic processes, and includes a temperature information acquisition unit 112 and a display update unit 114. The temperature information acquisition unit 112 acquires temperature information (environment temperature) detected by the temperature detection unit 160, for example. The display update unit 114 performs display change processing of the electro-optical panel. The functions of the temperature information acquisition unit 112 and the display update unit 114 can be realized by, for example, hardware of the processor 110 and firmware (software) executed by the processor 110. For example, firmware for executing the processing of the temperature information acquisition unit 112 and the display update unit 114 is stored in the memory 130, and the temperature information acquisition unit 112 and the display update unit 114 are operated by the processor 110 operating based on the firmware. The function is realized.

  The memory controller 120 performs access control such as read control and write control of the memory 130. The memory 130 is a non-volatile memory such as a flash memory, for example. The memory 130 may be a mask ROM or the like.

  The driver unit 140 drives the electro-optic panel, and includes a drive voltage output unit 10, a display data storage unit 20, a drive waveform information output unit 30, and a host I / F 50.

  The serial I / F 150 realizes a serial interface such as SPI or I2C with the outside. The temperature detector 160 detects the temperature using a temperature sensor or the like. For example, the ambient temperature is detected by measuring resistance ratio information between the thermistor and the reference resistor. The power supply circuit 170 generates and supplies various power supply voltages such as a drive power supply voltage. The clock generation circuit 182 generates clocks of various frequencies, and the clock selection circuit 180 performs clock selection of the clock generated by the clock generation circuit 182.

  In FIG. 14, the memory 130 stores a plurality of waveform information IW1 to IWn. When the memory 130 is a non-volatile memory such as a flash memory, the waveform information IW1 to IWn is previously programmed in the non-volatile memory. Then, the processor 110 selects waveform information from the waveform information IW1 to IWn stored in the memory 130 via the memory controller 120. Then, the selected waveform information that is the selected waveform information is transferred to the driver unit 140. The drive waveform information output unit 30 of the driver unit 140 outputs drive waveform information based on the selected waveform information. For example, the selected waveform information is set as register values (register values of signal level and period length) of the registers RT1 to RTM in FIG.

  As described above, by storing the waveform information IW1 to IWn in the memory 130 accessible by the processor 110, it is possible to easily select the necessary waveform information when generating the drive waveform signal using the waveform information. Can be transferred.

  The waveform information IW1 to IWn can be loaded from an external device (external memory or the like) using, for example, the serial I / F 150 or a general-purpose input / output terminal, and can be written in the memory 130.

  Further, in the case of an integrated circuit device (such as a custom IC) that is known not to require a plurality of waveform information, only the determined waveform information may be stored in the memory 130.

  In FIG. 14, the processor 110 serving as the host performs setting in the various registers 52, 54, 56, and 58 described in FIG. 3 after transferring the waveform information to the driver unit 140. For example, basic settings such as setting a timer clock for determining the timing time of the drive waveform, voltage setting / boosting setting of the power supply circuit 70, and enabling / disabling of interrupts are performed. Further, when the oscillation circuit necessary for generating the timer clock is different from the oscillation circuit serving as the clock source of the processor 110, the setting of turning on the operation of the oscillation circuit is performed.

  The various settings as described above are realized by software (firmware) executed by an initial setting routine of the processor 110. Note that these settings can be made unnecessary after the initial settings have been made. Then, after the initial setting, the display of the electro-optical panel can be changed by software processing similar to that of a normal LCD driver or the like. Specifically, the processor 110 writes display data in the display data storage unit 20 of the driver unit 140. Then, a trigger for starting driving is set in the trigger register 54 described in FIG. As a result, a sequential drive waveform as shown in FIG. 5 is generated, the segment electrodes of the electro-optical panel are driven, and the display of the electro-optical panel is changed.

  If the display content is fixed, display data corresponding to the fixed display content is stored in advance in the memory 130 as shown in FIG. For example, when displaying a specific number in the 7-segment display, display data corresponding to the font of the specific number is stored in advance. Then, the processor 110 transfers the display data to the display data storage unit 20 of the driver unit 140, whereby the display change of the electro-optical panel is realized.

  In FIG. 14, for example, the temperature information acquisition unit 112 uses the temperature detection unit 160 to acquire ambient temperature information. Then, the drive waveform information output unit 30 of the driver unit 140 outputs drive waveform information based on the selected waveform information selected based on the acquired temperature information. Specifically, the processor 110 selects waveform information corresponding to the acquired temperature information from the waveform information IW1 to IWn stored in the memory 130. Then, the selected waveform information is transferred to the driver unit 140, a sequential drive waveform is generated based on this waveform information, and the electro-optical panel is driven.

  In this way, even when the ambient temperature changes, the waveform information optimum for the temperature at that time is selected from the plurality of waveform information IW1 to IWn, and the electro-optical panel is driven. Become. Therefore, even if the ambient temperature changes, it is possible to maintain high quality display characteristics.

  In FIG. 14, the display update unit 114 performs display update processing for the electro-optical panel. The drive waveform information output unit 30 of the driver unit 140 outputs drive waveform information based on the waveform information selected according to the length of the display update time of the electro-optical panel. For example, when the display update time is long, there is a possibility that high display quality cannot be maintained even if driving is performed using normal waveform information.

  In this regard, in FIG. 14, for example, when the display update time becomes long, the waveform information stored in the memory 130 for the case where the display update time becomes long is selected, transferred to the driver unit 140, and The optical panel is driven. For example, when the display update time exceeds a predetermined threshold value, waveform information for preventing burn-in (for example, FIG. 7) for repeating black display and white display is selected and transferred to the driver unit 140 for display change. A trigger is implemented. In this way, even when the display of the electro-optical panel is not updated over a long period of time, the drive based on the waveform information for preventing burn-in is intermittently performed. It becomes possible.

  FIG. 15 shows a second modification of the integrated circuit device of this embodiment. This second modification is an example applied to a display driver. This integrated circuit device includes a serial I / F 210, a command decoder 220, and a driver unit 240. Various modifications such as omitting some of these components or adding other components (for example, a power supply circuit and a timing control unit) are possible.

  The serial I / F 210 is an interface for inputting various commands, display data, and waveform information from a control device such as an MPU. The command decoder 220 decodes and interprets the command issued by the control device. The driver unit 240 drives the segment electrodes SEG1, SEG2,... Of the electro-optical panel based on the issued command, display data, and waveform information. A parallel I / F or the like may be provided instead of the serial I / F 210.

6). Electronic Device FIG. 16 shows a configuration example of an electronic device including the integrated circuit device 300 of this embodiment. The electronic apparatus includes an electro-optical panel 100, an integrated circuit device 300, an operation unit 310, a storage unit 320, and a communication unit 330. Various modifications may be made such as omitting some of these components or adding other components.

  The integrated circuit device 300 is a display driver for driving the electro-optical panel 100, a macro computer having a driver function, or the like.

  The electro-optical panel 100 is for displaying various images (information), and is, for example, an EPD panel or an ECD panel. The operation unit 310 is used by the user to input various information, and can be realized by various buttons, a keyboard, and the like. The storage unit 320 stores various information and can be realized by a RAM, a ROM, or the like. The communication unit 330 performs communication processing with the outside.

  In addition, as an electronic device implement | achieved by this embodiment, various apparatuses, such as an electronic card (credit card, a point card, etc.), electronic paper, a remote control, a clock, a mobile telephone, a portable information terminal, a calculator, can be assumed, for example.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term (such as an EPD panel) that is described at least once together with a different term (such as an electro-optical panel) in a broader or synonymous manner in the specification or drawings is referred to as the different term in any part of the specification or drawings. Can be replaced. Further, the configurations and operations of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

10 drive voltage output unit, 12 to 15 level shifter, 16, 17 logic circuit,
18, 19 booster circuit, 20 display data storage unit, 22 current display data storage unit,
24 last display data storage unit, 30 drive waveform information output unit, 32 drive waveform generation unit,
34 timing controller, 36 timing set counter,
38 wait timer, 39 loop control unit, 50 host I / F,
52 display setting register, 54 trigger register, 56 interrupt register,
58 power setting register, 70 power supply circuit, 80 clock selection circuit,
82 clock generation circuit, 84 oscillation circuit, 86 divider circuit,
100 electro-optic panel, 110 processor, 112 temperature information acquisition unit,
114 display update unit, 120 memory controller, 130 memory,
140 Driver part, 150 Serial I / F, 160 Temperature detection part,
210 serial I / F, 220 command decoder, 240 driver part,
300 integrated circuit device, 310 operation unit, 320 storage unit, 330 communication unit

Claims (9)

A drive voltage output unit that outputs a drive voltage supplied to the segment electrode of the electro-optic panel to an output terminal;
A display data storage unit for storing at least first display data and second display data;
Drive waveform for outputting drive waveform information when the display state at the segment electrode changes from the first display state corresponding to the first display data to the second display state corresponding to the second display data An information output unit,
The drive voltage output unit is
A drive signal generation unit that generates a drive signal specified by the first display data and the second display data from the display data storage unit and the drive waveform information from the drive waveform information output unit;
A first output stage for outputting the drive voltage based on the drive signal in a first voltage range;
A first level shifter that shifts the drive voltage based on the drive signal from the first voltage range to a second voltage range;
A second output stage for outputting the drive voltage in the second voltage range based on an output voltage of the first level shifter;
A switch that selects one of the output voltage of the first output stage and the output voltage of the second output stage and outputs the selected output voltage to the output terminal;
Have
When the first electro-optical panel is connected to said output terminal, said driving waveform information output unit may output the first drive waveform information corresponding to the first electro-optical panel, said switch, The integrated circuit device is set so as to select and output one of the output voltage of the first output stage and the output voltage of the second output stage corresponding to the first electro-optical panel. ,
If the second electro-optical panel is connected to said output terminal, said driving waveform information output unit may output the second driving waveform information corresponding to the second electro-optical panel, said switch, The integrated circuit device sets the output voltage of the first output stage and the output voltage of the second output stage to select and output the other output voltage corresponding to the second electro-optical panel. And
The first drive waveform information and the one output voltage are higher in display quality when used in the first electro-optic panel than the second drive waveform information and the other output voltage. Information and output voltage,
The second drive waveform information and the other output voltage are higher in display quality when used in the second electro-optical panel than the first drive waveform information and the one output voltage. An integrated circuit device characterized by information and output voltage . In claim 1,
The driving voltage output unit shifts the driving voltage based on the driving signal from a third voltage range to the first voltage range and outputs the driving voltage to the first output stage and the first level shifter. An integrated circuit device comprising: a level shifter. In claim 1,
A power supply circuit for supplying a voltage level of the first voltage range and a voltage level of the second voltage range;
The integrated circuit device, wherein the power supply circuit generates a set voltage, and the range of the set voltage has a voltage level of the first voltage range and a level of the drive signal. In claim 2,
A power supply circuit for supplying a voltage level in the third voltage range;
The integrated circuit device, wherein the voltage level of the third voltage range is supplied as the voltage level of the first voltage range. In any one of Claims 1 thru | or 4,
The drive waveform information includes N × N (N is an integer of 2 or more) drive waveform signals SWV (1, 1) to SWV (N, N),
The drive waveform information output unit
Registers RT1 to RTM (M is an integer of 2 or more),
The registers RTk (1 ≦ k ≦ M) among the registers RT1 to RTM correspond to the drive waveform signals SWV (1, 1) to SWV (N, N) in the basic period Tk among the basic periods T1 to TM. Store the register value specifying the signal level,
The drive waveform information output unit
An integrated circuit device comprising: an output unit that outputs the register value from the register RTk in the basic period Tk. In claim 5,
The drive waveform information output unit
A register for storing a designated period for designating at least one of the basic periods T1 to TM and the number of repetitions of the designated period;
The integrated circuit device, wherein the output unit of the drive waveform information output unit outputs the drive waveform information specified by the basic periods T1 to TM, the specified period, and the number of repetitions. In any one of Claims 1 thru | or 6.
The drive waveform information has identification information for setting the output terminal to a high impedance state,
The driving circuit information output unit outputs a setting signal based on the identification information. In claim 7,
The drive voltage output unit includes a logic circuit that outputs a logic signal based on the drive signal and the setting signal, and outputs the drive voltage to the output terminal based on the logic signal reflecting the drive signal. An integrated circuit device, wherein the output terminal is set to a high impedance state based on the logic signal reflecting the setting signal. An integrated circuit device according to any one of claims 1 to 8,
The electro-optic panel;
An electronic device comprising: