JPH04191680A - Semiconductor integrated circuit having incorporated self-diagnostic function - Google Patents

Abstract

PURPOSE:To facilitate logical inspection by connecting a register capable of changing over the function as a shifter and the function as an LFSR to the product term line of a PLA and respectively individually self-diagnosing an AND plane and an OR plane. CONSTITUTION:At the time of the execution of a self-diagnostic program, a register group 53 is changed over to an FSR from a control signal wire 54. The input of an AND plane 50 is made active one at a time by a shifter and the output of the AND plane 50 is compressed by the register group 53 connected to product term lines 52. The compressed result is compared with an expected value by a comparator and the result of self-diagnosis is judged. Next, the register group 53 is changed over by the shifter to make the product term lines 52 active one at a time and the output of an OR plane 51 is compressed by a compression circuit. This compressed result is compared with an expected value by a comparator to judge the result of self-diagnosis.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit having a function of detecting a failure by a built-in self-diagnosis function without applying a test pattern from the outside. It is.

[Conventional technology]

In VLSI microprocessors and the like having extremely high transistor integration, a test input generator and a determination circuit are incorporated into the VLSI to facilitate testing thereof. FIG. 4 is a block diagram of this conventional built-in self-diagnosis mechanism, which consists of a series generation section (30) and a determination section (32). The sequence generation unit (30) uses a binary count or L
FSR (Linear Feedback 5h
ift Register). Judgment section (32
) has a compression circuit (32a) for the response output series from the combinational circuit (31), and the method of compressing the response output series using a counter or LFSR is usually called a signature analysis method. Finally, the output of the compression circuit (32a) and the reference value (32b) are passed through a comparator (32c) to determine whether it is normal or defective.

Next, Intel180386 will be explained as a specific conventional example. FIG. 5 is a block diagram of the built-in self-diagnosis mechanism of the Intel 180386. 3 big PLs
A 1 (40), P L A 2 (41), P L
A 3 (42), and during inspection, the normal PLA input is disconnected and the LFSR (40a), (41a), (4
2a) adds 2N-1 pseudo-random numbers to AND7L and a. The OR output section of the PLA has LFSRs (40b), (41b), and (42b) that input each output in parallel.
Accumulate calculation results for comprehensive input. CROM
(For microprogram) The input section of (43) has 2
A forward counter (43a) is connected. During testing, there is an LFSR (43b) in which a counter calculates all 2'' combinations and inputs them in parallel, and accumulates calculation results for exhaustive inputs.

Asserting the BUSY# bin (44) to 1 during reset starts the installation test. PLA 3 (42
) has the maximum number of inputs and requires 19 people, so 219
= 512, the cycle self-diagnosis is performed. This self-diagnosis ends when P L A 3 (42) returns to its original value. Next, execute the microneed instruction and create two 32
Bit accumulation register signature (45a), (45b
J is stored inside the chip via M-BUS (49) and is EXORed with the correct signature constant (46).
is performed in the ALU (47), and the EAX register (48
). If the FAX device is normal, the FAX
All contents of Regisk (48) will be '0''.FAX
The contents of the register (48) are user-visible, allowing testing of the processor at power-up.

[Problem to be solved by the invention]

Conventional semiconductor integrated circuits with a built-in self-diagnosis function were configured as described above, so when performing a 100% test in self-diagnosis of a PLA as the scale of the PLA increases,
Since the number of test vectors is enormous, there is a problem in that logic verification is difficult.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a semiconductor integrated circuit with a built-in self-diagnosis function that allows logic verification to be easily performed even when the PLA becomes large-scale. .

[Means to solve the problem]

In the semiconductor integrated circuit with a built-in self-diagnosis function according to the present invention, a register capable of switching between a function as a shifter and a function as an LFSR when executing a self-diagnosis program is connected to a product term line of a PLA, and thereby an AN
It has means for self-diagnosing the D plane and the OR plane individually.

[Effect]

The semiconductor S product circuit with a built-in self-diagnosis function in this invention activates the inputs of the AND plane one by one using a shifter when executing a self-diagnosis program, compresses the output of the AND plane with a register connected to the product term line, and then Then, the function of the register connected to the product term line is switched to a shifter to activate the product term line one by one and compress the output of the OR plane. By independently performing self-diagnosis on the AND plane and the OR plane, the test vector is shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit with built-in self-diagnosis function showing one embodiment of the present invention.

In the figure, (1) is a microprocessor, (2) a set pin, (31 is a float pin, +41 is a micro ROM section, which stores self-diagnosis programs and sends control signals to each block. (30) ) is the sequence generation part,
It functions as a shifter and generates input data when the self-diagnosis program is executed. (31) is a combinational circuit, which is a circuit to be tested.

(The compression circuit performs compression using the data 1eLFSR output by the combinational circuit [31). (32
b) is the expected value of self-diagnosis, and (32c) is a comparator.

FIG. 2 is a block diagram showing the internal configuration of combination circuit #I (31) in FIG. 1. In the figure, (50) is PL
AND plane of A, (51) is OR plane of PLA, (52
) is a product term line, (53) is a register group connected to the product term line, and (54) is a control signal line for switching the function of the register group (53) between a shifter function and an LFSR function.

Figure 3 shows the AND plane (50) and OR plane (51) in Figure 2.
) is configured as an NOR-NOR type.

In the figure, (56) is an AND plane clock signal, (57
) is the OR plane clock signal.

Next, the operation when executing the self-diagnosis program in the microprocessor of this embodiment will be explained.

First, by simultaneously asserting the reset pin (2) and float pin (3), the system enters the self-diagnosis mode and starts executing the self-diagnosis test of the microprogram.

The input of the combinational circuit (31) in this embodiment is 34 bits. When entering the self-diagnosis mode, the micro ROM section (
4) receives the control signal (21) from the combinational circuit (
The sequence generation unit (30) that generates the input of 31) is switched to a shifter. That is, the lower 1st bit of the 34-bit input latch is set to II II II, the other 33 bits are set to par 0'', and the 1st bit '1' is set every cycle.
°” shifts to the 2nd bit, 3rd bit, etc., and activates the inputs of the AND plane one by one. At the same time, the register group (53) is sent to LF from the control signal line (54).
Switch to SR.

The AND plane clock signal (56) is input at the same timing as in a normal processor mode even in the self-diagnosis mode. That is, during one cycle, the AND plane clock signal (56) becomes low active once and the product term line (52)
, then AND plane clock signal (5
6) to turn on the AND plane discharge transistor (58), and depending on whether the input signal line (61) to the AND plane is High or Low or whether there is a transistor or not, the product term line (52) Outputs Low or High. Therefore, AND plane (5
The output of the AND plane (50), that is, the value of the product term line (52), is uniquely determined only when one bit out of the 34 input bits of the input line (50) becomes active. This AND plane (5
The output of 0) is output every cycle and is compressed into a register group (53) which becomes an LFSR.

This compressed result is sent to Compare@(32c),
The result of the self-diagnosis is determined by comparing it with the expected value (32b). This judgment result (11) is 0 in register RO (13).
Written to the bit. If II II II is written, there is a fault in the AND plane. If "θ" is written, the AND plane is normal. The self-diagnosis of the AND plane is thus completed, and then the self-diagnosis of the OR plane is performed.

First, the control signal! From (54), the register group (53) is switched to a shifter. That is, ``1'' is set in the register connected to the product term line of the first tree, 0'' is set in the other registers, and 1'' is shifted to the adjacent register every cycle. Further, the product term for which II II II is set in this register becomes active. At the same time, the control signal (22) switches the IPLA output latch (32a) to the compression circuit.

The OR plane clock signal (57) is input even in the self-diagnosis mode at the same timing as in the normal processor mode. That is, during one cycle, the OR plane clock signal (57) becomes low active once, and the OR plane output (
60), then negates the OR plane clock signal (57) to turn on the OR plane discharge transistor (59), and the product term line (52) becomes H.
Depending on whether it is high or low or whether there is a transistor or not, the OR plane output (60) will be low or high.
Outputs igh.

When PA1°' is set in the register group (53), the product term line (52) becomes active, and an output uniquely determined from the OR plane is output to the compression circuit (32a).

The compressed result of the final cycle is sent to a comparator (32c) and compared with the expected value (32b) to determine the result of the self-diagnosis. The determination result (12) is written to the first bit of register RO (13). If It I II is written, there is a fault in the OR plane. II OI
If I is written, the OR plane is normal.

This completes the self-diagnosis of the OR plane. In this way, the self-diagnosis of the combinational circuit (31) is completed.

〔Effect of the invention〕

As described above, according to the present invention, each product term line is provided with a register that can switch the functions of LFSR and shifter, and self-diagnosis is performed separately for the AND plane and the OR plane, making logic verification easy. This has the advantage that the number of test vectors can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor integrated circuit with a built-in self-diagnosis function showing one embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of the combinational circuit (31) of FIG. 1, and FIG.
The figure shows the AND plane (50) in Figure 2 and the OR plane (51).
Figure 4 is a block diagram showing a conventional built-in self-diagnosis mechanism, and Figure 5 is a diagram showing a conventional built-in self-diagnosis mechanism.
FIG. 2 is a block diagram of the built-in self-diagnosis mechanism of nte180386. In the figure, (1) is the microprocessor, (2) the beam set pin, (3) is the float pin, (4) is the micro ROM section, (11) is the AND plane self-diagnosis judgment result, (
12) is the OR plane self-diagnosis judgment result, (13) is the register RO, (21), (22) is the micro ROM section (4)
(30) is a sequence generation unit, (31) is a combinational circuit, (32) is a determination unit, (32a) is a compression circuit, (32b) is an expected value, (32c) is a comparator, (50)
) is the AND plane of PLA, (51) is the OR plane of PLA, (52) is the product term line, (53) is the register group (54) connected to the product term line (52), and (56) is the control signal line. ) is A
ND plane clock signal, (57) is OR plane clock signal, (58) is AND plane discharge transistor, (59) is OR plane discharge transistor, (
60) shows the OR plane output, and (61) shows the input to the AND plane. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a semiconductor integrated circuit with a built-in self-diagnosis function that tests a PLA block based on a self-diagnosis program, the random number generator generates input data when executing the self-diagnosis program, and the PL receives the input data as input.
The P
A semiconductor integrated circuit with a built-in self-diagnosis function, characterized by comprising a circuit that arbitrarily divides an LA block and independently determines a self-diagnosis result.