JP2009004819A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP2009004819A JP2009004819A JP2008259161A JP2008259161A JP2009004819A JP 2009004819 A JP2009004819 A JP 2009004819A JP 2008259161 A JP2008259161 A JP 2008259161A JP 2008259161 A JP2008259161 A JP 2008259161A JP 2009004819 A JP2009004819 A JP 2009004819A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bonding
- electrode film
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05016—Shape in side view
- H01L2224/05017—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48455—Details of wedge bonds
- H01L2224/48456—Shape
- H01L2224/48458—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48724—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
- H01L2224/85206—Direction of oscillation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/2076—Diameter ranges equal to or larger than 100 microns
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】半導体チップ100の電極膜7の厚みを3.5μmから10μmにすることで、ボンディングワイヤ(アルミワイヤ12)の直径を300μm以上に太線化しても、層間絶縁膜6やn半導体基板1にクラックを発生させることなく、超音波ボンディングできる。
【選択図】図1
Description
図8は、ボンディングワイヤを固着した半導体チップの要部拡大断面図であり、同図(a)は平面図、同図(b)は同図(a)のX−X線で切断した要部断面図、同図(c)は同図(b)のA部の拡大図である。尚、平面図は半導体基板表面を示し、要部断面図はアルミワイヤ62が固着した半導体チップ200を示す。
半導体チップ200は、半導体基板51(例えばシリコン)の上に、ゲート酸化膜54、ポリシリコンのゲート電極55、層間絶縁膜56、電極膜57、さらにその上に図示しない保護膜が形成された構成となっている。そして、電極膜57には電気的接続を確保するためにボンディングワイヤであるアルミワイヤ62が超音波接合されている。また、半導体基板51には、ウエル領域52、エミッタ領域53が形成され、ゲート酸化膜54は、チャネル形成箇所上は、薄いゲート酸化膜54a、それ以外の箇所は厚いゲート酸化膜54bで形成され、テラスゲート構造58となっている。
このストライプ状の凹凸をした電極膜57の表面に、φ300μm未満のアルミワイヤ62が、このストライプ状の凸部59の長手方向65と直交するように超音波振動させて、ボンディングされている。この固着箇所63の形状は、振動方向に長い楕円形をしており、そのため、図8(a)のように、この楕円の長軸方向64はストライプ状の凸部59の長手方向65と直交する。
アルミワイヤ62の直径が300μm未満では、アルミ・シリコンで形成された電極膜の膜厚W0 を3μm程度以下にしても、ボンディング時に半導体チップ200を構成する層間絶縁膜56や半導体基板51のC部やD部で発生する機械的な応力を十分小さくできていた。
このような機械的損傷は、半導体チップ200の電気的特性不良、例えば、漏れ電流増大によるゲート特性不良(ゲート耐圧不良)などのチップ不良を発生させる。このチップ不良の発生率が増大すると、アルミワイヤ62の太線化により、製造工数の低減が図られたとしても、チップ不良率が増大することにより、IGBTモジュールのコストダウンは見込めなくなる。
また、機械的損傷が軽微で、ボンディング工程後の電気特性チェックで不良とならなかった場合でも、固着が不十分で、接合性が良好でない場合には、実使用時(スイッチング)の温度の上昇と降下の繰返しなどのパワーサイクルにより、ボンディング時の半導体チップ200の表面構造61(具体的には層間絶縁膜56や半導体基板51)にマイクロクラックが発生し、それを起点として、パワーサイクルにより大きなクラックに発展し、層間絶縁膜56や半導体基板51を破壊させたり、またアルミワイヤ62と電極膜57との固着部(接合部)を剥離させたりする。最悪の場合、半導体チップ200が動作しなくなる。
この発明の目的は、前記の課題を解決して、太線化されたボンディングワイヤを有し、半導体チップに機械的損傷がなく、ボンディングワイヤと半導体チップの接合状態が安定した半導体装置とその製造方法を提供することにある。
また、前記楕円形の接合面において、前記ボンディングワイヤと前記電極膜とは、前記電極膜表面のストライプ状の凸部ならびに凸部と凸部との間の部分で接合しているものとする。
また、半導体基板の一方の主面の表面層にウエル領域を形成し、該ウエル領域の表面層にエミッタ領域を形成し、前記ウエル領域と前記エミッタ領域はストライプ構造をなし、前記エミッタ領域に挟まれた前記ウエル領域上および前記半導体基板上にゲート酸化膜を介してゲート電極を形成し、該ゲート電極上に層間絶縁膜を形成し、コンタクトホールを開けた後、前記ウエル領域,前記エミッタ領域,前記層間絶縁膜上であって、前記層間絶縁膜上が凸部となるストライプ状の電極膜を形成し、該ストライプ状の電極膜にボンディングワイヤを超音波ボンディングする半導体装置の製造方法において、前記電極膜を前記凸部上の厚さが3.5μm以上で、10μm以下となるアルミ・シリコン膜で形成し、前記ボンディングワイヤに直径が300μm以上600μm以下のアルミワイヤを用い、前記ボンディングワイヤに、前記ストライプ状の電極の長手方向と直角の方向に超音波振動を与えて、前記ストライプ状の電極の長手方向と直角の方向が長軸なる楕円形の接合面を形成して前記電極膜と前記ボンディングワイヤとを接合するものとする。
n半導体基板1の一方の主面の表面層にpウエル領域2を形成し、pウエル領域2の表面層にnエミッタ領域3を形成する。pウエル領域2とnエミッタ領域3はストライプ構造をしている。
nエミッタ領域3に挟まれたpウエル領域2上およびn半導体基板1上にゲート酸化膜4を介してゲート電極5を形成する。ゲート構造は、チャネルが形成されない箇所のゲート酸化膜4bの膜厚を厚くしたテラスゲート構造8とする。ゲート電極5上に層間絶縁膜6を形成し、コンタクトホールを開けた後、エミッタ電極である電極膜7を、シリコンが微量(1%程度)に混入したアルミ・シリコン膜で形成する。この電極膜7の表面は、平坦でなく、テラスゲート構造8の厚いゲート酸化膜4b上の電極膜7の表面はストライプ状の凸部9となっている。
前記した電極膜7の表面に、図示しない超音波ボンダーにより、アルミワイヤ12を加圧し超音波振動させて固着(接合)する。このとき、図2のように、超音波振動の振動方向16はストライプ構造10の長手方向15に直角の方向であり、この直角方向は、アルミワイヤ12と電極膜7との固着箇所13(接合面)の長軸方向14と一致する。
この固着箇所13の平面形状は、超音波振動方向16に長い楕円形となり、従って、この楕円の長軸方向と振動方向も一致する。また、この楕円形の接合面で、アルミワイヤ12の自由端12a側がトウ側13aであり、アルミワイヤ12が図示しない超音波ボンダーに収納される側がヒール側13bとなる。
この電極膜7は、膜厚Wが3.5μm以上で10μm以下のアルミ・シリコン膜であり、この膜厚Wは、成膜装置の成膜時間あるいは成膜回数を制御することで、所定の厚い膜厚にする。また、ボンディングワイヤであるアルミワイヤ12の直径は、300μm以上で600μm以下である。
このように、電極膜の膜厚Wを3.5μm以上とすることで、超音波ボンディング時に層間絶縁膜6やn半導体基板1に発生する応力を低減できて、従来の膜厚W0 で、C部やD部に発生していたクラック60を無くすることができる。しかし、膜厚Wを10μmを超して増大させても、応力の低減効果は少なく、一方、製造コストは増大するために、膜厚Wは10μm以下がよい。つぎに、具体的な応力解析データについて説明する。
膜厚Wを増大させるほど、層間絶縁膜6に発生する応力は緩和される。勿論、n半導体基板1に加わる応力も緩和される。このように、応力が緩和されるのは、電極膜7が、座布団のような働きをして、電極膜の膜厚Wが厚くなるほど、クッション作用が大きくなるためである。従って、膜厚Wを増やせば、アルミワイヤ12に加える加圧力および超音波パワーを大きくすることができて、アルミワイヤ12の直径を大きくすることができる。
尚、図3は、アルミワイヤ12の直径が400μmの場合であるが、直径が600μmまで増大させても、図3の関係は殆ど変わらない。
図4は、アルミ・シリコンの電極膜の膜厚とチップ不良が発生する超音波パワーとの関係を示す図である。図の横軸は半導体チップ100の膜厚Wであり、3μmから10μmまで範囲とした。また、縦軸はチップ不良が発生する超音波パワーである。チップ不良とは、前記したようにゲート耐圧不良のことである。
また、ゲート耐圧が良好な半導体装置を用いて、温度差75℃で10万回のパワーサイクル試験を行った結果、このパワーサイクル試験に耐えるようにするためには、アルミワイヤ12に加える超音波パワーが8W以上必要であることが分かった。この試験に合格するということは、半導体装置のパワーサイクル耐量が確保されるということであり、このことは、電極膜7とアルミワイヤ12が、良好な接合性(十分大きい接合面積)を確保しているということを意味する。つまり、接合性を確保するためには、超音波パワーを8W以上とする必要があるということである。
以上より、ボンディング時のチップ不良の発生を抑え、且つ、アルミワイヤ12と電極膜7との接合性(パワーサイクル耐量)を確保するには、電極膜の膜厚Wを3.5μm以上とする必要がある。
一方、前記したように、この膜厚Wを10μmを超して大きくしても、層間絶縁膜6に発生する応力の低減効果が小さく、製造コストが増大する丈なので、膜厚Wは10μm以下でよい。
図5は、この発明の参考例の半導体装置であり、同図(a)は平面図、同図(b)は同図(a)のX−X線で切断した要部断面図、同図(c)は同図(a)のY−Y線で切断した要部断面図、同図(d)は、同図(b)のB部の拡大図である。
図1との違いは、超音波の振動方向16が、ストライプ状の凸部9の長手方向15に平行させて、アルミワイヤ12を電極膜7にボンディングする点である。この場合、楕円形の接合面(固着箇所13)の長軸方向14がストライプ構造10の長手方向15と平行になる。このときの長手方向15に対して長軸方向14(振動方向16と一致)の角度θ(図6に示す)は零となる。また、この角度θは20度以下であれば、振動による応力の直角成分(長手方向に対して)が小さい。勿論、この角度θが小さい程、直角成分が小さくなるために好ましい。
第1、第2実施例のように、半導体チップの電極膜7を厚膜化すること、ボンディング方向をストライプセル構造(ストライプ状の凸部9)と平行にすることで、ボンディング時に半導体チップの表面構造11(層間絶縁膜6やn半導体基板1)に発生する応力を緩和できて、初期欠陥のない高品質な半導体装置を提供できる。尚、これらの実施例は、当然、電気的配線にワイヤボンディングを使用している半導体装置に共通したものである。
2 pウエル領域
3 nエミッタ領域
4 ゲート酸化膜
4a 薄いゲート酸化膜
4b 厚いゲート酸化膜
5 ゲート電極
6 層間絶縁膜
7 電極膜
8 テラスゲート構造
9 ストライプ状の凸部
11 表面構造
12 アルミワイヤ
12a 自由端
13 固着箇所(接合面)
13a トウ側
13b ヒール側
14 長軸方向
15 長手方向
16 振動方向
Claims (3)
- 拡散領域を有する半導体基板上に絶縁膜を介して形成した電極膜と、該電極膜に超音波ボンディングで接合したボンディングワイヤを有する半導体装置において、前記電極膜を膜厚が3.5μm以上で、10μm以下のアルミ・シリコン膜で構成し、前記ボンディングワイヤに直径が300μm以上600μm以下のアルミワイヤを用い、前記ボンディングワイヤと前記電極膜との接合面は楕円形をなし、該楕円形の接合面の長軸方向が、前記電極膜表面のストライプ状の凸部の長手方向と直交することを特徴とする半導体装置。
- 前記楕円形の接合面において、前記ボンディングワイヤと前記電極膜とは、前記電極膜表面のストライプ状の凸部ならびに凸部と凸部との間の部分で接合していることを特徴とする請求項1に記載の半導体装置。
- 半導体基板の一方の主面の表面層にウエル領域を形成し、該ウエル領域の表面層にエミッタ領域を形成し、前記ウエル領域と前記エミッタ領域はストライプ構造をなし、前記エミッタ領域に挟まれた前記ウエル領域上および前記半導体基板上にゲート酸化膜を介してゲート電極を形成し、該ゲート電極上に層間絶縁膜を形成し、コンタクトホールを開けた後、前記ウエル領域,前記エミッタ領域,前記層間絶縁膜上であって、前記層間絶縁膜上が凸部となるストライプ状の電極膜を形成し、該ストライプ状の電極膜にボンディングワイヤを超音波ボンディングする半導体装置の製造方法において、
前記電極膜を前記凸部上の厚さが3.5μm以上で、10μm以下となるアルミ・シリコン膜で形成し、
前記ボンディングワイヤに直径が300μm以上600μm以下のアルミワイヤを用い、
前記ボンディングワイヤに、前記ストライプ状の電極の長手方向と直角の方向に超音波振動を与えて、前記ストライプ状の電極の長手方向と直角の方向が長軸なる楕円形の接合面を形成して前記電極膜と前記ボンディングワイヤとを接合することを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008259161A JP2009004819A (ja) | 2008-10-06 | 2008-10-06 | 半導体装置およびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008259161A JP2009004819A (ja) | 2008-10-06 | 2008-10-06 | 半導体装置およびその製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001020103A Division JP4221904B2 (ja) | 2001-01-29 | 2001-01-29 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009004819A true JP2009004819A (ja) | 2009-01-08 |
Family
ID=40320773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008259161A Withdrawn JP2009004819A (ja) | 2008-10-06 | 2008-10-06 | 半導体装置およびその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2009004819A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102208369A (zh) * | 2010-03-31 | 2011-10-05 | 罗姆股份有限公司 | 半导体装置的引线焊接结构及引线焊接方法 |
-
2008
- 2008-10-06 JP JP2008259161A patent/JP2009004819A/ja not_active Withdrawn
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102208369A (zh) * | 2010-03-31 | 2011-10-05 | 罗姆股份有限公司 | 半导体装置的引线焊接结构及引线焊接方法 |
CN102208369B (zh) * | 2010-03-31 | 2014-04-16 | 罗姆股份有限公司 | 半导体装置的引线焊接结构及引线焊接方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4221904B2 (ja) | 半導体装置およびその製造方法 | |
JP4600576B2 (ja) | 半導体装置およびその製造方法 | |
US10096570B2 (en) | Manufacturing method for power semiconductor device, and power semiconductor device | |
JP6398270B2 (ja) | 半導体装置 | |
JPWO2015111691A1 (ja) | 電極端子、電力用半導体装置、および電力用半導体装置の製造方法 | |
JP2007335632A (ja) | 半導体装置 | |
JP6448388B2 (ja) | 電力用半導体装置 | |
US9735100B2 (en) | Semiconductor device and method of manufacturing the same | |
JP6366723B2 (ja) | 半導体装置およびその製造方法 | |
WO2022080063A1 (ja) | 半導体モジュール | |
US20140367842A1 (en) | Power semiconductor device and method of manufacturing the same | |
JP7319295B2 (ja) | 半導体装置 | |
US10497586B2 (en) | Semiconductor device and a method of manufacturing the same | |
WO2011030368A1 (ja) | 半導体装置とその製造方法 | |
JP2009004819A (ja) | 半導体装置およびその製造方法 | |
JP4586508B2 (ja) | 半導体装置およびその製造方法 | |
JP2005251905A (ja) | 半導体装置 | |
JP5840102B2 (ja) | 電力用半導体装置 | |
JP2014120728A (ja) | 半導体装置およびその製造方法 | |
JP2023010131A (ja) | 半導体モジュールおよびその製造方法 | |
JP6844309B2 (ja) | 半導体モジュールの製造方法 | |
JP2003318216A (ja) | ワイヤボンディング方法 | |
JP2009016380A (ja) | 半導体装置及びその製造方法 | |
JPH1032218A (ja) | 半導体装置 | |
JP2020159995A (ja) | 半導体装置、半導体装置の製造方法、及び半導体装置の検査方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20081006 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20081216 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20090219 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20091112 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20110422 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110606 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110614 |
|
A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20110728 |