JP2008519337A5 - - Google Patents

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Publication number
JP2008519337A5
JP2008519337A5 JP2007539443A JP2007539443A JP2008519337A5 JP 2008519337 A5 JP2008519337 A5 JP 2008519337A5 JP 2007539443 A JP2007539443 A JP 2007539443A JP 2007539443 A JP2007539443 A JP 2007539443A JP 2008519337 A5 JP2008519337 A5 JP 2008519337A5
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JP
Japan
Prior art keywords
numbers
calculation
layer
hybrid
logic
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JP2007539443A
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English (en)
Japanese (ja)
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JP5133693B2 (ja
JP2008519337A (ja
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Priority claimed from CN 200410094539 external-priority patent/CN1619487A/zh
Priority claimed from CN 200410094538 external-priority patent/CN1619486A/zh
Priority claimed from CN 200410094537 external-priority patent/CN1619485A/zh
Application filed filed Critical
Priority claimed from PCT/CN2005/001838 external-priority patent/WO2006047952A2/zh
Publication of JP2008519337A publication Critical patent/JP2008519337A/ja
Publication of JP2008519337A5 publication Critical patent/JP2008519337A5/ja
Application granted granted Critical
Publication of JP5133693B2 publication Critical patent/JP5133693B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007539443A 2004-11-08 2005-11-03 ハイブリッド数字繰上げ方式および繰上げラインのデジタルエンジニアリング方法のコンピュータ技術的解法 Expired - Fee Related JP5133693B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
CN 200410094539 CN1619487A (zh) 2004-11-08 2004-11-08 称q进制、进位行数字工程方法和处理器
CN200410094537.5 2004-11-08
CN 200410094538 CN1619486A (zh) 2004-11-08 2004-11-08 偏q进制、进位行数字工程方法和处理器
CN 200410094537 CN1619485A (zh) 2004-11-08 2004-11-08 增q进制、进位行数字工程方法和处理器
CN200410094539.4 2004-11-08
CN200410094538.X 2004-11-08
PCT/CN2005/001838 WO2006047952A2 (fr) 2004-11-08 2005-11-03 Schema technique informatique d'echelle mixte et procede de conception numerique de ligne de transport

Publications (3)

Publication Number Publication Date
JP2008519337A JP2008519337A (ja) 2008-06-05
JP2008519337A5 true JP2008519337A5 (https=) 2008-09-04
JP5133693B2 JP5133693B2 (ja) 2013-01-30

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ID=36319535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007539443A Expired - Fee Related JP5133693B2 (ja) 2004-11-08 2005-11-03 ハイブリッド数字繰上げ方式および繰上げラインのデジタルエンジニアリング方法のコンピュータ技術的解法

Country Status (3)

Country Link
US (1) US8341203B2 (https=)
JP (1) JP5133693B2 (https=)
WO (1) WO2006047952A2 (https=)

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US20070271326A1 (en) * 2004-09-30 2007-11-22 Zhizhong Li Technical Solution to Written Calculations Engineering of the Digital Engineering Method for Hybrid Numeral Carry System and Carry Line
CN106445463A (zh) * 2015-08-13 2017-02-22 李志中 负q进制、进位行计算机和负q进制、进位行数字工程方法
US11764940B2 (en) 2019-01-10 2023-09-19 Duality Technologies, Inc. Secure search of secret data in a semi-trusted environment using homomorphic encryption
KR102243119B1 (ko) * 2019-07-17 2021-04-21 한양대학교 산학협력단 가변 정밀도 양자화 장치 및 방법
CN113984135A (zh) * 2021-10-11 2022-01-28 青岛海尔空调电子有限公司 流量统计方法、装置、计算机可读存储介质及系统

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US4866657A (en) 1986-07-18 1989-09-12 Matsushita Electric Industrial Co., Ltd. Adder circuitry utilizing redundant signed digit operands
JPH02170228A (ja) 1988-12-22 1990-07-02 Fujitsu Ltd 冗長二進加算回路
JPH02207323A (ja) 1989-02-07 1990-08-17 Fujitsu Ltd 冗長２進数加算回路
US5099237A (en) * 1990-07-10 1992-03-24 Research Corporation Technologies, Inc. Method and apparatus for providing maximum rate modulation or compression encoding and decoding
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JPH0773018A (ja) 1993-06-21 1995-03-17 Matsushita Electric Ind Co Ltd 繰り返し算術演算装置
JPH07319668A (ja) 1994-05-27 1995-12-08 Matsushita Electric Ind Co Ltd 冗長２進乗算器および冗長２進ａｌｕ並びにプログラム制御回路
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KR100480765B1 (ko) * 1999-03-26 2005-04-06 삼성전자주식회사 직교 주파수 분할 다중화 전송/수신 시스템 및 이를 이루기위한블록 엔코딩 방법
JP2000293360A (ja) 1999-04-01 2000-10-20 Nec Corp 定数変換処理装置および定数変換処理プログラムを記録した媒体
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US20060048038A1 (en) * 2004-08-27 2006-03-02 Yedidia Jonathan S Compressing signals using serially-concatenated accumulate codes

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