JP2008517467A5 - - Google Patents

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Publication number
JP2008517467A5
JP2008517467A5 JP2007536971A JP2007536971A JP2008517467A5 JP 2008517467 A5 JP2008517467 A5 JP 2008517467A5 JP 2007536971 A JP2007536971 A JP 2007536971A JP 2007536971 A JP2007536971 A JP 2007536971A JP 2008517467 A5 JP2008517467 A5 JP 2008517467A5
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JP
Japan
Prior art keywords
scaling
design layout
problem object
manufacturing information
identifying
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JP2007536971A
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Japanese (ja)
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JP2008517467A (ja
JP4511598B2 (ja
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Priority claimed from US10/711,959 external-priority patent/US7363601B2/en
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Publication of JP2008517467A5 publication Critical patent/JP2008517467A5/ja
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Publication of JP4511598B2 publication Critical patent/JP4511598B2/ja
Anticipated expiration legal-status Critical
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JP2007536971A 2004-10-15 2005-10-14 集積回路設計の層、領域またはセルであるオブジェクトを選択的にスケーリングするための方法、システム、およびプログラム Expired - Fee Related JP4511598B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/711,959 US7363601B2 (en) 2004-10-15 2004-10-15 Integrated circuit selective scaling
PCT/US2005/037145 WO2006044730A2 (en) 2004-10-15 2005-10-14 Integrated circuit selective scaling

Publications (3)

Publication Number Publication Date
JP2008517467A JP2008517467A (ja) 2008-05-22
JP2008517467A5 true JP2008517467A5 (enExample) 2008-10-16
JP4511598B2 JP4511598B2 (ja) 2010-07-28

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ID=36182266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007536971A Expired - Fee Related JP4511598B2 (ja) 2004-10-15 2005-10-14 集積回路設計の層、領域またはセルであるオブジェクトを選択的にスケーリングするための方法、システム、およびプログラム

Country Status (7)

Country Link
US (2) US7363601B2 (enExample)
EP (1) EP1805674A4 (enExample)
JP (1) JP4511598B2 (enExample)
KR (1) KR100962859B1 (enExample)
CN (1) CN100533445C (enExample)
TW (1) TWI353537B (enExample)
WO (1) WO2006044730A2 (enExample)

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US9495503B2 (en) 2011-04-06 2016-11-15 Qualcomm Incorporated Method and apparatus to enable a selective push process during manufacturing to improve performance of a selected circuit of an integrated circuit
US9939488B2 (en) 2011-08-31 2018-04-10 Teseda Corporation Field triage of EOS failures in semiconductor devices
US8907697B2 (en) 2011-08-31 2014-12-09 Teseda Corporation Electrical characterization for a semiconductor device pin
US8631375B2 (en) 2012-04-10 2014-01-14 International Business Machines Corporation Via selection in integrated circuit design
US8627247B1 (en) * 2012-07-11 2014-01-07 International Business Machines Corporation Systems and methods for fixing pin mismatch in layout migration
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US9292649B2 (en) 2013-11-18 2016-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Different scaling ratio in FEOL / MOL/ BEOL
KR102214028B1 (ko) * 2014-09-22 2021-02-09 삼성전자주식회사 가변구조형 스케일러를 포함하는 애플리케이션 프로세서와 이를 포함하는 장치들
CN112255882A (zh) * 2020-10-23 2021-01-22 泉芯集成电路制造(济南)有限公司 集成电路版图微缩方法

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