KR100962859B1 - 집적 회로의 선택적 스케일링 - Google Patents

집적 회로의 선택적 스케일링 Download PDF

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KR100962859B1
KR100962859B1 KR1020077009396A KR20077009396A KR100962859B1 KR 100962859 B1 KR100962859 B1 KR 100962859B1 KR 1020077009396 A KR1020077009396 A KR 1020077009396A KR 20077009396 A KR20077009396 A KR 20077009396A KR 100962859 B1 KR100962859 B1 KR 100962859B1
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scaling
design layout
design
integrated circuit
yield
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KR20070063020A (ko
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후크-루엔 헹
제이슨 디 하이벨러
케빈 더블유 멕킬렌
래니 알 나라얀
스테판 엘 러니언
로버트 에프 월커
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인터내셔널 비지네스 머신즈 코포레이션
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020077009396A 2004-10-15 2005-10-14 집적 회로의 선택적 스케일링 Expired - Fee Related KR100962859B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/711,959 2004-10-15
US10/711,959 US7363601B2 (en) 2004-10-15 2004-10-15 Integrated circuit selective scaling

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KR20070063020A KR20070063020A (ko) 2007-06-18
KR100962859B1 true KR100962859B1 (ko) 2010-06-09

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US (2) US7363601B2 (enExample)
EP (1) EP1805674A4 (enExample)
JP (1) JP4511598B2 (enExample)
KR (1) KR100962859B1 (enExample)
CN (1) CN100533445C (enExample)
TW (1) TWI353537B (enExample)
WO (1) WO2006044730A2 (enExample)

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US7784015B2 (en) * 2005-07-05 2010-08-24 Texas Instruments Incorporated Method for generating a mask layout and constructing an integrated circuit
US20070143234A1 (en) * 2005-12-16 2007-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for intelligent model-based optical proximity correction (OPC)
US7584440B2 (en) * 2006-10-12 2009-09-01 Cadence Design Systems, Inc. Method and system for tuning a circuit
US7783995B2 (en) * 2007-03-08 2010-08-24 International Business Machines Corporation System and method for circuit design scaling
US7568173B2 (en) * 2007-06-14 2009-07-28 International Business Machines Corporation Independent migration of hierarchical designs with methods of finding and fixing opens during migration
US8042070B2 (en) 2007-10-23 2011-10-18 International Business Machines Corporation Methods and system for analysis and management of parametric yield
US8671367B2 (en) * 2008-06-25 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design in optical shrink technology node
US8051401B2 (en) * 2008-10-15 2011-11-01 Arm Limited Post-routing power supply modification for an integrated circuit
US8656332B2 (en) * 2009-02-26 2014-02-18 International Business Machines Corporation Automated critical area allocation in a physical synthesized hierarchical design
US8375349B2 (en) 2009-09-02 2013-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for constant power density scaling
US20110233674A1 (en) * 2010-03-29 2011-09-29 International Business Machines Corporation Design Structure For Dense Layout of Semiconductor Devices
US8539389B2 (en) * 2010-09-27 2013-09-17 Teseda Corporation Correlation of device manufacturing defect data with device electrical test data
US9495503B2 (en) 2011-04-06 2016-11-15 Qualcomm Incorporated Method and apparatus to enable a selective push process during manufacturing to improve performance of a selected circuit of an integrated circuit
US9939488B2 (en) 2011-08-31 2018-04-10 Teseda Corporation Field triage of EOS failures in semiconductor devices
US8907697B2 (en) 2011-08-31 2014-12-09 Teseda Corporation Electrical characterization for a semiconductor device pin
US8631375B2 (en) 2012-04-10 2014-01-14 International Business Machines Corporation Via selection in integrated circuit design
US8627247B1 (en) * 2012-07-11 2014-01-07 International Business Machines Corporation Systems and methods for fixing pin mismatch in layout migration
GB2507754A (en) 2012-11-07 2014-05-14 Ibm Circuit topology scaling rule
US9292649B2 (en) 2013-11-18 2016-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Different scaling ratio in FEOL / MOL/ BEOL
KR102214028B1 (ko) * 2014-09-22 2021-02-09 삼성전자주식회사 가변구조형 스케일러를 포함하는 애플리케이션 프로세서와 이를 포함하는 장치들
CN112255882A (zh) * 2020-10-23 2021-01-22 泉芯集成电路制造(济南)有限公司 集成电路版图微缩方法

Citations (1)

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US6756242B1 (en) 1999-06-21 2004-06-29 Timothy James Regan Method of modifying an integrated circuit

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Patent Citations (1)

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US6756242B1 (en) 1999-06-21 2004-06-29 Timothy James Regan Method of modifying an integrated circuit

Also Published As

Publication number Publication date
JP2008517467A (ja) 2008-05-22
CN101040285A (zh) 2007-09-19
TWI353537B (en) 2011-12-01
KR20070063020A (ko) 2007-06-18
JP4511598B2 (ja) 2010-07-28
EP1805674A2 (en) 2007-07-11
US7363601B2 (en) 2008-04-22
WO2006044730A2 (en) 2006-04-27
US7882463B2 (en) 2011-02-01
EP1805674A4 (en) 2010-08-04
US20060085768A1 (en) 2006-04-20
WO2006044730A3 (en) 2006-08-17
TW200627213A (en) 2006-08-01
CN100533445C (zh) 2009-08-26
US20080148210A1 (en) 2008-06-19

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