JP2008515220A5 - - Google Patents

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Publication number
JP2008515220A5
JP2008515220A5 JP2007534576A JP2007534576A JP2008515220A5 JP 2008515220 A5 JP2008515220 A5 JP 2008515220A5 JP 2007534576 A JP2007534576 A JP 2007534576A JP 2007534576 A JP2007534576 A JP 2007534576A JP 2008515220 A5 JP2008515220 A5 JP 2008515220A5
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JP
Japan
Prior art keywords
layer
frequency power
substrate
high frequency
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2007534576A
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English (en)
Japanese (ja)
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JP2008515220A (ja
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Publication date
Priority claimed from US10/954,104 external-priority patent/US7361608B2/en
Application filed filed Critical
Publication of JP2008515220A publication Critical patent/JP2008515220A/ja
Publication of JP2008515220A5 publication Critical patent/JP2008515220A5/ja
Withdrawn legal-status Critical Current

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JP2007534576A 2004-09-30 2005-08-10 High−k層内に形態を形成する方法及びシステム Withdrawn JP2008515220A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/954,104 US7361608B2 (en) 2004-09-30 2004-09-30 Method and system for forming a feature in a high-k layer
PCT/US2005/028321 WO2006038974A2 (en) 2004-09-30 2005-08-10 A method and system for forming a feature in a high-k layer

Publications (2)

Publication Number Publication Date
JP2008515220A JP2008515220A (ja) 2008-05-08
JP2008515220A5 true JP2008515220A5 (https=) 2008-10-09

Family

ID=36098050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007534576A Withdrawn JP2008515220A (ja) 2004-09-30 2005-08-10 High−k層内に形態を形成する方法及びシステム

Country Status (4)

Country Link
US (1) US7361608B2 (https=)
JP (1) JP2008515220A (https=)
TW (1) TWI288975B (https=)
WO (1) WO2006038974A2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050101147A1 (en) * 2003-11-08 2005-05-12 Advanced Micro Devices, Inc. Method for integrating a high-k gate dielectric in a transistor fabrication process
US20060151846A1 (en) * 2005-01-13 2006-07-13 International Business Machines Corporation Method of forming HfSiN metal for n-FET applications
JP5280670B2 (ja) * 2007-12-07 2013-09-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7834387B2 (en) * 2008-04-10 2010-11-16 International Business Machines Corporation Metal gate compatible flash memory gate stack
JP2009295621A (ja) * 2008-06-02 2009-12-17 Panasonic Corp 半導体装置及びその製造方法
US8975706B2 (en) 2013-08-06 2015-03-10 Intermolecular, Inc. Gate stacks including TaXSiYO for MOSFETS
CN110993567B (zh) * 2019-12-09 2022-08-30 中国科学院微电子研究所 一种半导体结构及其形成方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6727148B1 (en) * 1998-06-30 2004-04-27 Lam Research Corporation ULSI MOS with high dielectric constant gate insulator
US6709715B1 (en) * 1999-06-17 2004-03-23 Applied Materials Inc. Plasma enhanced chemical vapor deposition of copolymer of parylene N and comonomers with various double bonds
US6348420B1 (en) * 1999-12-23 2002-02-19 Asm America, Inc. Situ dielectric stacks
US6492283B2 (en) * 2000-02-22 2002-12-10 Asm Microchemistry Oy Method of forming ultrathin oxide layer
WO2002001622A2 (en) * 2000-06-26 2002-01-03 North Carolina State University Novel non-crystalline oxides for use in microelectronic, optical, and other applications
US6660660B2 (en) * 2000-10-10 2003-12-09 Asm International, Nv. Methods for making a dielectric stack in an integrated circuit
JP2002343790A (ja) * 2001-05-21 2002-11-29 Nec Corp 金属化合物薄膜の気相堆積方法及び半導体装置の製造方法
US6806095B2 (en) * 2002-03-06 2004-10-19 Padmapani C. Nallan Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers
CN100390945C (zh) * 2002-03-29 2008-05-28 东京毅力科创株式会社 基底绝缘膜的形成方法
US6787440B2 (en) * 2002-12-10 2004-09-07 Intel Corporation Method for making a semiconductor device having an ultra-thin high-k gate dielectric
US6750126B1 (en) * 2003-01-08 2004-06-15 Texas Instruments Incorporated Methods for sputter deposition of high-k dielectric films
JP4681886B2 (ja) * 2003-01-17 2011-05-11 富士通セミコンダクター株式会社 半導体装置
US6869542B2 (en) * 2003-03-12 2005-03-22 International Business Machines Corporation Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials
US6696327B1 (en) * 2003-03-18 2004-02-24 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
JP2005039015A (ja) * 2003-07-18 2005-02-10 Hitachi High-Technologies Corp プラズマ処理方法および装置
KR20060054387A (ko) * 2003-08-04 2006-05-22 에이에스엠 아메리카, 인코포레이티드 증착 전 게르마늄 표면 처리 방법
US7303996B2 (en) * 2003-10-01 2007-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics
US7115530B2 (en) * 2003-12-03 2006-10-03 Texas Instruments Incorporated Top surface roughness reduction of high-k dielectric materials using plasma based processes
KR100568516B1 (ko) * 2004-02-24 2006-04-07 삼성전자주식회사 후처리 기술을 사용하여 아날로그 커패시터를 제조하는 방법
US20050205969A1 (en) * 2004-03-19 2005-09-22 Sharp Laboratories Of America, Inc. Charge trap non-volatile memory structure for 2 bits per transistor
JP4919586B2 (ja) * 2004-06-14 2012-04-18 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7323423B2 (en) * 2004-06-30 2008-01-29 Intel Corporation Forming high-k dielectric layers on smooth substrates
US7439113B2 (en) * 2004-07-12 2008-10-21 Intel Corporation Forming dual metal complementary metal oxide semiconductor integrated circuits

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