JP2008506191A5 - - Google Patents

Download PDF

Info

Publication number
JP2008506191A5
JP2008506191A5 JP2007520491A JP2007520491A JP2008506191A5 JP 2008506191 A5 JP2008506191 A5 JP 2008506191A5 JP 2007520491 A JP2007520491 A JP 2007520491A JP 2007520491 A JP2007520491 A JP 2007520491A JP 2008506191 A5 JP2008506191 A5 JP 2008506191A5
Authority
JP
Japan
Prior art keywords
architecture
unit
butterfly
reconfigurable
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007520491A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008506191A (ja
Filing date
Publication date
Priority claimed from US11/071,340 external-priority patent/US7568059B2/en
Application filed filed Critical
Priority claimed from PCT/US2005/024063 external-priority patent/WO2006014528A1/en
Publication of JP2008506191A publication Critical patent/JP2008506191A/ja
Publication of JP2008506191A5 publication Critical patent/JP2008506191A5/ja
Pending legal-status Critical Current

Links

JP2007520491A 2004-07-08 2005-07-08 可変サイズの高速直交変換を実施する方法および機器 Pending JP2008506191A (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US58639104P 2004-07-08 2004-07-08
US58638904P 2004-07-08 2004-07-08
US58635304P 2004-07-08 2004-07-08
US58639004P 2004-07-08 2004-07-08
US60425804P 2004-08-25 2004-08-25
US11/071,340 US7568059B2 (en) 2004-07-08 2005-03-03 Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards
PCT/US2005/024063 WO2006014528A1 (en) 2004-07-08 2005-07-08 A method of and apparatus for implementing fast orthogonal transforms of variable size

Publications (2)

Publication Number Publication Date
JP2008506191A JP2008506191A (ja) 2008-02-28
JP2008506191A5 true JP2008506191A5 (ko) 2008-08-21

Family

ID=35787416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007520491A Pending JP2008506191A (ja) 2004-07-08 2005-07-08 可変サイズの高速直交変換を実施する方法および機器

Country Status (6)

Country Link
EP (1) EP1769391A1 (ko)
JP (1) JP2008506191A (ko)
KR (1) KR101162649B1 (ko)
AU (1) AU2005269896A1 (ko)
CA (1) CA2563450A1 (ko)
WO (1) WO2006014528A1 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009110022A1 (ja) * 2008-03-03 2009-09-11 富士通株式会社 無線通信装置
FR2935819B1 (fr) * 2008-09-05 2010-09-10 Commissariat Energie Atomique Dispositif de traitement numerique pour transformee de fourier et filtrage a reponse impulsionnelle finie
CN102737007B (zh) * 2011-04-07 2015-01-28 中兴通讯股份有限公司 一种支持多个数据单元任意置换的方法和装置
WO2013042249A1 (ja) * 2011-09-22 2013-03-28 富士通株式会社 高速フーリエ変換回路
JPWO2013042249A1 (ja) * 2011-09-22 2015-03-26 富士通株式会社 高速フーリエ変換回路
KR101275087B1 (ko) 2011-10-28 2013-06-17 (주)에프씨아이 오에프디엠 수신기
US9525579B2 (en) 2012-07-18 2016-12-20 Nec Corporation FFT circuit
WO2015011874A1 (ja) 2013-07-23 2015-01-29 日本電気株式会社 デジタルフィルタ装置、デジタルフィルタ処理方法及びデジタルフィルタプログラムが記憶された記憶媒体
US9880975B2 (en) 2013-12-13 2018-01-30 Nec Corporation Digital filter device, digital filter processing method, and storage medium having digital filter program stored thereon
GB2548908B (en) * 2016-04-01 2019-01-30 Advanced Risc Mach Ltd Complex multiply instruction
KR102155770B1 (ko) * 2018-11-27 2020-09-14 한국항공대학교산학협력단 레이다 응용을 위한 이중 완전 셔플 네트워크 기반 가변 푸리에 변환 장치 및 방법
CN113111300B (zh) * 2020-01-13 2022-06-03 上海大学 具有优化资源消耗的定点fft实现系统
JP7317151B2 (ja) * 2020-02-06 2023-07-28 三菱電機株式会社 複素乗算回路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE131948T1 (de) * 1987-08-21 1996-01-15 Commw Scient Ind Res Org Transformationsverarbeitungsschaltung
US5293330A (en) * 1991-11-08 1994-03-08 Communications Satellite Corporation Pipeline processor for mixed-size FFTs
CA2242823A1 (en) * 1995-11-17 1997-05-29 Teracom Svensk Rundradio Improvements in or relating to real-time pipeline fast fourier transform processors
US6003056A (en) * 1997-01-06 1999-12-14 Auslander; Lewis Dimensionless fast fourier transform method and apparatus
JPH11143860A (ja) * 1997-11-07 1999-05-28 Matsushita Electric Ind Co Ltd 直交変換装置
US6061705A (en) * 1998-01-21 2000-05-09 Telefonaktiebolaget Lm Ericsson Power and area efficient fast fourier transform processor
JP2001156644A (ja) * 1999-11-29 2001-06-08 Fujitsu Ltd 直交変換装置
JP3846197B2 (ja) * 2001-01-19 2006-11-15 ソニー株式会社 演算システム
US20030055861A1 (en) * 2001-09-18 2003-03-20 Lai Gary N. Multipler unit in reconfigurable chip
JP4546711B2 (ja) * 2002-10-07 2010-09-15 パナソニック株式会社 通信装置

Similar Documents

Publication Publication Date Title
JP2008506191A5 (ko)
US6366936B1 (en) Pipelined fast fourier transform (FFT) processor having convergent block floating point (CBFP) algorithm
KR101162649B1 (ko) 가변적 크기의 고속 직교 변환을 구현하기 위한 방법 및장치
US20080071848A1 (en) In-Place Radix-2 Butterfly Processor and Method
CN103955447B (zh) 基于dsp芯片的fft加速器
JP4163178B2 (ja) 素因数分解アルゴリズムを用いる最適化された離散フーリエ変換方法および装置
KR20060061796A (ko) 리코드 ｒａｄｉｘ-2 파이프라인 ＦＦＴ 프로세서
US6317770B1 (en) High speed digital signal processor
CN109783766A (zh) 一种基2算法的快速傅里叶变换硬件设计方法
KR20110081971A (ko) 이산 푸리에 변환 계수의 행렬을 계산하는 방법 및 장치
KR20090127462A (ko) Ｆｆｔ/ｉｆｆｔ 연산코어
US20100128818A1 (en) Fft processor
CN117973443B (zh) 神经网络加速方法及装置、加速器、存储介质
Chinnapalanichamy et al. Serial and interleaved architectures for computing real FFT
US7653676B2 (en) Efficient mapping of FFT to a reconfigurable parallel and pipeline data flow machine
Singh et al. Design of radix 2 butterfly structure using vedic multiplier and CLA on xilinx
Cheng et al. Low-cost fast VLSI algorithm for discrete Fourier transform
US6728742B1 (en) Data storage patterns for fast fourier transforms
KR20220017638A (ko) 실수값을 입력으로 하는 고속푸리에 변환장치 및 방법
CN110750249B (zh) 一种快速傅里叶变换代码的生成方法及装置
CN115204373A (zh) 一种卷积神经网络的快速卷积及缓存模式的设计方法
Malashri et al. Low power and memory efficient FFT architecture using modified CORDIC algorithm
Nikara et al. Discrete cosine and sine transforms—regular algorithms and pipeline architectures
TW201724089A (zh) 具有滑動式二階遞迴傅立葉轉換的頻域適應性濾波系統
Ranganathan et al. Efficient hardware implementation of scalable FFT using configurable Radix-4/2