JP2008311347A - 半導体モジュール及びその製造方法 - Google Patents

半導体モジュール及びその製造方法 Download PDF

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Publication number
JP2008311347A
JP2008311347A JP2007156303A JP2007156303A JP2008311347A JP 2008311347 A JP2008311347 A JP 2008311347A JP 2007156303 A JP2007156303 A JP 2007156303A JP 2007156303 A JP2007156303 A JP 2007156303A JP 2008311347 A JP2008311347 A JP 2008311347A
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Japan
Prior art keywords
interposer
semiconductor chip
tape substrate
semiconductor module
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
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JP2007156303A
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English (en)
Japanese (ja)
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JP2008311347A5 (https=
Inventor
Yoshihide Nishiyama
佳秀 西山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
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Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2007156303A priority Critical patent/JP2008311347A/ja
Publication of JP2008311347A publication Critical patent/JP2008311347A/ja
Publication of JP2008311347A5 publication Critical patent/JP2008311347A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
JP2007156303A 2007-06-13 2007-06-13 半導体モジュール及びその製造方法 Withdrawn JP2008311347A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007156303A JP2008311347A (ja) 2007-06-13 2007-06-13 半導体モジュール及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007156303A JP2008311347A (ja) 2007-06-13 2007-06-13 半導体モジュール及びその製造方法

Publications (2)

Publication Number Publication Date
JP2008311347A true JP2008311347A (ja) 2008-12-25
JP2008311347A5 JP2008311347A5 (https=) 2010-07-22

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ID=40238719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007156303A Withdrawn JP2008311347A (ja) 2007-06-13 2007-06-13 半導体モジュール及びその製造方法

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JP (1) JP2008311347A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012129555A (ja) * 2009-01-20 2012-07-05 Altera Corp 挿入層上に配置されたコンデンサーを有するｉｃパッケージ
US9160048B2 (en) 2012-06-04 2015-10-13 Fujitsu Limited Electronic device with terminal circuits

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012129555A (ja) * 2009-01-20 2012-07-05 Altera Corp 挿入層上に配置されたコンデンサーを有するｉｃパッケージ
JP2012518893A (ja) * 2009-01-20 2012-08-16 アルテラ コーポレイション 挿入層上に配置されたコンデンサーを有するｉｃパッケージ
CN102362347B (zh) * 2009-01-20 2016-11-09 阿尔特拉公司 具有布置在插入层上的电容器的集成电路封装件
US9160048B2 (en) 2012-06-04 2015-10-13 Fujitsu Limited Electronic device with terminal circuits

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