JP2008276628A5 - - Google Patents

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Publication number
JP2008276628A5
JP2008276628A5 JP2007121407A JP2007121407A JP2008276628A5 JP 2008276628 A5 JP2008276628 A5 JP 2008276628A5 JP 2007121407 A JP2007121407 A JP 2007121407A JP 2007121407 A JP2007121407 A JP 2007121407A JP 2008276628 A5 JP2008276628 A5 JP 2008276628A5
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JP
Japan
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JP2007121407A
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JP2008276628A (ja
JP5018219B2 (ja
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Priority to JP2007121407A priority Critical patent/JP5018219B2/ja
Priority claimed from JP2007121407A external-priority patent/JP5018219B2/ja
Priority to US12/150,566 priority patent/US8843863B2/en
Publication of JP2008276628A publication Critical patent/JP2008276628A/ja
Publication of JP2008276628A5 publication Critical patent/JP2008276628A5/ja
Application granted granted Critical
Publication of JP5018219B2 publication Critical patent/JP5018219B2/ja
Expired - Fee Related legal-status Critical Current
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JP2007121407A 2007-05-02 2007-05-02 回路最適化情報管理装置およびその方法、並びにプログラム Expired - Fee Related JP5018219B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007121407A JP5018219B2 (ja) 2007-05-02 2007-05-02 回路最適化情報管理装置およびその方法、並びにプログラム
US12/150,566 US8843863B2 (en) 2007-05-02 2008-04-29 Apparatus, method and computer program for managing circuit optimization information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007121407A JP5018219B2 (ja) 2007-05-02 2007-05-02 回路最適化情報管理装置およびその方法、並びにプログラム

Publications (3)

Publication Number Publication Date
JP2008276628A JP2008276628A (ja) 2008-11-13
JP2008276628A5 true JP2008276628A5 (ja) 2010-05-06
JP5018219B2 JP5018219B2 (ja) 2012-09-05

Family

ID=40054484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007121407A Expired - Fee Related JP5018219B2 (ja) 2007-05-02 2007-05-02 回路最適化情報管理装置およびその方法、並びにプログラム

Country Status (2)

Country Link
US (1) US8843863B2 (ja)
JP (1) JP5018219B2 (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101037882B1 (ko) * 2007-03-06 2011-05-31 가부시키가이샤 시마쓰세사쿠쇼 에지 평가 방법, 에지 검출 방법, 화상 보정 방법, 및 화상 처리 시스템
JP5310378B2 (ja) * 2009-08-20 2013-10-09 株式会社リコー テストベンチの作成方法、テストベンチ作成装置
US8887083B2 (en) * 2010-01-27 2014-11-11 Synopsys, Inc. Generating equations based on user intent
JP5991184B2 (ja) * 2012-12-18 2016-09-14 富士通株式会社 設計支援方法、設計支援装置、および設計支援プログラム
US9310433B2 (en) 2014-04-18 2016-04-12 Breker Verification Systems Testing SOC with portable scenario models and at different levels
US9728278B2 (en) 2014-10-24 2017-08-08 Micron Technology, Inc. Threshold voltage margin analysis
CN105843998B (zh) * 2016-03-18 2019-03-05 石河子大学 固-固分离水力旋流器参数的数值模拟优化方法
US11216605B2 (en) 2019-09-17 2022-01-04 S3 Fuzion, Inc. Interactive system for guiding electronics design and assembly
CN113392610B (zh) * 2021-08-18 2021-11-05 苏州贝克微电子有限公司 一种用于大规模集成电路瞬态分析的仿真优化方法及装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0554094A (ja) * 1991-08-23 1993-03-05 Mitsubishi Electric Corp 回路シミユレーシヨン装置
JPH05174092A (ja) * 1991-12-25 1993-07-13 Toshiba Corp 回路設計支援装置
JPH0766294A (ja) * 1993-08-26 1995-03-10 Sony Corp 集積回路の自動設計装置
US5953519A (en) * 1995-06-12 1999-09-14 Fura; David A. Method and system for generating electronic hardware simulation models
US6785873B1 (en) * 1997-05-02 2004-08-31 Axis Systems, Inc. Emulation system with multiple asynchronous clocks
US6651225B1 (en) * 1997-05-02 2003-11-18 Axis Systems, Inc. Dynamic evaluation logic system and method
US6389379B1 (en) * 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
JPH10312405A (ja) * 1997-05-13 1998-11-24 N Ii C Tele Net Works Kk ゲートアレイ設計シミュレータ
JPH1185822A (ja) 1997-09-04 1999-03-30 Hitachi Ltd 回路設計支援方法及び装置並びに回路設計支援プログラムを記憶した記憶媒体
US20060117274A1 (en) * 1998-08-31 2006-06-01 Tseng Ping-Sheng Behavior processor system and method
US7076415B1 (en) * 1998-12-17 2006-07-11 Cadence Design Systems, Inc. System for mixed signal synthesis
JP2002324097A (ja) * 2001-04-25 2002-11-08 Hitachi Ltd Ｃｍｏｓオペアンプの設計システムおよび設計方法
JP2005055960A (ja) * 2003-08-05 2005-03-03 Renesas Technology Corp 回路設計情報の記録媒体
JP2006178775A (ja) * 2004-12-22 2006-07-06 Canon Inc 検証環境作成装置及びその処理方法
JP2007213232A (ja) * 2006-02-08 2007-08-23 Canon Inc 設計支援システム及びドキュメント生成方法

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