JP2008270443A - Multilayer wiring board and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board which has a thinned semiconductor element maintaining planarity and is suitable to obtain an easily assembled thinned structure, and to provide a manufacturing method thereof. <P>SOLUTION: The multilayer wiring board has a structure in which a semiconductor element 3 is bonded between first and second substrate materials 1 and 2 which are face-to-face disposed. The first substrate material 1 is provided with a wiring board having a wiring layer 1b formed on one surface of an insulating substrate 1a, and a conductive paste-made through electrode 1c piercing through the insulating substrate and having one end connected to the wiring layer and the other end exposed to the other surface of the insulating substrate. The semiconductor element 3 is provided with an electrode pad 3b formed on one surface of the semiconductor substrate 3a, a protective insulating film 3c having a contact hole, a re-wiring layer 3e formed thereon and connected to the electrode pad, and a first insulating film 3d, 3f for forming the re-wiring layer, and a second insulating film 3h formed on the other surface of the semiconductor substrate. The other end of the through electrode 1c is connected to the re-wiring layer 3e. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multilayer wiring board and a method for manufacturing the same, and more particularly to a multilayer wiring board suitable for reducing the thickness of a built-in semiconductor element and package substrate and a method for manufacturing the same.

  In the printed circuit board field, a package substrate for electrically connecting an element and an external circuit or device is used to transmit a signal or supply power to an element manufactured by a wafer process such as a semiconductor IC / LSI element. ing. A conventional package substrate has been used in which an individualized IC chip is mounted on a circuit substrate larger than the IC chip on which the rewiring layer is formed and wire-bonded. With the recent increase in the number of functions of portable electronic devices, further miniaturization of semiconductor devices is required, and the demand for higher integration of IC / LSI has been focused on miniaturization of packages. .

  Under such circumstances, in recent years, a wafer level chip scale package (WLCSP) constituted only by a built-up method has been developed as an ultimate small package. This WLCSP is a method of building up wiring directly on an IC using a Si wafer as a base, and the package size is minimized to the same extent as the IC chip size. However, since the number of terminals that can be arranged on the package is restricted by the rule of the terminal pitch of the mounting board, the application of WLCSP is limited to an element having a small number of pins.

  As a technique for solving the restriction of WLCSP, for example, a package substrate technique called EWLP (Embedded Wafer Level Package) as disclosed in Patent Document 1 is known. However, this EWLP uses a built-up method based on repeated processes such as a resist mask and plating, which requires a large number of processes and a high manufacturing cost. There is a problem that a large amount of heat history is applied to the insulating substrate resin layer, and the resin is liable to deteriorate.

  On the other hand, as seen in Patent Document 2, a circuit wiring layer and an adhesive layer are provided on both surfaces of an insulating substrate, and a large number of wiring substrates are provided with through electrodes made of conductive paste serving as interlayer conductive vias. There is a technique for obtaining a multilayer wiring board structure by batch-bonding the wiring boards by thermocompression bonding.

  The present inventors have developed a package-type wiring board capable of incorporating components using such a conductive paste through electrode and a batch thermocompression bonding technique. An example of the developed technology is schematically illustrated in FIG.

  In this conventional package type wiring board, the upper wiring board 81 has an insulating substrate 81a, a circuit wiring layer 81b on the upper surface thereof, and a through electrode 81c made of a conductive paste that penetrates the insulating substrate 81a. The lower wiring substrate 82 includes an insulating substrate 82a and a circuit wiring layer 82b on the lower surface thereof. The semiconductor element 83 between the upper and lower wiring boards 81 and 82 is electrically connected to the wiring layer 81b through the through electrode 81c and embedded in an adhesive layer 84 that bonds the wiring boards.

  The semiconductor element 83 is formed by forming a large number of element regions corresponding to the semiconductor element 83 on the upper surface of a large-area semiconductor wafer by selective diffusion technology, etc., and polishing the back surface of the wafer to thin the wafer. Then, it is diced and taken out in a plurality of pieces. This wafer thinning is as important as the market demand for package substrate thinning.

  The semiconductor element 83 includes a semiconductor substrate 83a thinned by polishing the back surface of the wafer, an electrode pad 83b formed on a part of the upper surface, and an electrode pad 83b attached to the upper surface of the semiconductor substrate 83a. An inorganic insulating film 83c made of silicon oxide or silicon nitride having contact holes is provided. A first organic insulating film 83d that forms a contact hole for the pad 83b is formed on the surface of the insulating film 83c. A rewiring layer 83e is formed on the pad 83b and the organic insulating film 83d with a pattern matching the wiring layer 81b of the upper wiring substrate 81 by, for example, a semi-additive method. Further, a second organic insulating film 83f having a contact hole corresponding to a part of the rewiring layer 83e is deposited on the first organic insulating film 83d. The organic insulating films 83f and 83d are left to be baked after being subjected to photolithography processing by spin coating a liquid photosensitive polyimide precursor in patterning the rewiring layer 83e and forming contact holes. Thus, it is formed on the upper surface of the semiconductor substrate 83a.

  By the way, although an assembly process diagram of the package substrate incorporating the semiconductor element 83 is omitted, in this assembly process, each semiconductor element 83 picked up one by one by the vacuum chuck of the mounter equipment is re-wired. The layer 83e is temporarily fixed to the upper wiring substrate 81 with an adhesive layer material in a state where the layer 83e is pressed against the through electrode 81c (see FIG. 8). Thereafter, the upper wiring substrate 81 with the semiconductor element 83 is aligned and laminated on the lower wiring substrate 82 with the adhesive layer 84 interposed therebetween, and the device is subjected to collective thermocompression bonding in a direction sandwiching the laminated body. A built-in package substrate is formed.

  In the prior art as described above, the first and second organic insulating films 83d and 83f may have a role of a buffer layer or the like for patterning of the redistribution layer and external pressing force. In order to cause curing shrinkage during the formation process, tensile stress is generated on the upper surface side of the semiconductor substrate 83a. Therefore, if the semiconductor substrate 83a is sufficiently thick, it can maintain flatness against the tensile stress. However, if the semiconductor substrate 83a is thinned, the semiconductor substrate 83a cannot withstand the tensile stress and easily causes chip warpage.

If there is such a chip warp, the vacuum chuck cannot attract (pick up) the element during the package substrate assembling process, which may increase the number of cases that hinder the mounting operation. Even if it can be picked up, when the semiconductor element 83 is positioned and pressed against the through electrode 81c and mounted as described above, there is a possibility that the alignment accuracy may be lowered or the semiconductor element 83 may be broken by the pressing force. is there. As described above, it is difficult to obtain both a thin semiconductor device and a package substrate and a reliable and stable mounting operation.
Japanese Patent Laid-Open No. 2004-95836 Japanese Patent Laid-Open No. 2003-318546

  The present invention solves the above-mentioned conventional problems, and is particularly suitable for obtaining a thin package structure that incorporates a thin semiconductor element capable of maintaining flatness and is easy to assemble. An object of the present invention is to provide a wiring board and a manufacturing method thereof.

  The present invention according to claim 1 is a multilayer wiring board in which a semiconductor element is embedded and sealed between a first substrate material and a second substrate material that are arranged facing each other, wherein the first substrate material is A wiring substrate having a wiring layer formed on one surface of the insulating substrate, and a conductive paste that penetrates the insulating substrate, has one end surface connected to the wiring layer, and the other end surface exposed on the other surface of the insulating substrate. The semiconductor element includes an electrode pad formed on one surface of a semiconductor substrate, a protective insulating film having a contact hole for the electrode pad, and a protective insulating film formed on the protective insulating film. A re-wiring layer connected thereto; a first insulating film for forming the re-wiring layer; and a second insulating film formed on the other surface of the semiconductor substrate, the other end surface of the through electrode being the re-wiring It is connected to the layers.

  According to a second aspect of the present invention, in the laminated wiring board according to the first aspect, the first insulating film and the second insulating film are formed using the same kind of organic resin material. It is characterized by.

  According to a third aspect of the present invention, in the multilayer wiring board according to the first or second aspect, the first substrate material includes a plurality of wiring boards each having a wiring layer on one surface of the insulating substrate. Each of the wiring substrates is provided with a through electrode made of a conductive paste that is connected to a corresponding wiring layer and penetrates the insulating substrate, and the through electrode of the wiring substrate on the semiconductor element side Is connected to the rewiring layer of the semiconductor element, and the through electrode of another wiring board separated from the semiconductor element is electrically connected to the wiring layer of the adjacent wiring board.

  According to a fourth aspect of the present invention, in the multilayer wiring board according to any one of the first to third aspects, an adhesive layer is formed on the other surface of the insulating substrate, and the penetration The electrode penetrates the insulating substrate and the adhesive layer, and the semiconductor element is embedded in the adhesive layer.

  According to a fifth aspect of the present invention, in the multilayer wiring board according to any one of the first to fourth aspects, a third substrate is provided between the first substrate material and the second substrate material. A plate material is disposed, and the third substrate material is formed of a film-like spacer having an opening into which the semiconductor element is inserted, and an adhesive layer material is filled between the first to third substrate materials and the opening. It is characterized by.

  According to a sixth aspect of the present invention, in the multilayer wiring board according to any one of the first to fourth aspects, a third substrate is provided between the first substrate material and the second substrate material. A plate material is disposed, and the third substrate material is an intermediate wiring substrate having a wiring layer on at least one surface of an insulating substrate, has an opening into which the semiconductor element is inserted, and the first to third substrates An adhesive layer material is filled between the plate materials and in the opening.

  According to a seventh aspect of the present invention, in the multilayer wiring board according to any one of the first to sixth aspects, the second substrate material is formed on at least one surface of the insulating substrate. A wiring board having a wiring layer, a through electrode made of a conductive paste provided through the insulating substrate and connected to the wiring layer, and at least partially on a surface of the insulating substrate on the first substrate material side It is characterized by comprising an adhesive layer provided.

The method for manufacturing a multilayer wiring board according to claim 8 includes: (A) a protective insulating film having an electrode pad formed on one surface of a semiconductor substrate and a contact hole for the electrode pad; and the protective insulating film A semiconductor device comprising: a redistribution layer formed on and connected to the electrode pad; a first insulation film for forming the redistribution layer; and a second insulation film formed on the other surface of the semiconductor substrate. (B) forming a wiring substrate by patterning a wiring layer on one surface of the insulating substrate to create a first substrate material; (C) forming the wiring substrate on the other surface of the insulating substrate; Forming a bonding layer on the surface; and (D) forming a through hole penetrating the insulating substrate and the bonding layer in a positional relationship corresponding to a part of the rewiring layer of the semiconductor element and the wiring layer. When,
(E) filling the through hole with a conductive paste to form a through electrode having one end surface connected to the wiring layer and the other end surface exposed on the other surface of the insulating substrate; (F) (G) aligning and connecting the other end surface of the through electrode to the rewiring layer of the semiconductor element, and temporarily bonding the semiconductor element to the adhesive layer to integrate with the first substrate material; ) Providing a second substrate material facing the first substrate material; and (H) aligning and superimposing the semiconductor element integrated with the first substrate material on the second substrate material. And (I) a step of collectively heating and pressing the first substrate material and the second substrate material in an overlapping direction, surrounding the semiconductor element with the adhesive layer, and bonding the first and second substrate materials to each other; It is characterized by providing.

  According to the structure and the manufacturing method of the multilayer wiring board of the present invention, the above-mentioned conventional problems are solved, and the thinned semiconductor element which can maintain the flatness and incorporate the thinned semiconductor element can be thinned easily. The package structure can be obtained.

  Hereinafter, a first embodiment of a multilayer wiring board according to the present invention will be described with reference to FIG.

  The first substrate material 1 constituting the upper surface side of the package type laminated wiring substrate is a first insulating substrate 1a made of, for example, a polyimide resin film and a first copper foil patterning formed on one surface (upper surface) thereof. A first wiring board having a wiring layer 1b and a plurality of first through holes made of a conductive paste provided through the first insulating substrate 1a and having one end (upper end) connected to a part of the first wiring layer 1b. An electrode 1c is provided.

  The second substrate material 2 constituting the lower surface side of the package type multilayer wiring board is disposed facing the lower side of the first substrate material 1 and is arranged to face each other, for example, a second insulating substrate 2a made of a polyimide resin film and one of them. A second wiring substrate having a second wiring layer 2b made of copper foil patterned on the surface (lower surface), and one end (lower end) of the second wiring layer 2b provided through the second insulating substrate 2a. A plurality of second through electrodes 2c made of a conductive paste connected to the portion are provided.

  The semiconductor element 3 disposed between the first substrate material 1 and the second substrate material 2 at the center of the left and right in the figure is an element region formed on the upper surface portion of a semiconductor substrate 3a made of silicon, for example. And, for example, a semiconductor IC chip provided with circuit wiring (not shown). On the upper surface of the semiconductor substrate 3a, there is an electrode pad 3b connected to the element region and circuit wiring, and a surface protective insulating film 3c made of an inorganic insulator made of silicon oxide or silicon nitride having a contact hole for the electrode pad 3b. Is formed.

  A first organic insulating film 3d having a thickness of, for example, 10 μm is formed on the surface of the insulating film 3c to form a contact hole for the pad 3b. On the pad 3b and the organic insulating film 3d, there is a pattern in which a rewiring layer 3e made of, for example, a copper plating layer is aligned with the wiring layer 1b and the through electrode 1c of the upper wiring substrate which is the first substrate material 1. For example, it is formed by a semi-additive method. By the way, the rewiring layer 3e provided on the protective insulating film 3c via the first organic insulating film 3d is rewired with respect to the circuit wiring already formed on the IC chip. be able to.

  Further, on the first organic insulating film 3d, a second organic insulating film 3f is deposited with a thickness of 5 μm, for example, and has a contact hole 3g corresponding to a part of the rewiring layer 3e. ing. Each of the organic insulating films 3d and 3f is formed by, for example, spin-coating a liquid photosensitive polyimide precursor and performing photolithography treatment when patterning or forming contact holes in the rewiring layer 3e. By remaining, it is formed on the upper surface of the semiconductor element 3.

  On the other hand, on the lower surface (back surface) of the semiconductor substrate 3a, that is, the surface opposite to the element region, the back surface organic insulating film 3h is spin-coated with the liquid photosensitive polyimide precursor and baked, for example, 15 μm. It is formed in the thickness.

  In the description of the present invention, the first and second organic insulating films 3d and 3f are expressed as a first insulating film, and the back organic insulating film 3h is a second insulating film as meaning the same category. Sometimes expressed.

  As described above, the first and second insulating films (3d, 3f) and the second insulating film (3h) are formed on the upper and lower surfaces of the semiconductor substrate 3a, respectively. Even if hardening shrinkage occurs in the formation process of the insulating film, the respective chip stresses generated on both surfaces of the semiconductor substrate 3a balance or cancel each other, thereby suppressing the chip warpage of the semiconductor substrate 3a.

  By the way, in order to suppress or prevent the chip warp, the first insulating film (3d, 3f) and the second insulating film (3h) are made of the same kind of material as described above, for example, an organic resin material. It is best to form using. The total thickness of the first insulating films (3d, 3f) and the thickness of the second insulating film (3h) can be adjusted to each other so that the tensile stresses on both surfaces are balanced. Thus, since the semiconductor substrate 3a can maintain flatness without chip warpage, it is possible to further reduce the thickness of the semiconductor substrate 3a and promote the reduction of the thickness of the package substrate. The combination of the materials of the first insulating film (3d, 3f) and the second insulating film (3h) may be variously changed on the assumption that the desired flatness of the semiconductor substrate 3a can be maintained.

  Of the plurality of first through electrodes 1c of the first substrate material 1, two first through electrodes 1c at the left and right central portions in the figure are arranged at a pitch that can face the rewiring layers 3e, respectively. The lower end portions thereof are connected to the surfaces of the rewiring layers 3e through the contact holes 3g, respectively.

  The third substrate material 4 disposed between the first substrate material 1 and the second substrate material 2 is, for example, a wiring layer 4b, 4c made of copper foil, which is patterned on both surfaces of the insulating substrate 4a. The wiring layer 4b is composed of a double-sided wiring type intermediate wiring board having a through-hole type interlayer conductive path 4d between the wiring layers 4b and 4c. And the said 3rd board | substrate material 4 (intermediate wiring board) has the opening part 4e in which the said semiconductor element 3 is inserted. The opening 4e is formed so as to penetrate the insulating substrate 4a with a slightly larger diameter than the outer diameter of the semiconductor element, and to have a shape and size that surrounds the entire circumference of the semiconductor element with a gap. ing.

  The adhesive layer material 5 filled in the gaps between the first to third substrate materials 1, 2, 4 and the opening 4e is formed by bonding these members 1, 2, 4 together. The semiconductor element 3 is embedded and sealed in the adhesive layer material 5 (details of materials and forming methods will be described later).

  The wiring layers 4b and 4c on the upper and lower surfaces of the third substrate material 4 (intermediate wiring substrate) are formed on the through electrodes 1c of the first substrate material 1 and the second substrate material 2 which are opposed to each other at the left and right positions in the drawing. Each is connected to the through electrode 2c.

  In this way, each of the first to third substrate materials 1, 2, and 4 is formed of a circuit wiring board, and the first and second substrate materials 1 and 2 are included in a package type multilayer wiring substrate. For internal circuit elements including semiconductor elements, interlayer conductive vias to the wiring layers 1b and 2b on the upper and lower surfaces of the package can be formed through the through electrodes 1c and 2c. Therefore, the package can be reduced in thickness and size, and can easily cope with an increase in the number of wirings accompanying an increase in the functionality of the semiconductor element and an increase in the number of built-in elements. Further, when each of the insulating substrates having an area that is as wide as possible than the chip area of the semiconductor element 3 is used, the wiring layers of the first to third substrate materials 1, 2, and 4 are arranged in the outer direction of the semiconductor element 3. Therefore, it is easy to cope with the higher functionality and the increase in the number of built-in elements.

  The thickness of the third substrate material 4 is approximately the same as the thickness of the semiconductor element 3 and is parallel to the first and second substrate materials 1 and 2 in a batch thermocompression bonding process to be described later. It can also serve as a spacer for performing adhesion by the adhesive layer material 5 while maintaining the properties.

  By the way, the semiconductor element 3 has various electrode pads according to the number of built-in elements and the number of circuit functions. Therefore, each wiring layer formed on each of the substrate materials 1, 2, 4 corresponding to the type of the semiconductor element 3 to be incorporated has the number of wiring layers, the wiring pitch, the wiring length, etc. according to the type. It can also be referred to as a redistribution layer formed in a defined manner.

  By the way, in the first embodiment of the present invention, the first and second substrate materials 1 and 2 are constituted by so-called single-sided wiring substrates, and the third substrate material 4 is constituted by a double-sided wiring substrate. The two substrate materials 1 and 2 may be appropriately changed such as a double-sided wiring substrate, or the third substrate material 4 may be a single-sided wiring substrate, and each of the substrate materials 1, 2, and 4 is at least one of insulating substrates. A wiring layer may be formed on the surface.

  Although not shown, the third substrate material 4 has a shape having an extended portion obtained by extending the insulating substrate 4a to the outside of the package type multilayer wiring board. By providing an external terminal layer connected to the wiring layer in the package, a structure that can be electrically connected to an external connector or the like can be provided. In this case, the third substrate material 4 functions not only as an intermediate wiring board for circuit configuration in the package, but also as a flat cable having input / output terminals for external circuits such as power supply terminals and electronic devices. Can have.

  Next, the manufacturing method of the said multilayer wiring board in one Embodiment of this invention is demonstrated with reference to FIGS. 2 is a cross-sectional view illustrating the manufacturing process of the semiconductor element 3, FIG. 3 is a cross-sectional view illustrating the manufacturing process of the first substrate material 1, FIG. 4 is a cross-sectional view illustrating the manufacturing process of the third substrate material 4, and FIG. It is sectional drawing for demonstrating the assembly method of this multilayer wiring board.

  First, the manufacturing method of the semiconductor element 3 will be described with reference to FIG. 2. In the step of FIG. 2A, for example, an IC is formed on the upper surface portion of a semiconductor wafer 3A made of silicon by, for example, selective diffusion technology. A large number of unit element regions (not shown) corresponding to the semiconductor elements 3 such as / LSI are formed, and circuit wiring and a plurality of element electrode pads 3b are formed for each element area. Further, a protective insulating film 3c, which is an inorganic insulator made of silicon oxide or silicon nitride, having contact holes for each electrode pad 3b is formed on the upper surface of the wafer 3A.

  Next, as shown in FIG. 2B, a liquid photosensitive polyimide precursor is spin-coated on the surface of the wafer 3A, and contact holes 3i exposing the pads 3b are formed by photolithography, followed by baking. A first organic insulating film 3d having a thickness of 10 μm is formed on the protective insulating film 3c.

  Then, as shown in FIG. 2C, a plurality of 5 μm thick conductor circuits, for example, patterned by a copper plating layer on each electrode pad 3b and the first organic insulating film 3d by a semi-additive method, for example. The rewiring layer 3e is formed.

  Thereafter, as shown in FIG. 2D, a liquid photosensitive polyimide precursor is spin-coated again over the entire upper surface of the wafer 3A, and a part of the surface of each rewiring layer 3e is exposed by photolithography. After forming the contact hole 3g for forming, a second organic insulating film 3f having a thickness of 5 μm is formed by baking. Thus, the organic insulating films 3d and 3f serve as first insulating films for forming the rewiring layers 3e.

  Next, for each unit element region corresponding to the semiconductor element 3, a probing inspection is performed through the rewiring layer 3e to determine whether the electrical characteristics are good or bad. The determination result can be marked on the wafer as necessary to facilitate the discrimination of the quality of the chip.

  Thereafter, in order to obtain a thinned semiconductor substrate 3a, the back surface of the wafer 3A is thinned by a method such as polishing with a grindstone or mechanical or chemical polishing until the total thickness of the chip reaches 85 μm. Shape and process. Then, a liquid photosensitive polyimide precursor is spin-coated on the lower surface (back surface) of the semiconductor substrate 3a, that is, the surface opposite to the element region, and baked to form a second organic insulating film having a thickness of 15 μm. An insulating layer 3h is formed.

  In forming the organic insulating films 3d and 3f, which are the first insulating layers on the upper surface side, and the rear organic insulating film 3h, which is the second insulating layer on the lower surface side, benzocyclobutene (BCB) or other photosensitive resin material is used. Polybenzoxazole (PBO) or the like can be used. Further, the photosensitive resin is not necessarily applied by spin coating, and curtain coating, screen printing, spray coating, or the like may be used. Further, the photosensitive resin is not limited to liquid, and a film-like resin may be laminated. Whichever resin material is used, it is most preferable that the first and second insulating layers 3d, 3f, and 3h are formed on the front and back surfaces of the semiconductor substrate 3a using the same material.

  Thereafter, as shown in FIG. 2E, a plurality of singulated semiconductor elements 3 having a semiconductor substrate 3a thinned by dicing are taken out. The semiconductor element 3 can be applied to various semiconductor products such as a semiconductor IC or LSI, and can include circuit elements such as an inductor, a capacitor, and a resistor in addition to a normal conductive circuit.

  As described above, since the first insulating film (3d, 3f) and the second insulating film (3h) made of the same kind of resin material are formed on both surfaces of the semiconductor substrate 3a, Even if curing shrinkage occurs in the process of forming each insulating film, the tensile stresses generated on both surfaces of the semiconductor substrate 3a are balanced or offset each other. Therefore, since chip warpage of the semiconductor element 3 is suppressed and flatness can be maintained, further reduction in thickness is possible.

Next, the manufacturing method of the 1st board | substrate material 1 is demonstrated with reference to FIG. First, FIG. 3 (a)
In the step shown in FIG. 1, for example, a single-sided copper-clad plate (CCL) in which a wiring material layer 1B made of copper foil is provided on one surface (upper surface) of a flexible first insulating substrate 1a made of a polyimide resin film is prepared. As the first insulating substrate 1a and the wiring material layer 1B, those having thicknesses of 25 μm and 9 μm were used, respectively.

  The CCL is prepared by a so-called casting method in which a polyimide varnish is applied to a copper foil and the varnish is cured, or a copper seeding layer is sputtered on a polyimide film to grow a copper electrolytic plating, In addition, one obtained by bonding a copper foil by rolling or electrolysis with a polyimide film can be used. For the first insulating substrate 1a, a plastic film such as a liquid crystal polymer may be used instead of the polyimide resin.

  In the step shown in FIG. 3B, an etching resist pattern (etching mask) corresponding to a desired circuit pattern is formed on the surface of the wiring material layer 1B by photolithography, and then chemical selective etching is performed on the wiring material layer 1B. By performing, the 1st wiring board which has the 1st wiring layer 1b patterned by the desired circuit was obtained. For the etching, for example, an etchant mainly containing ferric chloride is used, but an etchant mainly containing cupric chloride can also be used.

  In the step shown in FIG. 3C, the adhesive layer 5a and the resin film F are sequentially stacked on the other surface (lower surface) opposite to the first wiring layer 1b of the first insulating substrate 1a and bonded by thermocompression bonding. Match. An epoxy thermosetting resin film adhesive having a thickness of 25 μm was used for the adhesive layer 5a, and a polyimide resin film having a thickness of 25 μm was used for the resin film F. The thermocompression bonding was performed by using a vacuum laminator and pressing with a pressure of 0.3 MPa at a temperature equal to or lower than the curing temperature of the adhesive in an atmosphere under reduced pressure.

  As the material of the adhesive layer 5a, an adhesive such as an acrylic resin or a thermoplastic adhesive represented by thermoplastic polyimide can be used instead of the epoxy thermosetting resin. The adhesive layer 5a may be formed by applying a varnish-like resin adhesive on the lower surface of the first insulating substrate 1a instead of the film material.

  As the resin film F, a plastic film such as PET or PEN may be used instead of polyimide, and a film that can be bonded or peeled off by UV irradiation may be formed on the surface of the adhesive layer 5a.

  Next, in the step shown in FIG. 3D, a via hole having a diameter of 100 μm is formed by drilling the first insulating substrate 1a, the adhesive layer 5a and the resin film F with a YAG laser so as to penetrate from the lower surface side. A plurality of through holes 1d (four places in the figure) are formed. Thereafter, plasma desmear treatment with a mixed gas of CF4 and O2 is performed.

  During the laser processing, a small hole (not shown) having a diameter of about 30 μm may be formed in the central portion corresponding to each through hole 1d in the wiring layer 1b. The through-hole 1d and the small hole can be formed by laser processing using a carbonic acid laser or excimer laser, drilling, or chemical etching, or can be formed by drilling or chemical etching.

  In addition, the plasma desmear process is not limited to CF4 and O2 mixed gas as the type of gas used, and other inert gas such as Ar can be used, and a wet desmear process is applied instead of the dry process. May be.

  In the step shown in FIG. 3E, a plurality of through electrodes 1c are formed by filling each through hole 1d with a conductive paste by screen printing until the space of each through hole 1d is filled. To do. Thereafter, the resin film F is peeled off. As a result, the portion of the other end surface (lower surface) of each through electrode 1c is exposed in a state of projecting to the lower surface side of the adhesive layer 5a with a height corresponding to the thickness dimension of the resin film F. Thus, the resin film F adjusts the protruding height of the through electrode by appropriately selecting the thickness thereof, and when the through electrode 1c and the rewiring layer 3d of the semiconductor element 3 are pressed and connected to each other, The pressing force can be adjusted so as to obtain a low resistance connection and avoidance of element damage.

  In particular, when the small hole communicating with the through hole 1d is formed in the first wiring layer 1b, one end surface (upper side) of the through electrode 1c is the inner surface (lower surface) of the first wiring layer 1b and Engaging with a relatively large area over the inner wall of the small hole, the connection is made even stronger. The first substrate material 1 is formed through the above steps.

  By the way, the conductive paste of the through electrode 1c is selected from the group of at least one kind of low electrical resistance metal particles selected from the group of nickel, silver and copper and the group of tin, bismuth, indium and lead. It comprised at least 1 type of low melting metal particle, and comprised with the paste which mixed the binder component which has an epoxy resin as a main component. Further, by adjusting the viscosity or the like of the binder component, when the through electrode 1c and the rewiring layer 3d are pressed and connected, the connection resistance can be lowered and damage to the element can be reduced. The conductive paste has a metal composition that is easy to be alloyed at a low temperature, such as the curing temperature of the adhesive layer 5a, so that the metal particles can be diffusion bonded to each other or diffusion bonded to the metal of the rewiring layer 3d. By using, it is possible to secure connection reliability equivalent to interlayer connection by bulk metal or plating. In addition, since the said electrically conductive paste is excellent also in heat conductivity, it can also acquire the effect which heat-generates and dissipates generated heat outside.

  By the way, although the manufacturing method of the second substrate material 2 is not shown, one surface of a flexible second insulating substrate 2a made of, for example, a polyimide resin film (in FIG. 1), like the first substrate material 1. A single-sided copper clad plate (CCL) provided with a wiring material layer for the second wiring layer 2b made of copper foil on the lower surface is used. An adhesive layer and a resin film similar to the adhesive layer 5a and the resin film F of the first substrate material 1 are bonded to the other surface (the upper side in FIG. 1) of the second insulating substrate 2a. Further, the patterning of the second wiring layer 2b, the method of forming the through hole and the through electrode 2c, and the materials used for each member are the same as in the case of the first substrate material 1.

  Next, the manufacturing method of the said 3rd board | substrate material 4 is demonstrated with reference to FIG. First, in the step shown in FIG. 4A, for example, a double-sided copper clad plate (CCL) in which wiring material layers 4B and 4C made of copper foil are respectively provided on both sides of an insulating substrate 4a made of a polyimide resin film is prepared. Therefore, as shown in FIG. 4B, a through hole TH penetrating the double-sided CCL is formed by, for example, a drill, and a plasma desmear process using a CF4 and O2 mixed gas is performed.

  Thereafter, as shown in FIG. 4C, copper plating is grown on both surfaces of the double-sided CCL and the inner wall of the through hole TH to form a wiring material layer 4BC. At this time, an interlayer conductive path (via) 4d is formed on the inner wall of the through hole TH.

  Then, as shown in FIG. 4D, circuit patterning is performed on the material layer 4BC on both surfaces of the double-sided CCL by the same method as the formation of the first substrate material 1, and one wiring layer 4b. The other wiring layer 4c is formed on both upper and lower surfaces of the insulating substrate 4a. During the patterning, the central portion 4a1 of the insulating plate 4a is exposed on both surfaces by removing the portion corresponding to the semiconductor element 3 in the material layer 4BC. That is, the wiring layer 4b and the wiring layer 4c are patterned at a pitch so that the semiconductor element 3 after mounting is not in contact.

  Next, as shown in FIG. 4E, an opening 4e that is penetrated by a drill, for example, is formed in the central portion 4a1 of the insulating plate 4a. The opening 4 e has a shape / dimension that is slightly larger than the outer diameter of the semiconductor element 3 so as to surround and surround the outer wall of the semiconductor element 3.

  The through hole TH and the opening 4e can be formed by YAG laser, carbonic acid laser, excimer laser or chemical etching. The plasma desmear process is not limited to CF4 and O2 mixed gas as the type of gas used, but other inert gases such as Ar can be used, and a wet desmear process can be applied instead of a dry process. Also good.

  The first to third substrate materials 1, 2, and 4 are subjected to quality screening as a package assembly part after manufacturing, by quality inspection, as in the case of inspection and selection of semiconductor elements.

  Next, a manufacturing method relating to the assembly of the package type wiring board of the first embodiment will be described with reference to FIG. In addition, about the part which is the same as that of each part shown by FIGS. 1-4, the same referential mark is attached | subjected and the detailed description is abbreviate | omitted.

  First, in the process shown in FIG. 5A, a semiconductor element (chip) 3 corresponding to a non-defective product that has been inspected and selected in the process related to FIG. 2D is prepared. The non-defective chip 3 is aligned with the first substrate material (first wiring board) 1 manufactured in the process shown in FIG. 3E by the semiconductor element chip mounter, and the material of the adhesive layer 5a is obtained. Further, the adhesive paste is temporarily bonded by thermocompression bonding at a temperature equal to or lower than the curing temperature of the conductive paste of the through electrode 1c. Specifically, the rewiring layer 3e of the semiconductor element 3 is temporarily bonded to the through electrode 1c of the first substrate material and the lower surface of the adhesive layer 5a.

  Since the semiconductor element 3 is manufactured with a flat shape as described above, when mounted on the first substrate material 1, the semiconductor element 3 is surely picked up by a vacuum chuck, and the rewiring layer 3d and the through electrode 1c. Are mounted (integrated) securely on the first substrate material 1 in a state where the alignment accuracy is high.

  In the step shown in FIG. 5B, the second substrate material (second wiring substrate) 2 is disposed with the through electrode 2c and the adhesive layer 5b facing upward, and the third substrate material (intermediate) is disposed thereon. The wiring board 4 is aligned and overlapped. At this time, a part of the wiring layer 4c on the lower surface of the third substrate material 2 overlaps the upper end surface of the through electrode 2c at the left and right positions in the drawing.

  Next, the semiconductor element 3 integrated with the first substrate material (first wiring substrate) 1 is inserted in alignment with the opening 4e of the third substrate material 4, and the first substrate material 1 is superposed on the third substrate material 4. At this time, the semiconductor element 3 is arranged so that the entire outer periphery of the semiconductor substrate 3a maintains a gap with the inner wall of the opening 4e and does not contact the wiring layers 4b and 4c of the third substrate material 4. Is done. In addition, the lower end surface of the through electrode 1c at the left and right positions of the first substrate material 1 is opposed to a part of the through electrode 2c of the second substrate material 2, and the wiring layer 4b on the upper surface of the third substrate material 4 is disposed. Overlapping part of In this manner, a stacked body of the first to third substrate materials, the substrate materials 1, 2, 4 and the semiconductor element 3 is configured.

  Then, the laminated body is thermocompression-bonded in a laminating direction in a reduced pressure atmosphere of 1 kPa or less using a vacuum cure press machine, thereby completing a package type wiring board having a multi-layered structure as shown in FIG. In this step, the adhesive layers 5a and 5b of the first and second substrate materials 1 and 2 are plastically flowed by heating and pressurizing, and the openings 4e of the third substrate material 4 and the semiconductor are formed between the substrate materials. The gap between the side periphery of the element 3 and the through hole TH are filled, and the adhesive layer material 5 is formed into a single layer as shown in FIG. As a result, a package adhesive seal in which the semiconductor element 3 is embedded in the adhesive layer material 5 can be easily obtained. At this stage, the conductive paste is hardened and the metal component is alloyed in parallel with the package sealing. As a result, even when each through electrode is pressed between 1c and the rewiring layer 3e of the semiconductor element 3, damage to the element is avoided and a low resistance connection is obtained.

  According to the manufacturing method according to the first embodiment, the first and second substrate materials 1 and 2 use a metal foil-clad wiring substrate material such as a single-sided CCL, and the first and second layers for interlayer connection. The second through electrodes 1c and 2c can be easily formed by printing and filling with a conductive paste. Therefore, compared with the above-described conventional built-up method (see Patent Document 1), the plating process can be eliminated through the entire package assembly process, and the production time and production cost can be greatly reduced.

  In addition, since the first to third substrate materials 1, 2, and 4 are bonded and fixed to each other through the adhesive layers 5a and 5b by the collective heat pressing process, the package substrate laminated structure can be obtained by one press. Compared with the built-up system, the heat history applied to these laminated members and the deterioration of the members can be significantly reduced.

  Furthermore, since the first to third substrate materials 1, 2, 4 and the semiconductor element 3 are manufactured in advance in separate process lines, even if a failure occurs in each assembly member for each manufacturing process, it is a defective product each time. Can be eliminated, and accumulation of yield deterioration can be avoided.

  Next, two other embodiments of the semiconductor element will be described with reference to FIGS. 6 (a) and 6 (b). Here, the same components as those of the semiconductor element 3 shown in FIG. 1 and the like are denoted by the same reference numerals, and detailed description thereof is omitted. That is, in the semiconductor element 30 shown in FIG. 6A, the first organic insulating film 3d in the first embodiment of FIG. 1 is omitted, and the second organic insulating film 3f is placed on the protective insulating film 3c. The first insulating film on the upper surface side of the semiconductor substrate 3a is composed of the organic insulating film 3f. The semiconductor element 31 shown in FIG. 6B is an example in which the second-layer organic insulating film 3f in the first embodiment of FIG. 1 is omitted, and the first insulating film on the upper surface side of the semiconductor substrate 3a is formed. The organic insulating film 3d is used.

  According to each of the other embodiments, by omitting one of the organic insulating films 3d and 3f, the number of steps corresponding to the semiconductor elements 30 and 31 can be reduced. Further, since the thickness and the occupation amount of the organic insulating film on the upper surface side of the semiconductor substrate 3a are reduced, the thickness of the organic insulating film 3h constituting the second insulating film on the lower surface (back surface) side of the semiconductor substrate 3a is reduced. It is also possible to further reduce the thickness of the semiconductor element.

  Next, a second embodiment according to the multilayer wiring board of the present invention will be described with reference to FIG. Here, an example in which the semiconductor element 30 shown in FIG. And about the part which is the same as that of each part shown by FIGS. 1-6, or the same part, the same referential mark is attached | subjected and the detailed description is abbreviate | omitted.

  The first substrate material 1x has a multilayer wiring board structure. That is, the first substrate material 1x is formed by laminating the upper wiring substrate on the lower wiring substrate (semiconductor element 30 side) having the first insulating substrate 1a, the first wiring layer 1b, and the through electrode 1c made of conductive paste. Is formed. The upper wiring substrate includes another wiring layer 1f patterned on the upper surface of another insulating substrate 1d and a plurality of through electrodes 1g made of other conductive paste that penetrates the other insulating substrate 1d (four locations in the figure). It is adhered to the first wiring layer 1b and the first insulating substrate 1a by the adhesive layer 1e.

  Each through electrode 1g has one end surface (upper end) connected to the inner surface of the other wiring layer 1f and the other end surface (lower end) connected to the first wiring layer 1b by thermocompression bonding. As can be seen from FIG. 7, the through-electrodes 1c and 1g are small protrusions each having a convex shape and having a diameter smaller than that of the through-electrode main body portion formed in advance on the corresponding wiring layers 1e and 1f, respectively. The hole is filled and engaged.

  Formation of small holes in the through electrodes 1c and 1g and the wiring layers 1e and 1f having such a shape can be applied to the through electrodes 1c and 2c and the wiring layers 1b and 2b in the first embodiment.

  A solder resist 6 is deposited on the other insulating substrate 1d and the other wiring layer 1f. The solder resist 6 has a plurality of contact holes that expose portions of the other wiring layers 1f corresponding to the through electrodes 1g, and a solder paste is printed on the upper surface of the upper wiring board and reflowed. Thus, a plurality of external terminal electrodes 7 made of ball-shaped solder bumps are formed. The external terminal electrode 7 is not limited to the ball bump, but may adopt another external terminal structure such as a beam lead type according to a connection terminal structure of an electronic device to be mounted.

  The first substrate material 1x can be laminated with two or more layers by further stacking other wiring substrates, and a plurality of desired wiring substrates can be stacked according to the multi-function / high functionality of the semiconductor element 3. By providing such a multilayer wiring board structure, it is possible to freely mount on a highly functional electronic device.

  In this example, the second substrate material 2x is made of a flexible polyimide resin film as a support plate for the first substrate material 1x, the semiconductor element 30, and the like. The second substrate material 2x as a support plate may be formed using an insulating film such as PEN or PET, a rigid glass epoxy resin insulating plate, or a metal plate such as copper foil.

  Further, if the second substrate material 2x is made of a material with good heat conductivity, such as copper foil, it can effectively dissipate not only the role of the support plate but also the heat from the semiconductor element 30 to the outside. The electrical operation of the element 30 can be stabilized. In that case, it is possible to mount even a semiconductor element having a large calorific value, which could not be incorporated in the prior art, and the application range of the package substrate to various semiconductor elements can be expanded.

  The third substrate material 4x is exclusively for the role of a spacer, and is made of, for example, a polyimide resin film having the same thickness as the semiconductor element 30 and having an opening 4e surrounding the side periphery with a gap. . Such a third substrate material 4x suppresses undesired flow deformation of the adhesive layer material when the first substrate material 1x and the second substrate material 2x are thermocompression bonded to each other via the adhesive layer material 5, The parallelism between the plate materials 1x and 2x and the positional accuracy of the semiconductor element 3 can be improved.

  By the way, even if each member is exchanged and combined between the first to third substrate materials 1, 2, 4 of the first embodiment and the first to third substrate materials 1x, 2x, 4x of the second embodiment. Good. For example, in the first embodiment, the first substrate material 1x of the second embodiment is used instead of the first substrate material 1, or the third substrate material 4x is used instead of the third substrate material 4. May be. As described above, by appropriately combining the first to third substrate materials of the first and second embodiments, various types of package-type multilayer wiring boards according to the multi-function / high functionality of the semiconductor element 30 are obtained. Can be provided.

  Further, the technique of a plurality of external terminal electrodes composed of solder resist and solder ball bumps in the second embodiment can be applied to the first embodiment. That is, such a solder resist and a plurality of external terminal electrodes can be formed on the upper surface of the first substrate material 1 and the lower surface of the second substrate material 2 in the first embodiment.

  By the way, in any of the multilayer wiring boards of the first and second embodiments, the third substrate material 4, 4x is omitted, and the first substrate material 1, 1x and the second substrate material 2, 2x are used. It is possible to further reduce the thickness of the package by bonding only with the adhesive layer material 5. This is because, for example, the number of functions of semiconductor elements and the number of electrode pads thereof are relatively small, the chip size and the thickness are small, the number of wiring layers of the first substrate material 1, 1x, the wiring layer pitch, and the wiring This can be carried out when the layer length or the like and the insulating substrate area (size) can be reduced, or when the thickness of the adhesive layer material 5 is sufficiently larger than the thickness of the semiconductor element. Note that the adhesive layer provided in advance on the second substrate materials 2 and 2x is not necessarily provided on the entire surface of the second substrate materials 2 and 2x. For example, the adhesive layer is provided only on the periphery avoiding the portion corresponding to the semiconductor element. Etc., at least partially.

  Moreover, in each said embodiment, the heat dissipation effect of a semiconductor element can be improved by forming good heat conductive layers, such as copper foil, in the bottom face of the said semiconductor element. Further, when the second substrate material 2x is a good heat conductive material, the good heat conductive layer on the bottom surface of the semiconductor element is brought into direct contact with the second substrate material 2x without an adhesive layer. The heat dissipation effect is further improved.

1 is a cross-sectional view showing a multilayer wiring board according to a first embodiment of the present invention. It is a figure for demonstrating the manufacturing method of the semiconductor element which concerns on 1st Embodiment of this invention, (a)-(d) is sectional drawing according to the process. , It is a figure for demonstrating the manufacturing method of the 1st board | substrate material which concerns on 1st Embodiment of this invention, (a)-(e) is sectional drawing according to the process. It is a figure for demonstrating the manufacturing method of the 3rd board | substrate material which concerns on 1st Embodiment of this invention, (a)-(e) is sectional drawing according to the process. It is a figure for demonstrating the assembly method of the multilayer wiring board which concerns on 1st Embodiment of this invention, (a) And (b) is sectional drawing according to the process. It is a figure which shows other embodiment of the semiconductor element concerning this invention about two types, (a) And (b) is sectional drawing of each example. It is sectional drawing which shows the laminated wiring board which concerns on 2nd Embodiment of this invention. It is sectional drawing which shows the principal part of the multilayer wiring board in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1x 1st board | substrate material 1a, 1d, 2a, 4a Insulation board | substrate 1b, 1f, 2b, 4b, 4c, Wiring layer 1c, 1g, 2c, Through electrode 2, 2x 2nd board | substrate material 3, 30, 31 Semiconductor element 3a Semiconductor substrate 3b Electrode pad 3c Protective insulating film 3d, 3f Organic insulating film (first insulating layer)
3e Rewiring layer 3h Back side organic insulating film (second insulating layer)
4, 4x Third substrate material 5 Adhesive layer material 5
1e, 5a, 5b, adhesive layer

Claims (8)

  A laminated wiring board in which a semiconductor element is embedded and bonded and sealed between a first substrate material and a second substrate material arranged facing each other, wherein the first substrate material has a wiring layer on one surface of an insulating substrate. And a through electrode made of a conductive paste that penetrates the insulating substrate, has one end surface connected to the wiring layer, and the other end surface exposed on the other surface of the insulating substrate. A protective insulating film having an electrode pad formed on one surface of a semiconductor substrate and a contact hole for the electrode pad, a rewiring layer formed on the protective insulating film and connected to the electrode pad, and the rewiring A first insulating film for forming a layer; and a second insulating film formed on the other surface of the semiconductor substrate, wherein the other end surface of the through electrode is connected to the rewiring layer. Laminated wiring board.   2. The multilayer wiring board according to claim 1, wherein the first insulating film and the second insulating film are formed using the same kind of organic resin material.   The first substrate material has a multilayer wiring substrate structure in which a plurality of wiring substrates each having a wiring layer on one surface of an insulating substrate is laminated, and each of the wiring substrates is connected to a corresponding wiring layer to form the insulating layer. A through electrode made of a conductive paste penetrating the substrate is provided, and the through electrode of the wiring board on the semiconductor element side is connected to the rewiring layer of the semiconductor element, and the through electrode of another wiring board separated from the semiconductor element The multilayer wiring board according to claim 1, wherein the wiring board is electrically connected to a wiring layer of an adjacent wiring board.   The adhesive layer is formed on the other surface of the insulating substrate, the through electrode penetrates the insulating substrate and the adhesive layer, and the semiconductor element is embedded in the adhesive layer. The laminated wiring board according to any one of claims 3 to 3.   A third substrate material is disposed between the first substrate material and the second substrate material, and the third substrate material comprises a film-like spacer having an opening into which the semiconductor element is inserted. The laminated wiring board according to any one of claims 1 to 4, wherein an adhesive layer material is filled between third substrate materials and in the opening.   A third substrate material is disposed between the first substrate material and the second substrate material, and the third substrate material comprises an intermediate wiring substrate having a wiring layer on at least one surface of an insulating substrate, and the semiconductor element 5. An adhesive layer material is filled between the first to third substrate materials and in the opening. 5. The laminated wiring board according to one claim.   The second substrate material includes a wiring substrate having a wiring layer formed on at least one surface of an insulating substrate, a through electrode made of a conductive paste provided through the insulating substrate and connected to the wiring layer, and The structure according to any one of claims 1 to 6, further comprising an adhesive layer provided at least partially on a surface of the insulating substrate on the first substrate material side. The laminated wiring board described. (A) a protective insulating film having an electrode pad formed on one surface of a semiconductor substrate and a contact hole for the electrode pad; a rewiring layer formed on the protective insulating film and connected to the electrode pad; Providing a semiconductor element comprising a first insulating film for forming a wiring layer and a second insulating film formed on the other surface of the semiconductor substrate;
(B) forming a wiring substrate by patterning a wiring layer on one surface of the insulating substrate to form a first substrate material;
(C) forming an adhesive layer on the other surface of the insulating substrate;
(D) forming a through hole penetrating the insulating substrate and the adhesive layer in a positional relationship corresponding to a part of the rewiring layer of the semiconductor element and the wiring layer;
(E) filling the through hole with a conductive paste to form a through electrode having one end surface connected to the wiring layer and the other end surface exposed on the other surface of the insulating substrate;
(F) a step of aligning and connecting the other end surface of the through electrode to the rewiring layer of the semiconductor element, and temporarily bonding the semiconductor element to the adhesive layer to integrate with the first substrate material; ,
(G) providing a second substrate material facing the first substrate material;
(H) aligning and superimposing the semiconductor element integrated with the first substrate material on the second substrate material;
(I) a step of collectively heating and pressing the first substrate material and the second substrate material in an overlapping direction, surrounding the semiconductor element by the adhesive layer, and bonding the first and second substrate materials;
A method of manufacturing a laminated wiring board, comprising:

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