JP2007129148A - Method of manufacturing electronic component packaging structure - Google Patents

Method of manufacturing electronic component packaging structure Download PDF

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JP2007129148A
JP2007129148A JP2005322356A JP2005322356A JP2007129148A JP 2007129148 A JP2007129148 A JP 2007129148A JP 2005322356 A JP2005322356 A JP 2005322356A JP 2005322356 A JP2005322356 A JP 2005322356A JP 2007129148 A JP2007129148 A JP 2007129148A
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electronic component
insulating layer
viscous liquid
liquid resin
wiring pattern
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JP4593444B2 (en
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Atsushi Oi
淳 大井
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
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    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic component packaging structure which is capable of packaging an electronic component by embedding it in an insulating layer with reliability. <P>SOLUTION: The above manufacturing method comprises processes of forming a viscous liquid resin 14a on a mounted body 10, arranging and temporarily bonding an electronic component 20 onto the viscous liquid resin 14a, of obtaining a first insulating layer 14, by making the viscous liquid resin 14a harden through thermal treatment, to fix the electronic component 20 to the first insulating layer 14, and of forming a second insulating layer 16 that covers the electronic component 20. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は電子部品実装構造体の製造方法に係り、より詳しくは、電子部品が絶縁層に埋設された構造を有する電子部品実装構造体の製造方法に関する。   The present invention relates to a method for manufacturing an electronic component mounting structure, and more particularly to a method for manufacturing an electronic component mounting structure having a structure in which an electronic component is embedded in an insulating layer.

従来、電子部品が絶縁層に埋設された構造を有する電子部品実装構造体がある。このような電子部品実装構造体では、多層配線パターンを備えた回路基板に半導体チップなどが層間絶縁層に埋設された状態で配線パターンに電気接続されて実装されている。   Conventionally, there is an electronic component mounting structure having a structure in which an electronic component is embedded in an insulating layer. In such an electronic component mounting structure, a semiconductor chip or the like is mounted on a circuit board having a multilayer wiring pattern while being electrically connected to the wiring pattern in a state of being embedded in an interlayer insulating layer.

そのような電子部品実装構造体の製造方法としては、特許文献１には、半導体チップの段差を容易に解消するために、回路基板の配線パターンを半導体チップの厚みと同一に形成しておき、配線パターンの間の絶縁層の上に半導体チップを実装した後に、樹脂層で半導体チップを被覆する方法が記載されている。   As a method of manufacturing such an electronic component mounting structure, in Patent Document 1, in order to easily eliminate the step of the semiconductor chip, the wiring pattern of the circuit board is formed to be the same as the thickness of the semiconductor chip, A method is described in which after mounting a semiconductor chip on an insulating layer between wiring patterns, the semiconductor chip is covered with a resin layer.

また、特許文献２には、同じく半導体チップの段差を容易に解消するために、未硬化の第１樹脂層の中に半導体チップを埋め込み、さらに半導体チップを被覆する第２樹脂層を形成した後に、第１、第２樹脂層を硬化させる方法が記載されている。
特開２００４−１６５２７７号公報 特開２００４−２４７７０６号公報 Further, in Patent Document 2, similarly, in order to easily eliminate the step of the semiconductor chip, the semiconductor chip is embedded in the uncured first resin layer, and further, the second resin layer covering the semiconductor chip is formed. A method for curing the first and second resin layers is described.
JP 2004-165277 A Japanese Patent Laid-Open No. 2004-247706

上記した特許文献１では、半導体チップを層間絶縁層とは材料が異なるダイアタッチ材によって回路基板上の絶縁層にフェイスアップで実装している。このため、実装構造体に熱がかかる際に、それらの熱膨張係数の違いに基づく熱応力の発生により、層間絶縁層にクラックが発生したり、半導体チップと配線パターンとのコンタクト不良が発生したりするおそれがあり、信頼性が必ずしも十分とはいえない。   In Patent Document 1 described above, a semiconductor chip is mounted face-up on an insulating layer on a circuit board by a die attach material made of a material different from that of an interlayer insulating layer. For this reason, when heat is applied to the mounting structure, cracks occur in the interlayer insulating layer due to the generation of thermal stress based on the difference in their thermal expansion coefficients, and contact failure between the semiconductor chip and the wiring pattern occurs. The reliability is not always sufficient.

また、半導体チップをフェイスダウンでフリップチップ実装する場合では、層間絶縁層と材料が異なるアンダーフィル材で半導体チップの下側を封止する必要があるので、同様な問題が発生するおそれがある。   Further, when flip-chip mounting the semiconductor chip face down, it is necessary to seal the lower side of the semiconductor chip with an underfill material that is made of a material different from that of the interlayer insulating layer, so that a similar problem may occur.

さらに、上記した特許文献２の方法では、未硬化の樹脂層はある程度の柔軟性を有するものの、半導体チップを比較的高い圧力で樹脂層に押し込む必要があるので、機械強度の弱い半導体チップを使用する場合は、半導体チップにクラックが発生するなどして信頼性が問題になる場合が想定される。   Furthermore, in the method of Patent Document 2 described above, although the uncured resin layer has a certain degree of flexibility, it is necessary to push the semiconductor chip into the resin layer with a relatively high pressure, so a semiconductor chip with low mechanical strength is used. In such a case, it is assumed that reliability may be a problem due to cracks in the semiconductor chip.

本発明は以上の課題を鑑みて創作されたものであり、電子部品を信頼性よく絶縁層に埋設して実装できる電子部品実装構造体の製造方法を提供することを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing an electronic component mounting structure that can embed an electronic component in an insulating layer and mount it with high reliability.

上記課題を解決するため、本発明は電子部品実装構造体の製造方法に係り、被実装体の上に粘性液状樹脂を形成する工程と、前記粘性液状樹脂の上に電子部品を配置して仮接着する工程と、前記粘性液状樹脂を熱処理によって硬化させて第１絶縁層を得ることにより、前記電子部品を前記第１絶縁層に固着する工程と、前記電子部品を被覆する第２絶縁層を形成する工程とを有することを特徴とする。   In order to solve the above-described problems, the present invention relates to a method for manufacturing an electronic component mounting structure, which includes a step of forming a viscous liquid resin on a mounted body, and an electronic component disposed on the viscous liquid resin. A step of bonding, a step of fixing the electronic component to the first insulating layer by curing the viscous liquid resin by a heat treatment to obtain a first insulating layer, and a second insulating layer covering the electronic component. And a step of forming.

本発明では、まず、被実装体の上に粘性液状樹脂（樹脂ワニス）が形成された後に、電子部品（薄型化された半導体チップなど）が粘性液状樹脂の上に配置されて仮接着される。その後に、粘性液状樹脂が熱処理によって硬化して第１絶縁層が形成され、これによって電子部品が第１絶縁層に固着される。さらに、電子部品が第２絶縁層によって被覆されて絶縁層に埋設される。   In the present invention, first, after a viscous liquid resin (resin varnish) is formed on an object to be mounted, an electronic component (such as a thinned semiconductor chip) is placed on the viscous liquid resin and temporarily bonded. . Thereafter, the viscous liquid resin is cured by heat treatment to form the first insulating layer, and thereby the electronic component is fixed to the first insulating layer. Further, the electronic component is covered with the second insulating layer and embedded in the insulating layer.

本発明では、ダイアタッチ材を使用することなく、粘性液状樹脂によって電子部品を接着するようにしたので、粘性液状樹脂（第１絶縁層）と電子部品を被覆する第２絶縁層とを同一の樹脂から形成することが可能になる。このため、電子部品の周りの絶縁層の熱膨張係数を同一に設定することができるので、実装構造体に熱がかかる際に、熱応力による絶縁層のクラックの発生などが防止され、実装構造体の信頼性を向上させることができる。   In the present invention, since the electronic component is bonded with the viscous liquid resin without using a die attach material, the viscous liquid resin (first insulating layer) and the second insulating layer covering the electronic component are made the same. It becomes possible to form from resin. For this reason, since the thermal expansion coefficient of the insulating layer around the electronic component can be set to be the same, when the mounting structure is heated, the occurrence of cracks in the insulating layer due to thermal stress is prevented, and the mounting structure The reliability of the body can be improved.

また、粘性液状樹脂を電子部品の接着層として使用するので、高価な樹脂材料に限定されることなく樹脂材料の選択肢が広がり、低コスト化を図ることができる。   Further, since the viscous liquid resin is used as the adhesive layer of the electronic component, the choice of the resin material is expanded without being limited to the expensive resin material, and the cost can be reduced.

本発明の一つの好適な態様では、被実装体は配線パターンを備えた基板であり、粘性液状樹脂が配線パターンの上に形成される。あるいは、配線パターンを被覆する下地絶縁層を形成しておき、粘性液状樹脂を下地絶縁層の上に形成するようにしてもよい。   In one preferable aspect of the present invention, the mounted body is a substrate provided with a wiring pattern, and a viscous liquid resin is formed on the wiring pattern. Alternatively, a base insulating layer that covers the wiring pattern may be formed, and the viscous liquid resin may be formed on the base insulating layer.

また、電子部品はその接続端子が上側を向いて粘性液状樹脂の上に配置され、絶縁層に形成されたビアホールを介して電子部品の接続端子及び配線パターンに電気接続されるｎ層（ｎは１以上の整数）の配線パターンを形成してもよい。   In addition, the electronic component is arranged on the viscous liquid resin with the connection terminal facing upward, and is electrically connected to the connection terminal and the wiring pattern of the electronic component through a via hole formed in the insulating layer (n is n (An integer greater than or equal to 1) may be formed.

さらには、電子部品のバンプを粘性液状樹脂に押し込んで配線パターンに電気接続できるように接触させて実装してもよい。この態様の場合、粘性液状樹脂がアンダーフィル材として機能し、層間絶縁層と熱膨張係数の異なるアンダーフィル材が残存しなくなる。従って、電子部品をフリップチップ実装する場合であっても、層間絶縁層にクラックが発生するなどの不具合が解消され、実装構造体の信頼性を向上させることができる。   Furthermore, the bumps of the electronic component may be pushed into the viscous liquid resin and mounted so as to be electrically connected to the wiring pattern. In this embodiment, the viscous liquid resin functions as an underfill material, and no underfill material having a thermal expansion coefficient different from that of the interlayer insulating layer remains. Therefore, even when the electronic component is flip-chip mounted, problems such as the occurrence of cracks in the interlayer insulating layer are eliminated, and the reliability of the mounting structure can be improved.

以上説明したように、本発明では、同一樹脂よりなる絶縁層の中に電子部品がダメージを受けることなく埋設されるので、電子部品実装構造体の信頼性を向上させることができる。   As described above, according to the present invention, since the electronic component is embedded in the insulating layer made of the same resin without being damaged, the reliability of the electronic component mounting structure can be improved.

以下、本発明の実施の形態について、添付の図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

（第１の実施の形態）
図１及び図２は本発明の第１実施形態の電子部品実装構造体の製造方法における電子部品を絶縁層に埋設して実装する際の基本プロセスを示す断面図、図３〜図５は同じく電子部品実装構造体の製造方法を示す断面図である。 (First embodiment)
1 and 2 are cross-sectional views showing a basic process for mounting an electronic component embedded in an insulating layer in the method for manufacturing an electronic component mounting structure according to the first embodiment of the present invention, and FIGS. It is sectional drawing which shows the manufacturing method of an electronic component mounting structure.

最初に、本実施形態に係る電子部品を絶縁層に埋設して実装する際の基本プロセスについて説明する。図１（ａ）に示すように、まず、配線パターン１２を備えた基板１０（被実装体）を用意する。その後に、図１（ｂ）に示すように、基板１０上の配線パターン１２の上に粘性液状樹脂（樹脂ワニス）１４ａを形成する。さらに、図１（ｂ）及び（ｃ）に示すように、接続端子２０ａを備えた電子部品２０を用意し、その接続端子２０ａを上側にして電子部品２０を粘性液状樹脂１４ａの上に配置する。このとき、粘性液状樹脂１４ａは粘着性を有するので、電子部品２０はダイアタッチ材を使用することなく粘性液状樹脂１４ａに仮接着される。   First, a basic process when the electronic component according to the present embodiment is embedded in an insulating layer and mounted will be described. As shown in FIG. 1A, first, a substrate 10 (mounted body) provided with a wiring pattern 12 is prepared. Thereafter, as shown in FIG. 1B, a viscous liquid resin (resin varnish) 14 a is formed on the wiring pattern 12 on the substrate 10. Further, as shown in FIGS. 1B and 1C, an electronic component 20 having a connection terminal 20a is prepared, and the electronic component 20 is disposed on the viscous liquid resin 14a with the connection terminal 20a facing upward. . At this time, since the viscous liquid resin 14a has adhesiveness, the electronic component 20 is temporarily bonded to the viscous liquid resin 14a without using a die attach material.

次いで、図１（ｃ）の構造体を熱処理することにより、図２（ａ）に示すように、粘性液状樹脂１４ａを硬化させて第１絶縁層１４を得る。これによって、電子部品２０が第1絶縁層１４に固着される。   Next, the structure shown in FIG. 1C is heat-treated to cure the viscous liquid resin 14a and obtain the first insulating layer 14 as shown in FIG. As a result, the electronic component 20 is fixed to the first insulating layer 14.

続いて、図２（ｂ）に示すように、電子部品２０を被覆する第２絶縁層１６を形成する。これにより、第１絶縁層１４及び第２絶縁層１６によって第１層間絶縁層１８が構成され、電子部品２０が第１層間絶縁層１８の中に埋設される。   Subsequently, as shown in FIG. 2B, a second insulating layer 16 covering the electronic component 20 is formed. Accordingly, the first insulating layer 14 and the second insulating layer 16 constitute the first interlayer insulating layer 18, and the electronic component 20 is embedded in the first interlayer insulating layer 18.

本実施形態に係る電子部品２０の実装方法では、粘性液状樹脂１４ａを電子部品２０の接着層として使用し、全体にわたって同一樹脂材料（熱膨張係数が同一）からなる第１層間絶縁層１８に電子部品を埋設するようにしている。これにより、熱応力の発生が抑えられて第１層間絶縁層１８にクラックが生じるなどの不具合が解消され、実装構造体の信頼性を向上させることができる。   In the mounting method of the electronic component 20 according to the present embodiment, the viscous liquid resin 14a is used as the adhesive layer of the electronic component 20, and the first interlayer insulating layer 18 made of the same resin material (having the same thermal expansion coefficient) is used as the electronic material. I try to embed parts. Thereby, generation | occurrence | production of the crack which the generation | occurrence | production of a thermal stress is suppressed and the 1st interlayer insulation layer 18 produces is eliminated, and the reliability of a mounting structure can be improved.

次に、上述した第１実施形態の基本プロセスに基づいてさらに詳しい実施例について説明する。まず、図３（ａ）に示すように、両面側に第１配線パターン３２をそれぞれ備えたコア基板３０（被実装体）を用意する。コア基板３０はガラスエポキシ樹脂などの絶縁体よりなり、コア基板３０にはそれを貫通するスルーホール３０ａが設けられている。そのスルーホール３０ａ内には導電性ビア３１が設けられており、コア基板３０の両面側の第１配線パターン３２は導電性ビア３１を介して相互接続されている。   Next, a more detailed example will be described based on the basic process of the first embodiment described above. First, as shown in FIG. 3A, a core substrate 30 (a mounted body) having first wiring patterns 32 on both sides is prepared. The core substrate 30 is made of an insulator such as glass epoxy resin, and the core substrate 30 is provided with a through hole 30a penetrating therethrough. Conductive vias 31 are provided in the through holes 30 a, and the first wiring patterns 32 on both sides of the core substrate 30 are interconnected via the conductive vias 31.

その後に、図３（ｂ）に示すように、コア基板３０の上面側の第１配線パターン３２の上に膜厚が０．１〜１０μｍの粘性液状樹脂１４ａを塗布する。粘性液状樹脂１４ａとしては、エポキシ樹脂ワニス又はポリイミド樹脂ワニスなどが使用され、スピンコート法、スプレー法又は印刷などによって形成される。粘性液状樹脂１４ａは、樹脂を溶媒に溶かしたものであり、電子部品を粘性液状樹脂１４ａの上に配置する際に電子部品が粘性液状樹脂１４ａの中に沈み込まない程度の粘度を有するものが好ましい。そのような粘性液状樹脂１４ａの粘度は好適には１００ｃＰ程度である。   Thereafter, as shown in FIG. 3B, a viscous liquid resin 14 a having a film thickness of 0.1 to 10 μm is applied on the first wiring pattern 32 on the upper surface side of the core substrate 30. As the viscous liquid resin 14a, an epoxy resin varnish, a polyimide resin varnish, or the like is used, and the viscous liquid resin 14a is formed by a spin coat method, a spray method, printing, or the like. The viscous liquid resin 14a is obtained by dissolving a resin in a solvent, and has such a viscosity that the electronic component does not sink into the viscous liquid resin 14a when the electronic component is placed on the viscous liquid resin 14a. preferable. The viscosity of such viscous liquid resin 14a is preferably about 100 cP.

粘性液状樹脂１４ａは、コア基板３０の上面側の全面に層状に設けられる。これにより、後述するように、粘性液状樹脂１４ａの上に多層配線を形成する際に積層される配線パターンや絶縁層の平坦性を向上させることができる。   The viscous liquid resin 14 a is provided in layers on the entire upper surface side of the core substrate 30. As a result, as will be described later, it is possible to improve the flatness of the wiring pattern and insulating layer that are laminated when the multilayer wiring is formed on the viscous liquid resin 14a.

次いで、図３（ｃ）に示すように、電子部品の一例として、厚みが１００μｍ以下（好適には１００〜５０μｍ）のチップキャパシタ４０を用意する。チップキャパシタ４０は、シリコン基板４２上に絶縁層（不図示）を介して下部電極４４が形成され、その上に複数の誘電体パターン４６が形成され、さらに複数の誘電体パターン４６の上に上部電極４８がそれぞれ形成されて構成されている。下部電極４４及び上部電極４８の所定部に接続部がそれぞれ画定されている。チップキャパシタ４０の上面側にパッシベーション膜が設けられている場合もある。   Next, as shown in FIG. 3C, a chip capacitor 40 having a thickness of 100 μm or less (preferably 100 to 50 μm) is prepared as an example of an electronic component. In the chip capacitor 40, a lower electrode 44 is formed on a silicon substrate 42 via an insulating layer (not shown), a plurality of dielectric patterns 46 are formed thereon, and an upper portion is formed on the plurality of dielectric patterns 46. Electrodes 48 are formed and configured. Connection portions are defined in predetermined portions of the lower electrode 44 and the upper electrode 48, respectively. In some cases, a passivation film is provided on the upper surface side of the chip capacitor 40.

なお、本実施形態では、電子部品としてチップキャパシタを例示するが、半導体チップなどの各種の電子部品を使用することができる。   In the present embodiment, a chip capacitor is exemplified as the electronic component, but various electronic components such as a semiconductor chip can be used.

そして、素子形成面が上側になるようにチップキャパシタ４０を粘性液状樹脂１４ａの上に配置する。チップキャパシタ４０は、フリップチップボンダやマウンターなどのボンディングツールによって所定の位置に位置合わせされて配置される。   Then, the chip capacitor 40 is disposed on the viscous liquid resin 14a so that the element formation surface is on the upper side. The chip capacitor 40 is arranged in a predetermined position by a bonding tool such as a flip chip bonder or a mounter.

このとき、粘性液状樹脂１４ａは粘着性を有するので、チップキャパシタ４０の背面が粘性液状樹脂１４ａに仮接着される。また、チップキャパシタ４０は、僅かに押圧することで粘性液状樹脂１４ａに容易に仮接着されるので、チップキャパシタ４０の機械強度が弱い場合であってもチップにダメージを与えるおそれがない。   At this time, since the viscous liquid resin 14a has adhesiveness, the back surface of the chip capacitor 40 is temporarily bonded to the viscous liquid resin 14a. Further, since the chip capacitor 40 is easily temporarily bonded to the viscous liquid resin 14a by being slightly pressed, there is no possibility of damaging the chip even when the mechanical strength of the chip capacitor 40 is weak.

続いて、図３（ｃ）の構造体を１８０℃の温度雰囲気で１〜２時間、熱処理することにより、図３（ｄ）に示すように、粘性液状樹脂１４ａを硬化させて第１絶縁層１４を得る。これによって、チップキャパシタ４０が第１絶縁層１４に固着される。   Subsequently, the structural body of FIG. 3C is heat-treated at 180 ° C. for 1 to 2 hours to cure the viscous liquid resin 14a as shown in FIG. Get 14. As a result, the chip capacitor 40 is fixed to the first insulating layer 14.

次いで、図４（ａ）に示すように、チップキャパシタ４０を覆うように半硬化の樹脂フィルムを配置し、真空雰囲気（又は減圧雰囲気）で、半硬化の樹脂フィルムを加熱しながらチップキャパシタ４０側に押圧することにより、チップキャパシタ４０を被覆する第２絶縁層１６を形成する。第２絶縁層１６の材料としては、第１絶縁層１４と熱膨張係数を同一にするために同一の樹脂材料が使用される。   Next, as shown in FIG. 4A, a semi-cured resin film is disposed so as to cover the chip capacitor 40, and the semi-cured resin film is heated in a vacuum atmosphere (or a reduced pressure atmosphere) while facing the chip capacitor 40 side. Is pressed to form the second insulating layer 16 covering the chip capacitor 40. As the material of the second insulating layer 16, the same resin material is used in order to make the thermal expansion coefficient the same as that of the first insulating layer 14.

このようにして、第１、第２絶縁層１４，１６によって第１層間絶縁層１８が構成され、チップキャパシタ４０は全体にわたって同一樹脂材料（熱膨張係数が同一）からなる第１層間絶縁層１８の中に埋設されて実装される。また、粘性液状樹脂１４ａは、硬化することでコア基板３０とチップキャパシタ４０との接着層として機能するので、第１、第２絶縁層１４，１６と材料が異なるダイアタッチ材を特別に使用する必要がない。   Thus, the first and second insulating layers 14 and 16 constitute the first interlayer insulating layer 18, and the chip capacitor 40 is entirely made of the same resin material (having the same thermal expansion coefficient) as the first interlayer insulating layer 18. It is embedded in and mounted. Further, since the viscous liquid resin 14a functions as an adhesive layer between the core substrate 30 and the chip capacitor 40 by being cured, a die attach material different in material from the first and second insulating layers 14 and 16 is specially used. There is no need.

以上のことから、チップキャパシタ４０の周りには異なる材料の絶縁層が存在しないことから、実装構造体に熱がかかる際に、熱膨張係数の違いに基づく熱応力の発生が抑止されるので、第１層間絶縁層１８（第１、第２絶縁層１４，１６）にクラックが発生するなどの不具合が解消される。   From the above, since there are no insulating layers of different materials around the chip capacitor 40, when heat is applied to the mounting structure, the generation of thermal stress based on the difference in thermal expansion coefficient is suppressed. Problems such as the occurrence of cracks in the first interlayer insulating layer 18 (first and second insulating layers 14 and 16) are eliminated.

さらに、コア基板３０の反りの発生を防止するために、コア基板３０の下面側にも第２絶縁層１６と同一の樹脂層を形成して第１層間絶縁層１８とする。なお、コア基板３０の下面側に電子部品を実装するしないに係らず、コア基板３０の下面側の第１配線パターン３２上にも同様な粘性液状樹脂１４ａを形成してもよい。コア基板３０の両面側に粘性液状樹脂１４ａをそれぞれ形成することにより、コア基板３０の両面側においてさらにバランスがとれるようになり、電子部品実装構造体の反りの発生が防止される。   Further, in order to prevent the warpage of the core substrate 30, the same resin layer as the second insulating layer 16 is formed on the lower surface side of the core substrate 30 to form the first interlayer insulating layer 18. Note that the same viscous liquid resin 14 a may be formed on the first wiring pattern 32 on the lower surface side of the core substrate 30 regardless of whether or not electronic components are mounted on the lower surface side of the core substrate 30. By forming the viscous liquid resin 14a on both sides of the core substrate 30 respectively, further balance can be achieved on both sides of the core substrate 30 and the occurrence of warpage of the electronic component mounting structure can be prevented.

次いで、図４（ｂ）に示すように、コア基板３０の上面側の第１層間絶縁層１８をレーザで加工することにより、チップキャパシタ４０の下部電極４４及び上部電極４８の各接続部と第１配線パターン３２とに到達する深さの第１ビアホール１８ｘをそれぞれ形成する。あるいは、レーザの代わりに、フォトリソグラフィ及びエッチング（ＲＩＥ）を使用して第１ビアホール１８ｘを形成してもよい。   Next, as shown in FIG. 4B, the first interlayer insulating layer 18 on the upper surface side of the core substrate 30 is processed with a laser so that each connection portion of the lower electrode 44 and the upper electrode 48 of the chip capacitor 40 and First via holes 18x each having a depth reaching one wiring pattern 32 are formed. Alternatively, the first via hole 18x may be formed using photolithography and etching (RIE) instead of the laser.

さらに、コア基板３０の下面側の第１層間絶縁層１８にも第１配線パターン３２に到達する深さの第１ビアホール１８ｘが形成される。   Further, a first via hole 18 x having a depth reaching the first wiring pattern 32 is also formed in the first interlayer insulating layer 18 on the lower surface side of the core substrate 30.

続いて、図４（ｃ）に示すように、コア基板３０の上面側の第１層間絶縁層１８の上に、第１ビアホール１８ｘを介してチップキャパシタ４０の下部電極４４及び上部電極４８の各接続部と第１配線パターン３２とに接続される第２配線パターン３２ａを形成する。さらに、コア基板３０の下面側にも第１ビアホール１８ｘを介して第１配線パターン３２に接続される第２配線パターン３２ａが第１層間絶縁層１８の上に形成される。   Subsequently, as shown in FIG. 4C, each of the lower electrode 44 and the upper electrode 48 of the chip capacitor 40 is formed on the first interlayer insulating layer 18 on the upper surface side of the core substrate 30 through the first via hole 18x. A second wiring pattern 32 a connected to the connection portion and the first wiring pattern 32 is formed. Further, a second wiring pattern 32 a connected to the first wiring pattern 32 through the first via hole 18 x is also formed on the first interlayer insulating layer 18 on the lower surface side of the core substrate 30.

第２配線パターン３２ａは例えばセミアディティブ法によって形成される。詳しく説明すると、まず、第１層間絶縁層１８上及び第１ビアホール１８ｘの内面にスパッタ法や無電解めっきによりシード層（不図示）を形成する。その後に、第２配線パターン３２ａに対応する部分に開口部が設けられたレジスト膜（不図示）を形成する。次いで、シード層をめっき給電層に利用する電解めっきにより、レジスト膜の開口部に金属層パターン（不図示）を形成する。さらに、レジスト膜を除去した後に、金属層パターンをマスクにしてシード層をエッチングすることにより第２配線パターン３２ａを得る。なお、セミアディティブ法の他に、サブトラクティブ法やフルアディティブ法などを使用してもよい。   The second wiring pattern 32a is formed by, for example, a semi-additive method. More specifically, first, a seed layer (not shown) is formed on the first interlayer insulating layer 18 and on the inner surface of the first via hole 18x by sputtering or electroless plating. Thereafter, a resist film (not shown) having an opening in a portion corresponding to the second wiring pattern 32a is formed. Next, a metal layer pattern (not shown) is formed in the opening of the resist film by electrolytic plating using the seed layer as a plating power feeding layer. Further, after removing the resist film, the second wiring pattern 32a is obtained by etching the seed layer using the metal layer pattern as a mask. In addition to the semi-additive method, a subtractive method or a full additive method may be used.

次いで、図５（ａ）に示すように、上記した方法と同様な方法により、コア基板３０の両面側において、第２配線パターン３２ａ上に第２ビアホール１８ｙが設けられた第２層間絶縁層１８ａをそれぞれ形成した後に、第２ビアホール１８ｙを介して第２配線パターン３２ａに接続される第３配線パターン３２ｂを第２層間絶縁層１８ａ上にそれぞれ形成する。   Next, as shown in FIG. 5A, the second interlayer insulating layer 18a in which the second via hole 18y is provided on the second wiring pattern 32a on the both surface sides of the core substrate 30 by the same method as described above. Then, a third wiring pattern 32b connected to the second wiring pattern 32a through the second via hole 18y is formed on the second interlayer insulating layer 18a.

続いて、図５（ｂ）に示すように、コア基板３０の両面側の第３配線パター３２ｂ上に開口部３４ｘが設けられたソルダレジスト膜３４をそれぞれ形成する。さらに、コア基板３０の両面側のソルダレジスト膜３４の開口部３４ｘ内に露出する第３配線パターン３２ｂ上にＮｉ／Ａｕめっきを施すことにより接続部Ｃをそれぞれ形成する。   Subsequently, as shown in FIG. 5B, solder resist films 34 each having an opening 34 x are formed on the third wiring pattern 32 b on both sides of the core substrate 30. Further, the connection portions C are respectively formed by performing Ni / Au plating on the third wiring patterns 32b exposed in the openings 34x of the solder resist film 34 on both sides of the core substrate 30.

なお、本実施形態では、コア基板３０の両面側に３層の第１〜第３配線パターン３２，３２ａ，３２ｂをそれぞれ積層する形態を例示するが、コア基板３０の両面側にｎ層（ｎは１以上の整数）の配線パターンがそれぞれ形成された形態としてもよい。あるいは、コア基板３０の片面のみに多層配線パターンを形成するようにしてもよい。また、多層回路基板の任意の層に電子部品を内蔵して実装することができる。   In this embodiment, the first to third wiring patterns 32, 32 a, and 32 b of the three layers are respectively stacked on both surfaces of the core substrate 30, but n layers (n (An integer of 1 or more) may be formed. Alternatively, a multilayer wiring pattern may be formed only on one side of the core substrate 30. Also, electronic components can be built in and mounted on any layer of the multilayer circuit board.

以上により、図５（ｂ）に示される第１実施形態の電子部品実装構造体１が得られる。そして、コア基板３０の上面側の第３配線パターン３２ｂの接続部Ｃに半導体チップ（不図示）がフリップチップ接続される。また、コア基板３０の下面側の第３配線パターン３２ｂの接続部Ｃが外部接続用パッドとなる。ＢＧＡ（Ball Grid Array）タイプとする場合は、コア基板３０の下面側の第３配線パターン３２ｂの接続部Ｃにはんだボールや金バンプなどの外部接続端子（不図示）が設けられ、その外部接続端子がマザーボード（配線基板）に接続される。また、ＬＧＡ(Land Grid Array)タイプとする場合は、外部接続端子は省略され、接続部Ｃ自体が外部接続端子となる。   As described above, the electronic component mounting structure 1 according to the first embodiment shown in FIG. 5B is obtained. Then, a semiconductor chip (not shown) is flip-chip connected to the connection portion C of the third wiring pattern 32 b on the upper surface side of the core substrate 30. Further, the connection portion C of the third wiring pattern 32b on the lower surface side of the core substrate 30 serves as an external connection pad. In the case of the BGA (Ball Grid Array) type, external connection terminals (not shown) such as solder balls and gold bumps are provided at the connection portion C of the third wiring pattern 32b on the lower surface side of the core substrate 30, and the external connection is performed. The terminal is connected to the mother board (wiring board). In the case of an LGA (Land Grid Array) type, the external connection terminals are omitted, and the connection portion C itself is an external connection terminal.

以上説明したように、第１実施形態では、第１配線パターン３２を備えたコア基板３０上に接着層として機能する粘性液状樹脂１４ａを形成した後に、チップキャパシタ４０を粘性液状樹脂１４ａの上に配置して仮接着する。その後に、粘性液状樹脂１４ａを熱処理によって硬化させて第１絶縁層１４とすることにより、チップキャパシタ４０を第１絶縁層１４に固着する。さらに、チップキャパシタ４０を被覆する第２絶縁層１６を形成する。これによって、チップキャパシタ４０は第１、第２絶縁層１４，１６から構成される第１層間絶縁層１８の中に埋設される。しかも、第１、第２絶縁層１４，１６として同一の樹脂材料を選択できるので、チップキャパシタ４０は全体にわたって熱膨張係数が同一の第１層間絶縁層１８の中に埋設される。従って、電子部品実装構造体１に熱がかかる際に、熱膨張係数の違いに基づく熱応力の発生が抑止されるので、第１層間絶縁層１８にクラックが発生したり、チップキャパシタ４０と第２配線パターン３２ａとの間でコンタクト不良が発生したりする不具合が解消される。   As described above, in the first embodiment, after the viscous liquid resin 14a functioning as an adhesive layer is formed on the core substrate 30 provided with the first wiring pattern 32, the chip capacitor 40 is placed on the viscous liquid resin 14a. Place and temporarily bond. Thereafter, the viscous liquid resin 14 a is cured by heat treatment to form the first insulating layer 14, thereby fixing the chip capacitor 40 to the first insulating layer 14. Further, the second insulating layer 16 that covers the chip capacitor 40 is formed. As a result, the chip capacitor 40 is embedded in the first interlayer insulating layer 18 composed of the first and second insulating layers 14 and 16. Moreover, since the same resin material can be selected as the first and second insulating layers 14 and 16, the chip capacitor 40 is embedded in the first interlayer insulating layer 18 having the same thermal expansion coefficient throughout. Therefore, when heat is applied to the electronic component mounting structure 1, the generation of thermal stress based on the difference in thermal expansion coefficient is suppressed, so that cracks occur in the first interlayer insulating layer 18, and the chip capacitor 40 and the first The problem that a contact failure occurs between the two wiring patterns 32a is solved.

このように、第１実施形態の電子部品実装構造体１では、信頼性試験時や実際に使用する際に熱がかかるとしても、熱応力によるクラックやコンタクト不良の発生が防止され、信頼性を向上させることができる。   As described above, in the electronic component mounting structure 1 according to the first embodiment, even when heat is applied during the reliability test or when actually used, the occurrence of cracks and contact failures due to thermal stress is prevented, and reliability is improved. Can be improved.

さらには、粘性液状樹脂１４ａを接着層として使用することにより、多種多様な樹脂材料の中から樹脂を選択し、電子部品を同一材料の絶縁層に埋設することができるので、高価な樹脂材料に限定されることなく、低コスト化を図ることができる。   Furthermore, by using the viscous liquid resin 14a as an adhesive layer, it is possible to select a resin from a wide variety of resin materials and embed electronic components in an insulating layer of the same material. Without being limited, cost reduction can be achieved.

（第２の実施の形態）
図６及び図７は本発明の第２実施形態の電子部品実装構造体の製造方法における電子部品を絶縁層に埋設して実装する際の基本プロセスを示す断面図、図８〜図１０は同じく電子部品実装構造体の製造方法を示す断面図である。第２実施形態が第１実施形態と異なる点は、基板上の配線パターンの上に下地絶縁層を形成した後に、粘性液状樹脂を形成することにあるので、第１実施形態と同一工程及び同一符号を付した同一要素についてはその詳しい説明を省略する。 (Second Embodiment)
6 and 7 are cross-sectional views showing a basic process when an electronic component is embedded and mounted in an insulating layer in the method for manufacturing an electronic component mounting structure according to the second embodiment of the present invention, and FIGS. It is sectional drawing which shows the manufacturing method of an electronic component mounting structure. The second embodiment is different from the first embodiment in that the viscous liquid resin is formed after forming the base insulating layer on the wiring pattern on the substrate. Detailed description of the same elements with reference numerals will be omitted.

最初に、第２実施形態に係る電子部品を絶縁層に埋設して実装する際の基本プロセスについて説明する。図６（ａ）に示すように、まず、第１実施形態と同様な配線パターン１２を備えた基板１０を用意し、基板１０上の配線パターン１２の上に下地絶縁層１３を形成する。その後に、図６（ｂ）に示すように、下地絶縁層１３の上に、第１実施形態と同様な粘性液状樹脂１４ａを形成する。下地絶縁層１３は粘性液状樹脂１４ａと同一樹脂から形成される。さらに、図６（ｃ）に示すように、電子部品２０の接続端子２０ａを上側にして粘性液状樹脂１４ａ上に電子部品２０を配置して仮接着する。   First, a basic process when the electronic component according to the second embodiment is embedded in an insulating layer and mounted will be described. As shown in FIG. 6A, first, a substrate 10 having a wiring pattern 12 similar to that of the first embodiment is prepared, and a base insulating layer 13 is formed on the wiring pattern 12 on the substrate 10. Thereafter, as shown in FIG. 6B, a viscous liquid resin 14a similar to that of the first embodiment is formed on the base insulating layer 13. The base insulating layer 13 is formed from the same resin as the viscous liquid resin 14a. Further, as shown in FIG. 6C, the electronic component 20 is placed on the viscous liquid resin 14a and temporarily bonded with the connection terminal 20a of the electronic component 20 facing upward.

次いで、第１実施形態と同様に、図６（ｃ）の構造体を熱処理することにより、図７（ａ）に示すように、粘性液状樹脂１４ａを硬化させて第１絶縁層１４を得る。これによって、電子部品２０が第１絶縁層１４に固着される。さらに、図７（ｂ）に示すように、電子部品２０を被覆する第２絶縁層１６を形成する。これにより、下地絶縁層１３、第１絶縁層１４及び第２絶縁層１６によって層間絶縁層１８が構成され、電子部品２０が第１層間絶縁層１８の中に埋設されて実装される。   Next, as in the first embodiment, the structure shown in FIG. 6C is heat-treated to cure the viscous liquid resin 14a and obtain the first insulating layer 14 as shown in FIG. 7A. As a result, the electronic component 20 is fixed to the first insulating layer 14. Further, as shown in FIG. 7B, a second insulating layer 16 that covers the electronic component 20 is formed. Thus, the interlayer insulating layer 18 is constituted by the base insulating layer 13, the first insulating layer 14, and the second insulating layer 16, and the electronic component 20 is embedded and mounted in the first interlayer insulating layer 18.

第２実施形態においても、第１実施形態と同様に、電子部品２０が同一樹脂の第１層間絶縁層１８の中に埋設されるので、熱応力の発生が抑制され、第１層間絶縁層１８にクラックが発生するなどの不具合が解消される。それに加えて、下地絶縁層１３によって配線パターン１２の段差を解消できることから、粘性液状樹脂１４ａの平坦性が向上するので、配線パターン１２の上に粘性液状樹脂１４ａを直接形成する場合（第１実施形態）よりも電子部品２０を密着性よく実装することができる。   Also in the second embodiment, as in the first embodiment, since the electronic component 20 is embedded in the first interlayer insulating layer 18 of the same resin, generation of thermal stress is suppressed, and the first interlayer insulating layer 18 is suppressed. Problems such as cracks are eliminated. In addition, since the level difference of the wiring pattern 12 can be eliminated by the base insulating layer 13, the flatness of the viscous liquid resin 14a is improved. Therefore, when the viscous liquid resin 14a is directly formed on the wiring pattern 12 (first embodiment). The electronic component 20 can be mounted with better adhesion than the configuration.

次に、上述した第２実施形態の基本プロセスに基づいてさらに詳しい実施例について説明する。図８（ａ）に示すように、まず、第１実施形態の図３（ａ）と同様に、両面側に第１配線パターン３２を備えたコア基板３０を用意する。その後に、図８（ｂ）に示すように、コア基板３０の両面側に、第１配線パターン３２を被覆する下地絶縁層１３をそれぞれ形成する。下地絶縁層１３の材料としては、次の工程で形成される粘性液状樹脂と同一材料からなる硬化済み又は半硬化（Ｂ−ステージ）の樹脂が使用される。さらに、図８（ｃ）に示すように、コア基板３０の上面側の下地絶縁層１３の上に、第１実施形態と同様な粘性液状樹脂１４ａを形成する。   Next, more detailed examples will be described based on the basic process of the second embodiment described above. As shown in FIG. 8A, first, as in FIG. 3A of the first embodiment, a core substrate 30 having first wiring patterns 32 on both sides is prepared. After that, as shown in FIG. 8B, the base insulating layer 13 that covers the first wiring pattern 32 is formed on both sides of the core substrate 30. As the material of the base insulating layer 13, a cured or semi-cured (B-stage) resin made of the same material as the viscous liquid resin formed in the next step is used. Further, as shown in FIG. 8C, a viscous liquid resin 14 a similar to that in the first embodiment is formed on the base insulating layer 13 on the upper surface side of the core substrate 30.

次いで、図９（ａ）に示すように、第１実施形態と同様に、粘性液状樹脂１４ａの上にチップキャパシタ４０を配置して仮接着する。さらに、図９（ａ）の構造体を熱処理することにより、図９（ｂ）に示すように、粘性液状樹脂１４ａを硬化させて第１絶縁層１４を得る。これによって、チップキャパシタ４０が第１絶縁層１４に固着される。   Next, as shown in FIG. 9A, as in the first embodiment, the chip capacitor 40 is disposed on the viscous liquid resin 14a and temporarily bonded thereto. Further, by heat-treating the structure of FIG. 9A, the viscous liquid resin 14a is cured to obtain the first insulating layer 14 as shown in FIG. 9B. As a result, the chip capacitor 40 is fixed to the first insulating layer 14.

次いで、図９（ｃ）に示すように、第１実施形態と同様に、キャパシタチップ４０を被覆する第２絶縁層１６を形成する。これにより、下地絶縁層１３、第１絶縁層１４及び第２絶縁層１６によって第１層間絶縁層１８が構成され、チップキャパシタ４０が第１層間絶縁層１８に埋設される。また、コア基板３０の下面側にも第２絶縁層１６が形成され、下地絶縁層１３と第２絶縁層１６とにより第１層間絶縁層１８が構成される。   Next, as shown in FIG. 9C, the second insulating layer 16 that covers the capacitor chip 40 is formed as in the first embodiment. Thus, the first interlayer insulating layer 18 is configured by the base insulating layer 13, the first insulating layer 14, and the second insulating layer 16, and the chip capacitor 40 is embedded in the first interlayer insulating layer 18. The second insulating layer 16 is also formed on the lower surface side of the core substrate 30, and the base insulating layer 13 and the second insulating layer 16 constitute the first interlayer insulating layer 18.

続いて、図１０（ａ）に示すように、第１実施形態と同様に、第１層間絶縁層１８に設けられた第１ビアホール１８ｘを介してチップキャパシタ４０の下部電極４４及び上部電極４８の各接続部と第１配線パターン３２とに接続される第２配線パターン３２ａが第１層間絶縁層１８の上に形成される。また、コア基板３０の下面側にも、第１層間絶縁層１８に設けられた第１ビアホール１８ｘを介して第１配線パターン３２に接続される第２配線パターン３２ａが第１層間絶縁層１８の上に形成される。   Subsequently, as shown in FIG. 10A, as in the first embodiment, the lower electrode 44 and the upper electrode 48 of the chip capacitor 40 are connected via the first via hole 18x provided in the first interlayer insulating layer 18. A second wiring pattern 32 a connected to each connection portion and the first wiring pattern 32 is formed on the first interlayer insulating layer 18. A second wiring pattern 32 a connected to the first wiring pattern 32 through the first via hole 18 x provided in the first interlayer insulating layer 18 is also provided on the lower surface side of the core substrate 30. Formed on top.

続いて、図１０（ｂ）に示すように、第１実施形態と同様に、コア基板３０の両面側に、第２層間絶縁層１８ａに設けられた第２ビアホール１８ｙを介して第２配線パターン３２ａに接続される第３配線パターン３２ｂが第２層間絶縁層１８ｂの上にそれぞれ形成される。さらに、第１実施形態と同様に、コア基板３０の両面側に、第３配線パター３２ｂの上に開口部３４ｘが設けられたソルダレジスト膜３４がそれぞれ形成された後に、ソルダレジスト膜３４の開口部３４に接続部Ｃがそれぞれ形成される。   Subsequently, as shown in FIG. 10B, as in the first embodiment, the second wiring pattern is formed on both sides of the core substrate 30 via the second via holes 18y provided in the second interlayer insulating layer 18a. Third wiring patterns 32b connected to 32a are respectively formed on the second interlayer insulating layer 18b. Further, as in the first embodiment, after the solder resist film 34 having the opening 34x provided on the third wiring pattern 32b is formed on both sides of the core substrate 30, the openings of the solder resist film 34 are formed. Connection portions C are formed in the portions 34, respectively.

以上により、第２実施形態の電子部品実装構造体１ａが得られる。   Thus, the electronic component mounting structure 1a of the second embodiment is obtained.

第２実施形態の電子部品実装構造体１ａは、第１実施形態と同様な効果を奏する。これに加えて、前述したように、第１配線パターン３２が下地絶縁層１３の中に埋め込まれてその段差が吸収されるので、下地絶縁層１３上に形成される粘性液状樹脂１４ａの平坦性が向上し、これによってチップキャパシタ４０を密着性よく実装することができる。   The electronic component mounting structure 1a of the second embodiment has the same effects as those of the first embodiment. In addition, as described above, since the first wiring pattern 32 is embedded in the base insulating layer 13 and the step is absorbed, the flatness of the viscous liquid resin 14a formed on the base insulating layer 13 is increased. As a result, the chip capacitor 40 can be mounted with good adhesion.

（第３の実施の形態）
図１１及び図１２は本発明の第３実施形態の電子部品実装構造体の製造方法を示す断面図である。第３実施形態の特徴は、第１実施形態において電子部品の接続端子（バンプ）を下側にした状態で（フェイスダウン）実装することにある。第１実施形態と同一工程及び同一符号を付した同一要素についてはその詳しい説明を省略する。 (Third embodiment)
11 and 12 are cross-sectional views illustrating a method for manufacturing an electronic component mounting structure according to a third embodiment of the present invention. A feature of the third embodiment is that mounting is performed with the connection terminals (bumps) of the electronic components facing down (face down) in the first embodiment. Detailed descriptions of the same steps and the same elements as those in the first embodiment are omitted.

図１１（ａ）に示すように、まず、第１実施形態と同様な方法により、コア基板３０の上面側の第１配線パターン３２の上に粘性液状樹脂１４ａを形成する。さらに、図１１（ａ）及び（ｂ）に示すように、バンプ５０ａを備えた半導体チップ５０を用意し、半導体チップ５０のバンプ５０ａを下側にした状態で（フェイスダウン）、半導体チップ５０を粘性液状樹脂１４ａに押し込むことにより、半導体チップ５０のバンプ５０ａを第１配線パターン３２に電気接続されるように接触させる。   As shown in FIG. 11A, first, the viscous liquid resin 14a is formed on the first wiring pattern 32 on the upper surface side of the core substrate 30 by the same method as in the first embodiment. Further, as shown in FIGS. 11A and 11B, a semiconductor chip 50 provided with bumps 50a is prepared, and the semiconductor chip 50 is mounted with the bumps 50a of the semiconductor chip 50 facing down (face down). The bump 50a of the semiconductor chip 50 is brought into contact with the first wiring pattern 32 by being pushed into the viscous liquid resin 14a.

次いで、図１１（ｂ）の構造体を熱処理することにより、図１１（ｃ）に示すように、粘性液状樹脂１４ａを硬化させて第１絶縁層１４を得る。これによって、半導体チップ５０は第１絶縁層１４に固着されると共に、その接続端子５０ａが第１配線パターン３２に電気接続される。   Next, the structure shown in FIG. 11B is heat-treated to cure the viscous liquid resin 14a and obtain the first insulating layer 14 as shown in FIG. 11C. As a result, the semiconductor chip 50 is fixed to the first insulating layer 14, and the connection terminal 50 a is electrically connected to the first wiring pattern 32.

その後に、図１２（ａ）に示すように、第１実施形態の図４（ａ）〜図４（ｃ）の工程と同一の工程を遂行することにより、第１、第２絶縁層１４，１６から構成される第１層間絶縁層１８に設けられた第１ビアホール１８ｘを介して第１配線パターン３２に接続される第２配線パターン３２ａが第１層間絶縁層１８上に形成される。このようにして、半導体チップ５０は、第１、第２絶縁層１４，１６から構成される同一樹脂からなる第１層間絶縁層１８に埋設される。   Thereafter, as shown in FIG. 12A, by performing the same steps as those of FIGS. 4A to 4C of the first embodiment, the first and second insulating layers 14, A second wiring pattern 32 a connected to the first wiring pattern 32 through a first via hole 18 x provided in the first interlayer insulating layer 18 composed of 16 is formed on the first interlayer insulating layer 18. In this way, the semiconductor chip 50 is embedded in the first interlayer insulating layer 18 made of the same resin and composed of the first and second insulating layers 14 and 16.

次いで、第１実施形態の図５（ａ）及び（ｂ）の工程と同一の工程を遂行する。これにより、図１２（ｂ）に示すように、コア基板３０の両面側において、第２層間絶縁層１８ａに設けられた第２ビアホール１８ｙを介して第２配線パターン３２ａに接続される第３配線パターン３２ｂが第２層間絶縁層１８ａ上にそれぞれ形成される。さらに、第３配線パターン３２ｂ上に開口部３４ｘが設けられたソルダレジスト膜３４がそれぞれ形成され、その開口部３４ｘに接続部Ｃが形成される。   Next, the same process as the process of FIGS. 5A and 5B of the first embodiment is performed. Thereby, as shown in FIG. 12B, the third wiring connected to the second wiring pattern 32a through the second via hole 18y provided in the second interlayer insulating layer 18a on both sides of the core substrate 30. Patterns 32b are respectively formed on the second interlayer insulating layer 18a. Further, a solder resist film 34 having an opening 34x is formed on the third wiring pattern 32b, and a connection portion C is formed in the opening 34x.

以上により、第３実施形態の電子部品実装構造体１ｂが得られる。   As described above, the electronic component mounting structure 1b of the third embodiment is obtained.

第３実施形態においても、半導体チップ５０が同一樹脂からなる第１層間絶縁層１８に埋設されるので、第１実施形態と同様な効果を奏する。また、半導体チップ５０をフリップチップ実装する際に、粘性液状樹脂１４ａ（第１絶縁層１４）が半導体チップ５０の下側の隙間を充填するアンダーフィル材としても機能するので、層間絶縁層と材料が異なる従来のアンダーフィル材が残存することはなく、この点においても電子部品実装構造体の信頼性を向上させることができる。   Also in the third embodiment, since the semiconductor chip 50 is embedded in the first interlayer insulating layer 18 made of the same resin, the same effects as in the first embodiment can be obtained. In addition, when the semiconductor chip 50 is flip-chip mounted, the viscous liquid resin 14a (first insulating layer 14) also functions as an underfill material that fills the gap below the semiconductor chip 50. However, the conventional underfill material having a different thickness does not remain, and in this respect as well, the reliability of the electronic component mounting structure can be improved.

なお、前述した第１〜第３実施形態では、被実装体として配線パターンを備えた回路基板を使用したが、金属基板などの各種の基板を使用することができる。例えば、金属基板の上に同様な方法で電子部品を絶縁層の中に埋設して実装した後に、金属基板を絶縁層に対して選択的に除去する形態などに適用してもよい。   In the first to third embodiments described above, the circuit board provided with the wiring pattern is used as the mounted body, but various boards such as a metal board can be used. For example, the present invention may be applied to a mode in which an electronic component is embedded in an insulating layer and mounted on a metal substrate in the same manner, and then the metal substrate is selectively removed from the insulating layer.

図１（ａ）〜（ｃ）は本発明の第１実施形態の電子部品実装構造体の製造方法における電子部品を絶縁層に埋設して実装する際の基本プロセスを示す断面図（その１）である。1A to 1C are cross-sectional views showing a basic process for mounting an electronic component embedded in an insulating layer in the method for manufacturing an electronic component mounting structure according to the first embodiment of the present invention (No. 1). It is. 図２（ａ）及び（ｂ）は本発明の第１実施形態の電子部品実装構造体の製造方法における電子部品を絶縁層に埋設して実装する際の基本プロセスを示す断面図（その２）である。FIGS. 2A and 2B are cross-sectional views showing a basic process for mounting an electronic component embedded in an insulating layer in the method for manufacturing an electronic component mounting structure according to the first embodiment of the present invention (No. 2). It is. 図３（ａ）〜（ｄ）は本発明の第１実施形態の電子部品実装構造体の製造方法を示す断面図（その１）である。3A to 3D are cross-sectional views (part 1) showing the method for manufacturing the electronic component mounting structure according to the first embodiment of the present invention. 図４（ａ）〜（ｃ）は本発明の第１実施形態の電子部品実装構造体の製造方法を示す断面図（その２）である。4A to 4C are sectional views (No. 2) showing the method for manufacturing the electronic component mounting structure according to the first embodiment of the present invention. 図５（ａ）及び（ｂ）は本発明の第１実施形態の電子部品実装構造体の製造方法を示す断面図（その３）である。5A and 5B are sectional views (No. 3) showing the method for manufacturing the electronic component mounting structure according to the first embodiment of the invention. 図６（ａ）〜（ｃ）は本発明の第１実施形態の電子部品実装構造体の製造方法における電子部品を絶縁層に埋設して実装する際の基本プロセスを示す断面図（その１）である。FIGS. 6A to 6C are cross-sectional views showing a basic process for mounting an electronic component embedded in an insulating layer in the method for manufacturing an electronic component mounting structure according to the first embodiment of the present invention (No. 1). It is. 図７（ａ）及び（ｂ）は本発明の第１実施形態の電子部品実装構造体の製造方法における電子部品を絶縁層に埋設して実装する際の基本プロセスを示す断面図（その２）である。FIGS. 7A and 7B are cross-sectional views showing a basic process for mounting an electronic component embedded in an insulating layer in the method for manufacturing an electronic component mounting structure according to the first embodiment of the present invention (No. 2). It is. 図８（ａ）〜（ｃ）は本発明の第２実施形態の電子部品実装構造体の製造方法を示す断面図（その１）である。8A to 8C are cross-sectional views (No. 1) showing the method for manufacturing the electronic component mounting structure according to the second embodiment of the present invention. 図９（ａ）〜（ｃ）は本発明の第２実施形態の電子部品実装構造体の製造方法を示す断面図（その２）である。9A to 9C are cross-sectional views (part 2) illustrating the method for manufacturing the electronic component mounting structure according to the second embodiment of the present invention. 図１０（ａ）及び（ｂ）は本発明の第２実施形態の電子部品実装構造体の製造方法を示す断面図（その３）である。10A and 10B are sectional views (No. 3) showing the method for manufacturing the electronic component mounting structure according to the second embodiment of the invention. 図１１（ａ）〜（ｃ）は本発明の第３実施形態の電子部品実装構造体の製造方法を示す断面図（その１）である。11A to 11C are cross-sectional views (part 1) showing the method for manufacturing the electronic component mounting structure according to the third embodiment of the present invention. 図１２（ａ）及び（ｂ）は本発明の第３実施形態の電子部品実装構造体の製造方法を示す断面図（その２）である。12A and 12B are cross-sectional views (part 2) showing the method for manufacturing the electronic component mounting structure according to the third embodiment of the present invention.

符号の説明Explanation of symbols

１，１ａ，１ｂ…電子部品実装構造体、１０…基板、１２…配線パターン、１３…下地絶縁層、１４ａ…粘性液状樹脂、１４…第１絶縁層、１６…第２絶縁層、１８…第１層間絶縁層、１８ｘ…第１ビアホール、１８ａ…第２層間絶縁層、１８ｙ…第２ビアホール、２０…電子部品、２０ａ…接続端子、３０…コア基板、３０ａ…スルーホール、３１…導電性ビア、３２…第１配線パターン、３２ａ…第２配線パターン、３２ｂ…第３配線パターン、３４…ソルダレジスト膜、３４ｘ…開口部、Ｃ…接続部、４０…チップキャパシタ、４２…シリコン基板、４４…下部電極、４６…誘電体、４８…上部電極、５０…半導体チップ、５０ａ…バンプ。 DESCRIPTION OF SYMBOLS 1,1a, 1b ... Electronic component mounting structure, 10 ... Board | substrate, 12 ... Wiring pattern, 13 ... Base insulating layer, 14a ... Viscous liquid resin, 14 ... 1st insulating layer, 16 ... 2nd insulating layer, 18 ... 1st 1 interlayer insulating layer, 18x ... first via hole, 18a ... second interlayer insulating layer, 18y ... second via hole, 20 ... electronic component, 20a ... connection terminal, 30 ... core substrate, 30a ... through hole, 31 ... conductive via 32 ... 1st wiring pattern, 32a ... 2nd wiring pattern, 32b ... 3rd wiring pattern, 34 ... Solder resist film, 34x ... Opening part, C ... Connection part, 40 ... Chip capacitor, 42 ... Silicon substrate, 44 ... Lower electrode, 46 ... dielectric, 48 ... upper electrode, 50 ... semiconductor chip, 50a ... bump.

Claims (10)

被実装体の上に粘性液状樹脂を形成する工程と、
前記粘性液状樹脂の上に電子部品を配置して仮接着する工程と、
前記粘性液状樹脂を熱処理によって硬化させて第１絶縁層を得ることにより、前記電子部品を前記第１絶縁層に固着する工程と、
前記電子部品を被覆する第２絶縁層を形成する工程とを有することを特徴とする電子部品実装構造体の製造方法。 Forming a viscous liquid resin on the mounted body;
Placing electronic components on the viscous liquid resin and temporarily bonding them;
Fixing the electronic component to the first insulating layer by curing the viscous liquid resin by heat treatment to obtain a first insulating layer;
Forming a second insulating layer covering the electronic component. A method of manufacturing an electronic component mounting structure, comprising: 前記粘性液状樹脂から形成される前記第１絶縁層及び前記第２絶縁層は、同一樹脂からなることを特徴とする請求項１に記載の電子部品実装構造体の製造方法。   2. The method of manufacturing an electronic component mounting structure according to claim 1, wherein the first insulating layer and the second insulating layer formed of the viscous liquid resin are made of the same resin. 前記被実装体は配線パターンを備えた基板であり、
前記粘性液状樹脂を前記配線パターンの上に形成することを特徴とする請求項１に記載の電子部品実装構造体の製造方法。 The mounted body is a substrate provided with a wiring pattern,
The method for manufacturing an electronic component mounting structure according to claim 1, wherein the viscous liquid resin is formed on the wiring pattern. 前記被実装体は配線パターンを備えた基板であり、
前記粘性液状樹脂を形成する工程の前に、前記配線パターンを被覆する下地絶縁層を形成する工程をさらに有し、
前記粘性液状樹脂を前記下地絶縁層の上に形成することを特徴とする請求項１に記載の電子部品実装構造体の製造方法。 The mounted body is a substrate provided with a wiring pattern,
Before the step of forming the viscous liquid resin, further comprising a step of forming a base insulating layer that covers the wiring pattern,
The method for manufacturing an electronic component mounting structure according to claim 1, wherein the viscous liquid resin is formed on the base insulating layer. 前記電子部品を配置する工程において、
前記電子部品は接続端子を備えており、前記接続端子を上側に向けて前記電子部品を配置することを特徴とする請求項３又は４に記載の電子部品実装構造体の製造方法。 In the step of arranging the electronic component,
5. The method of manufacturing an electronic component mounting structure according to claim 3, wherein the electronic component includes a connection terminal, and the electronic component is arranged with the connection terminal facing upward. 前記第２絶縁層を得る工程の後に、
前記絶縁層に設けられたビアホールを介して、前記電子部品の接続端子及び前記基板上の前記配線パターンに電気的に接続されるｎ層（ｎは１以上の整数）の配線パターンを形成する工程をさらに有することを特徴とする請求項５に記載の電子部品実装構造体の製造方法 After obtaining the second insulating layer,
Forming a wiring pattern of an n layer (n is an integer of 1 or more) electrically connected to the connection terminal of the electronic component and the wiring pattern on the substrate through a via hole provided in the insulating layer; The method of manufacturing an electronic component mounting structure according to claim 5, further comprising: 前記基板が備えた前記配線パターンは、前記基板を貫通して設けられた導電性ビアを介して相互接続された状態で前記基板の両面側に形成されており、前記ｎ層の配線パターンは前記基板の両面側に形成されることを特徴とする請求項６に記載の電子部品実装構造体の製造方法。   The wiring pattern provided in the substrate is formed on both sides of the substrate in a state of being interconnected through conductive vias provided through the substrate, and the wiring pattern of the n layer is the The method for manufacturing an electronic component mounting structure according to claim 6, wherein the electronic component mounting structure is formed on both sides of the substrate. 前記電子部品を配置する工程において、
前記電子部品はバンプを備えており、前記電子部品のバンプを前記粘性液状樹脂に押し込んで前記配線パターンに電気接続できるように接触させることを特徴とする請求項１に記載の電子部品実装構造体の製造方法。 In the step of arranging the electronic component,
The electronic component mounting structure according to claim 1, wherein the electronic component includes a bump, and the bump of the electronic component is pressed into the viscous liquid resin so as to be electrically connected to the wiring pattern. Manufacturing method. 前記電子部品は、厚みが１００μｍ以下の半導体チップ又はチップキャパシタであることを特徴とする請求項１乃至８のいずれか一項に記載の電子部品実装構造体の製造方法。   The method of manufacturing an electronic component mounting structure according to any one of claims 1 to 8, wherein the electronic component is a semiconductor chip or a chip capacitor having a thickness of 100 µm or less. 前記粘性液状樹脂から形成される第１絶縁層及び前記第２絶縁層は、エポキシ樹脂又はポリイミド樹脂からなることを特徴とする請求項２に記載の電子部品実装構造体の製造方法。   The method for manufacturing an electronic component mounting structure according to claim 2, wherein the first insulating layer and the second insulating layer formed of the viscous liquid resin are made of an epoxy resin or a polyimide resin.
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JP2010251367A (en) * 2009-04-10 2010-11-04 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same, and electronic device
JP2015018851A (en) * 2013-07-09 2015-01-29 新光電気工業株式会社 Method for manufacturing electronic component built-in substrate

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JP2004247706A (en) * 2003-01-23 2004-09-02 Shinko Electric Ind Co Ltd Electronic component packaging structure and manufacturing method therefor
JP2005294383A (en) * 2004-03-31 2005-10-20 Shinko Electric Ind Co Ltd Capacitor mounting wiring board and manufacturing method thereof

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JP2015018851A (en) * 2013-07-09 2015-01-29 新光電気工業株式会社 Method for manufacturing electronic component built-in substrate

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