JP2022047632A - Wiring board, semiconductor device and method for manufacturing the same - Google Patents

Wiring board, semiconductor device and method for manufacturing the same Download PDF

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JP2022047632A
JP2022047632A JP2020153520A JP2020153520A JP2022047632A JP 2022047632 A JP2022047632 A JP 2022047632A JP 2020153520 A JP2020153520 A JP 2020153520A JP 2020153520 A JP2020153520 A JP 2020153520A JP 2022047632 A JP2022047632 A JP 2022047632A
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wiring board
group
semiconductor element
wiring
hole
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圭之 三政
Yoshiyuki Mitsumasa
浩二 細川
Koji Hosokawa
光久 渡部
Mitsuhisa Watabe
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

To provide highly reliable wiring boards, semiconductor devices, and a method for manufacturing the same with improved resistance to thermal stress by eliminating cracking problems caused by bubbles in insulation resin in through holes in wiring boards.SOLUTION: A semiconductor device 1 has a semiconductor device mounting area 101a provided on the first side 101 of the wiring board 10, a first group of through holes 103 provided in the semiconductor device mounting area 101a and penetrating the wiring board 10, and a second group of through holes 104 provided in an area other than the semiconductor device mounting area 101a and penetrating the wiring board 10. The first group of through holes 103 are exposed in the wiring board 10.SELECTED DRAWING: Figure 2

Description

本発明は、配線基板、これを用いた半導体装置及びその製造方法に関する。 The present invention relates to a wiring board, a semiconductor device using the wiring board, and a method for manufacturing the same.

近年、電子機器の小型化に対応するために、半導体部品の高密度実装が要求され、それに伴って半導体装置の小型、薄型化が進んでいる。このような要求に対して、ＢＧＡ(Ball Grid Array)と呼ばれる１つの配線基板の上に半導体素子を高密度実装する技術が開発されている。 In recent years, in order to cope with the miniaturization of electronic devices, high-density mounting of semiconductor components has been required, and along with this, the miniaturization and thinning of semiconductor devices have been progressing. In response to such demands, a technique for mounting semiconductor elements at high density on one wiring board called BGA (Ball Grid Array) has been developed.

ＢＧＡタイプの半導体装置の製造工程としては、配線基板の上面に半導体素子を搭載した後、配線基板の上面及び半導体素子を封止樹脂によって被覆する。また、配線基板の下面に外部接続端子として複数の半田ボールが配置されている。 In the manufacturing process of a BGA type semiconductor device, a semiconductor element is mounted on the upper surface of a wiring substrate, and then the upper surface of the wiring substrate and the semiconductor element are covered with a sealing resin. Further, a plurality of solder balls are arranged as external connection terminals on the lower surface of the wiring board.

従来の配線基板は、上面と下面の配線を電気的に接続するために、貫通穴が設けられている。また、貫通穴の側壁に導電シートが設けられ、貫通穴の内部に絶縁樹脂が充填されるのが一般的な作法である。 The conventional wiring board is provided with a through hole for electrically connecting the wiring on the upper surface and the wiring on the lower surface. Further, it is a general practice that a conductive sheet is provided on the side wall of the through hole and the inside of the through hole is filled with an insulating resin.

しかし、貫通穴の内部に絶縁樹脂を充填する際に、空気の混入により気泡を発生する場合がある。気泡が残留したまま絶縁樹脂を硬化すると、その後の加熱工程において、熱膨張による半導体装置の内部でクラックが発生しやすく、半導体素子と配線基板の配線との接続部分が剥離して電気的接続不良を引き起こす原因となる。その結果、半導体製品の信頼性を確保することが困難となる。 However, when the inside of the through hole is filled with the insulating resin, air bubbles may be generated due to the mixing of air. If the insulating resin is cured with the bubbles remaining, cracks are likely to occur inside the semiconductor device due to thermal expansion in the subsequent heating process, and the connection portion between the semiconductor element and the wiring of the wiring board is peeled off, resulting in poor electrical connection. Causes. As a result, it becomes difficult to ensure the reliability of semiconductor products.

本発明は、上記問題に鑑みなされたものであり、配線基板の貫通穴における絶縁樹脂の気泡に起因したクラック問題を解消し、熱応力に対する耐性を向上した信頼性の高い配線基板、半導体装置及びその製造方法を提供することを目的とする。チップ搭載用基板１０の絶縁ベース基板３を構成する材料としては、ガラスエポキシ樹脂，ポリイミド樹脂などの耐熱性、電気特性に優れた樹脂材料が好ましい。 The present invention has been made in view of the above problems, and is a highly reliable wiring board, a semiconductor device, and a semiconductor device that solves the crack problem caused by bubbles of the insulating resin in the through hole of the wiring board and improves the resistance to thermal stress. It is an object of the present invention to provide the manufacturing method. As the material constituting the insulating base substrate 3 of the chip mounting substrate 10, resin materials having excellent heat resistance and electrical characteristics such as glass epoxy resin and polyimide resin are preferable.

本発明の一態様は、互いに対向する第一面及び第二面を有する配線基板と、前記配線基板の前記第一面に設けられた半導体素子搭載領域と、前記半導体素子搭載領域に搭載された半導体素子と、前記半導体素子及び前記配線基板の前記第一面を被覆する封止樹脂とを備える半導体装置であって、前記配線基板は、前記配線基板の前記第一面及び前記第二面に形成され、前記半導体素子と電気的に接続された配線パターンと、前記半導体素子搭載領域に設けられ、前記配線基板を貫通する第一群の貫通穴と、前記半導体素子搭載領域以外の領域に設けられ、前記配線基板を貫通する第二群の貫通穴と、を備え、前記第一群の貫通穴の側壁、及び前記第二群の貫通穴の側壁に接続配線が形成られ、前記接続配線は、前記配線パターンと電気的に接続され、前記配線基板の前記第一面及び前記第二面は、絶縁部材により被覆され、前記第一群の貫通穴は前記配線基板において露出されている、半導体装置である。 One aspect of the present invention is mounted on a wiring substrate having a first surface and a second surface facing each other, a semiconductor element mounting region provided on the first surface of the wiring substrate, and a semiconductor element mounting region. A semiconductor device including a semiconductor element and a sealing resin that covers the semiconductor element and the first surface of the wiring substrate, wherein the wiring substrate is formed on the first surface and the second surface of the wiring substrate. A wiring pattern formed and electrically connected to the semiconductor element, a first group of through holes provided in the semiconductor element mounting region and penetrating the wiring substrate, and a region other than the semiconductor element mounting region. A connection wiring is formed on the side wall of the through hole of the first group and the side wall of the through hole of the second group, and the connection wiring is provided. A semiconductor that is electrically connected to the wiring pattern, the first surface and the second surface of the wiring board are covered with an insulating member, and the through holes of the first group are exposed in the wiring board. It is a device.

本発明の別の一態様は、互いに対向する第一面及び第二面を有する配線基板であって、前記配線基板の前記第一面に設けられた半導体素子搭載領域と、前記配線基板の前記第一面及び前記第二面に形成された配線パターンと、前記半導体素子搭載領域に設けられ、前記配線基板を貫通する第一群の貫通穴と、前記半導体素子搭載領域以外の領域に設けられ、前記配線基板を貫通する第二群の貫通穴とを備え、前記第一群の貫通穴の側壁、及び前記第二群の貫通穴の側壁に接続配線が形成られ、前記接続配線は、前記配線パターンと電気的に接続され、前記配線基板の前記第一面及び前記第二面は、絶縁部材により被覆され、前記第一群の貫通穴は前記配線基板において露出されている、配線基板である。 Another aspect of the present invention is a wiring board having a first surface and a second surface facing each other, the semiconductor element mounting region provided on the first surface of the wiring board, and the wiring board. The wiring pattern formed on the first surface and the second surface, the through hole of the first group provided in the semiconductor element mounting area and penetrating the wiring substrate, and the area other than the semiconductor element mounting area are provided. , A second group of through holes penetrating the wiring board are provided, and connection wiring is formed on the side wall of the through hole of the first group and the side wall of the through hole of the second group. In a wiring board, which is electrically connected to a wiring pattern, the first surface and the second surface of the wiring board are covered with an insulating member, and the through holes of the first group are exposed in the wiring board. be.

本発明の別の一態様は、互いに対向する第一面及び第二面を有する配線基板であって、前記配線基板の前記第一面における半導体素子搭載領域を設ける工程と、前記半導体素子搭載領域に設けられ、前記配線基板を貫通する第一群の貫通穴、及び前記半導体素子搭載領域以外の領域に設けられ、前記配線基板を貫通する第二群の貫通穴を形成する工程と、前記第一面及び前記第二面に配線パターン、前記第一群の貫通穴の側壁、及び前記第二群の貫通穴の側壁に接続配線を形成する工程と、前記配線基板の前記第一面、前記第二面、前記第一群の貫通穴、及び前記第二群の貫通穴に絶縁部材により被覆する工程と、所定領域でのマスキング、露光及び現像プロセスにより、前記配線基板において前記第一群の貫通穴を露出する工程と、を含む半導体装置の製造方法である。 Another aspect of the present invention is a wiring substrate having a first surface and a second surface facing each other, the step of providing a semiconductor element mounting region on the first surface of the wiring substrate, and the semiconductor element mounting region. A step of forming a through hole of the first group that penetrates the wiring board and a through hole of the second group that is provided in a region other than the semiconductor element mounting region and penetrates the wiring board. A step of forming a wiring pattern on one surface and the second surface, a side wall of the through hole of the first group, and a connection wiring on the side wall of the through hole of the second group, and the first surface of the wiring board, the said. By the step of covering the second surface, the through hole of the first group, and the through hole of the second group with an insulating member, and the masking, exposure, and development process in a predetermined area, the through hole of the first group is formed on the wiring substrate. It is a method of manufacturing a semiconductor device including a step of exposing a through hole.

本発明によれば、絶縁基板の貫通穴における絶縁樹脂の気泡に起因したクラック問題を解消し、熱応力に対する耐性を向上した信頼性の高い配線基板、半導体装置及びその製造方法を提供することができる。 INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a highly reliable wiring board, a semiconductor device, and a method for manufacturing the same, which eliminates the crack problem caused by bubbles of the insulating resin in the through hole of the insulating substrate and improves the resistance to thermal stress. can.

本発明の実施形態１に係る半導体装置の上面図である。It is a top view of the semiconductor device which concerns on Embodiment 1 of this invention. 図１のＡ－Ａ’断面図である。FIG. 1 is a cross-sectional view taken along the line AA'in FIG. 本発明の実施形態１に係る半導体装置の底面図である。It is a bottom view of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施形態２に係る配線基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the wiring board which concerns on Embodiment 2 of this invention. 本発明の実施形態２に係る配線基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the wiring board which concerns on Embodiment 2 of this invention. 本発明の実施形態２に係る配線基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the wiring board which concerns on Embodiment 2 of this invention. 本発明の実施形態２に係る配線基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the wiring board which concerns on Embodiment 2 of this invention. 本発明の実施形態２に係る配線基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the wiring board which concerns on Embodiment 2 of this invention. 本発明の実施形態３に係る半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施形態３に係る半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施形態３に係る半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 3 of this invention.

以下、本発明を実施するための形態につき、図面を参照しながら詳細に説明する。各実施形態は本発明の単なる一例を示したものであって、本発明をこれに限定するものではない。また、各実施形態には種々の変更又は改良を加えることが可能であり、そのような変更又は改良を加えた形態も本発明に含まれ得る。なお、各図面における構成要素の大きさは概念的なものであり、要素間の寸法の相対関係はこれに限定されない。 Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. Each embodiment shows only an example of the present invention, and the present invention is not limited thereto. In addition, various changes or improvements can be added to each embodiment, and the modified or improved forms may be included in the present invention. It should be noted that the size of the constituent elements in each drawing is conceptual, and the relative relationship of the dimensions between the elements is not limited to this.

（実施形態１）
図１～３は、それぞれ本発明の実施形態１に係る半導体装置１を示した上面図と断面図、底面図である。図１～３を併せて参照しながら説明する。半導体装置１は、互いに対向する第一面１０１及び第二面１０２を有する配線基板１０と、配線基板１０の第一面１０１に設けられた半導体素子搭載領域１０１ａと、前記半導体素子搭載領域１０１aに搭載された半導体素子２０と、前記半導体素子２０及び前記配線基板１０の前記第一面１０１を被覆する封止樹脂３０とを備える。前記配線基板１０は、前記第一面１０１及び前記第二面１０２に形成され、前記半導体素子２０と電気的に接続された配線パターン４０と、前記半導体素子搭載領域１０１aに設けられ、前記配線基板１０を貫通する第一群の貫通穴１０３と、前記半導体素子搭載領域１０１a以外の領域に設けられ、前記配線基板１０を貫通する第二群の貫通穴１０４とを備える。前記配線基板１０の前記第一面１０１及び前記第二面１０２は絶縁部材５０により被覆される。前記第一群の貫通穴１０３及び前記第二群の貫通穴１０４の側壁に接続配線４２が形成られる。前記接続配線４２は、前記配線パターン４０と前記半導体素子２０と電気的に接続される。前記第一群の貫通穴１０３は前記配線基板１０において露出されている。
以下、各部の構成について順次詳述する。 (Embodiment 1)
1 to 3 are a top view, a cross-sectional view, and a bottom view showing the semiconductor device 1 according to the first embodiment of the present invention, respectively. This will be described with reference to FIGS. 1 to 3. The semiconductor device 1 is provided in a wiring substrate 10 having a first surface 101 and a second surface 102 facing each other, a semiconductor element mounting region 101a provided on the first surface 101 of the wiring substrate 10, and the semiconductor element mounting region 101a. It includes a mounted semiconductor element 20 and a sealing resin 30 that covers the semiconductor element 20 and the first surface 101 of the wiring substrate 10. The wiring board 10 is provided on the wiring pattern 40 formed on the first surface 101 and the second surface 102 and electrically connected to the semiconductor element 20 and the semiconductor element mounting region 101a, and is provided on the semiconductor element mounting region 101a. It includes a through hole 103 of the first group penetrating the 10 and a through hole 104 of the second group provided in a region other than the semiconductor element mounting region 101a and penetrating the wiring substrate 10. The first surface 101 and the second surface 102 of the wiring board 10 are covered with an insulating member 50. A connection wiring 42 is formed on the side wall of the through hole 103 of the first group and the through hole 104 of the second group. The connection wiring 42 is electrically connected to the wiring pattern 40 and the semiconductor element 20. The through hole 103 of the first group is exposed in the wiring board 10.
Hereinafter, the configuration of each part will be described in detail in order.

配線基板１０の第一面１０１に少なくとも１つ以上の半導体素子搭載領域１０１a及び半導体素子搭載領域１０１a以外の領域が設けられている。半導体素子搭載領域１０１aは半導体素子２０の直下方に位置されている。半導体素子２０は、接着部材６０を介して配線基板１０の第一面１０１の半導体素子搭載領域１０１aに搭載されている。半導体素子搭載領域１０１aの面積は、半導体素子２０の寸法と同一でも良く、同一でなくても良い。具体的には、半導体素子搭載領域１０１aの面積は、半導体素子２０の寸法に比して、７０％以上１３０％以下であり、好ましくは８０％以上１２０％以下であり、さらに好ましくは、９０％以上１１０％以下である。また、半導体素子搭載領域１０１aの形状は、矩形、台形、円形、楕円形等であっても良い。 At least one or more semiconductor element mounting regions 101a and regions other than the semiconductor element mounting region 101a are provided on the first surface 101 of the wiring board 10. The semiconductor element mounting region 101a is located directly below the semiconductor element 20. The semiconductor element 20 is mounted on the semiconductor element mounting region 101a on the first surface 101 of the wiring board 10 via the adhesive member 60. The area of the semiconductor element mounting region 101a may or may not be the same as the dimensions of the semiconductor element 20. Specifically, the area of the semiconductor element mounting region 101a is 70% or more and 130% or less, preferably 80% or more and 120% or less, and more preferably 90% with respect to the dimensions of the semiconductor element 20. It is 110% or less. Further, the shape of the semiconductor element mounting region 101a may be rectangular, trapezoidal, circular, elliptical or the like.

配線基板１０の第一面１０１には、導電性を有する材料からなる配線パターン４０が形成されており、その配線パターン４０の一部は、複数の第一接続パッド４０１が形成されている。その複数の第一接続パッド４０１は、配線基板１０の第一面１０１において露出されており、ワイヤ２０１を介して半導体素子２０の電極パッド２０２と接続される。 A wiring pattern 40 made of a conductive material is formed on the first surface 101 of the wiring board 10, and a plurality of first connection pads 401 are formed in a part of the wiring pattern 40. The plurality of first connection pads 401 are exposed on the first surface 101 of the wiring board 10, and are connected to the electrode pads 202 of the semiconductor element 20 via the wire 201.

配線基板１０の第二面１０２には、導電性を有する材料からなる配線パターン４０が形成されており、その配線パターン４０の一部は、複数の第二接続パッド４０２が形成されている。その複数の第二接続パッド４０２は、配線基板１０の第二面１０２において露出されており、外部端子７０を介してマザーボード等の電子装置（未図示）と接続される。 A wiring pattern 40 made of a conductive material is formed on the second surface 102 of the wiring board 10, and a plurality of second connection pads 402 are formed in a part of the wiring pattern 40. The plurality of second connection pads 402 are exposed on the second surface 102 of the wiring board 10, and are connected to an electronic device (not shown) such as a motherboard via an external terminal 70.

また、配線基板１０は、配線基板１０を貫通する第一群の貫通穴１０３を備える。第一群の貫通穴１０３は、半導体素子搭載領域１０１aに設けられ、配線基板１０の第一面及び第二面において露出されている。 Further, the wiring board 10 includes a through hole 103 of the first group that penetrates the wiring board 10. The through hole 103 of the first group is provided in the semiconductor element mounting region 101a and is exposed on the first surface and the second surface of the wiring board 10.

配線基板１０は、配線基板１０を貫通する第二群の貫通穴１０４を備える。第二群の貫通穴１０４は、半導体素子搭載領域１０１a以外の領域に設けられる。第二群の貫通穴１０４は、配線基板１０の第一面及び第二面において露出されても良いが、露出されなくても良い。 The wiring board 10 includes a second group of through holes 104 that penetrate the wiring board 10. The through hole 104 of the second group is provided in a region other than the semiconductor device mounting region 101a. The through hole 104 of the second group may be exposed on the first surface and the second surface of the wiring board 10, but may not be exposed.

また、第一群の貫通穴１０３及び第二群の貫通穴１０４の側壁に接続配線４２が形成される。接続配線４２は、配線パターン４０と前記半導体素子２０と電気的に接続されている。 Further, a connection wiring 42 is formed on the side wall of the through hole 103 of the first group and the through hole 104 of the second group. The connection wiring 42 is electrically connected to the wiring pattern 40 and the semiconductor element 20.

配線基板１０の第一面１０１は、少なくとも第一群の貫通穴１０３、配線パターン４０の一部及び複数の第一接続パッド４０１を除いて、絶縁部材５０より被覆されている。また、配線基板１０の第二面１０２は、少なくとも第一群の貫通穴１０３、配線パターン４０の一部及び第二接続パッド４０２を除いて、絶縁部材５０より被覆されている。 The first surface 101 of the wiring board 10 is covered with the insulating member 50 except for at least the through hole 103 of the first group, a part of the wiring pattern 40, and the plurality of first connection pads 401. Further, the second surface 102 of the wiring board 10 is covered with the insulating member 50 except for at least the through hole 103 of the first group, a part of the wiring pattern 40, and the second connection pad 402.

第一群の貫通穴１０３は、絶縁部材５０により充填されていない。第二群の貫通穴１０４は、絶縁部材５０により充填されていても良いが、充填されていなくても良い。本実施形態では、第一群の貫通穴１０３は絶縁部材５０により充填されていなく、第二群の貫通穴１０４は絶縁部材５０により充填されていることを例示するが、第一群の貫通穴１０３及び第二群の貫通穴１０４両方とも絶縁部材５０により充填されていないことも可能である。 The through hole 103 of the first group is not filled with the insulating member 50. The through hole 104 of the second group may or may not be filled by the insulating member 50. In the present embodiment, it is exemplified that the through hole 103 of the first group is not filled by the insulating member 50 and the through hole 104 of the second group is filled by the insulating member 50, but the through hole of the first group is filled. It is also possible that both 103 and the through hole 104 of the second group are not filled by the insulating member 50.

なお、図１で示された第一群の貫通穴１０３、第二群の貫通穴１０４は、それぞれ半導体素子２０、絶縁部材５０の下にあるため、実際は上方からは見えないが、説明するために、点線で表している。 Since the through hole 103 of the first group and the through hole 104 of the second group shown in FIG. 1 are under the semiconductor element 20 and the insulating member 50, respectively, they cannot be actually seen from above, but for explanation. It is represented by a dotted line.

また、半導体素子２０、前記配線基板１０の前記第一面１０１及び配線パターン４０は、封止樹脂３０によって封止される。封止樹脂３０は、例えば、エポキシ系樹脂、フェノール系樹脂等の各種樹脂材料で構成されている。 Further, the semiconductor element 20, the first surface 101 of the wiring board 10, and the wiring pattern 40 are sealed by the sealing resin 30. The sealing resin 30 is made of various resin materials such as epoxy-based resin and phenol-based resin.

配線基板１０は、ガラスエポキシ、ポリイミド、ポリエステル、セラミック、エポキシ、ビスマレイミドトリアジン等耐熱性、電気特性に優れた樹脂材料が含んで構成されたコア基板１２を備える。この実施形態では、コア基板１２の主要構成材料としてガラスエポキシが用いられるが、これに限定されない。また、配線基板１０については、この実施形態で示すように、単層基板構造のものを使用してもよいし、多層基板構造のものを使用してもよい。 The wiring board 10 includes a core board 12 composed of a resin material having excellent heat resistance and electrical characteristics such as glass epoxy, polyimide, polyester, ceramic, epoxy, and bismaleimide triazine. In this embodiment, glass epoxy is used as the main constituent material of the core substrate 12, but the present invention is not limited to this. Further, as the wiring board 10, as shown in this embodiment, a single-layer board structure may be used, or a multi-layer board structure may be used.

半導体素子２０と配線基板1０の配線パターン４０との接続方式は、ゴールドワイヤなどの金属細線を介するワイヤーボンディング、またはバンプなどの導電性突起を介するフリップチップ接続方式等が挙げられる。なお、フリップチップ接続方式が利用される場合、バンプのピッチが広め（例えば、３００mｍ以上）のほうが好ましい。この実施例では、半導体素子２０はワイヤ２０１を介して配線パターン４０と電気的に接続されることを例示するが、これに限定されない。 Examples of the connection method between the semiconductor element 20 and the wiring pattern 40 of the wiring board 10 include wire bonding via a fine metal wire such as a gold wire, and a flip chip connection method via a conductive protrusion such as a bump. When the flip chip connection method is used, it is preferable that the bump pitch is wide (for example, 300 mm or more). In this embodiment, it is exemplified that the semiconductor element 20 is electrically connected to the wiring pattern 40 via the wire 201, but the present invention is not limited to this.

半導体素子２０の個数は特に限定されていない。この実施形態で示すように、1つの半導体素子２０が搭載されてもよいが、複数の半導体素子２０が搭載されてもよい。また、複数の半導体素子２０の場合について、半導体素子２０は、Ｘ方向及びＹ方向の少なくとも一方向に沿って配線基板１０の第一面１０１に搭載される。 The number of semiconductor elements 20 is not particularly limited. As shown in this embodiment, one semiconductor element 20 may be mounted, but a plurality of semiconductor elements 20 may be mounted. Further, in the case of a plurality of semiconductor elements 20, the semiconductor element 20 is mounted on the first surface 101 of the wiring board 10 along at least one direction in the X direction and the Y direction.

半導体素子２０の主要構成材料としては、例えばシリコン、炭化ケイ素、化合物半導体等の単結晶材料、多結晶材料、アモルファス材料等が挙げられる。本実施形態では、半導体素子２０の主要構成材料としてシリコンが用いられるが、これに限定されない。 Examples of the main constituent material of the semiconductor element 20 include single crystal materials such as silicon, silicon carbide, and compound semiconductors, polycrystalline materials, and amorphous materials. In the present embodiment, silicon is used as the main constituent material of the semiconductor device 20, but the present invention is not limited to this.

配線パターン４０、第一接続パッド４０１、第二接続パッド４０２及び接続配線４２の主要構成材料としては、金、銀、銅、スズ、ニッケル、鉛又はこれらの合金を含有していることが挙げられるが、これらに限定されない。また、配線パターン４０、第一接続パッド４０１、第二接続パッド４０２及び接続配線４２の主要構成材料は同一でも良く、同一でなくても良い。 The main constituent materials of the wiring pattern 40, the first connection pad 401, the second connection pad 402 and the connection wiring 42 include gold, silver, copper, tin, nickel, lead or alloys thereof. However, it is not limited to these. Further, the main constituent materials of the wiring pattern 40, the first connection pad 401, the second connection pad 402, and the connection wiring 42 may or may not be the same.

絶縁部材５０は、エポキシ系樹脂を主要成分からなるソルダーレジストを用いることが好ましい。また、ソルダーレジストの中では、室温で液状、ペースト状またはフィルム状であって、熱硬化性又は光硬化性のものが挙げられる。この実施形態では、絶縁部材５０は、室温は液状で光硬化性のソルダーレジストを用いることを例示するが、これに限定されない。 As the insulating member 50, it is preferable to use a solder resist containing an epoxy resin as a main component. Further, among the solder resists, those which are liquid, paste-like or film-like at room temperature and which are thermosetting or photocurable can be mentioned. In this embodiment, the insulating member 50 exemplifies the use of a photocurable solder resist that is liquid at room temperature, but is not limited thereto.

（実施形態２）
次に、本発明の実施形態２に係る配線基板１０の製造方法の一例について説明する。図４（ａ）～（ｅ）は、本実施形態１における半導体装置１を搭載するための配線基板１０の製造工程を示す断面図である。 (Embodiment 2)
Next, an example of the method for manufacturing the wiring board 10 according to the second embodiment of the present invention will be described. 4 (a) to 4 (e) are cross-sectional views showing a manufacturing process of a wiring board 10 for mounting the semiconductor device 1 in the first embodiment.

図４（ａ）は、互いに対向する第一面１０１及び第二面１０２を有する配線基板１０を準備し、第一面１０１において半導体素子搭載領域１０１ａを設ける工程を示す。半導体素子搭載領域１０１ａは、半導体素子（未図示）の直下方に位置するように設けられている。半導体素子搭載領域１０１aの面積は、半導体素子２０の寸法と同一でも良く、同一でなくても良い。具体的には、半導体素子搭載領域１０１aの面積は、半導体素子２０の寸法に比して、７０％以上１３０％以下であり、好ましくは８０％以上１２０％以下であり、さらに好ましくは、９０％以上１１０％以下である。また、半導体素子搭載領域１０１aの形状は、矩形、台形、円形、楕円形等であっても良い。 FIG. 4A shows a step of preparing a wiring board 10 having a first surface 101 and a second surface 102 facing each other and providing a semiconductor element mounting region 101a on the first surface 101. The semiconductor element mounting region 101a is provided so as to be located directly below the semiconductor element (not shown). The area of the semiconductor element mounting region 101a may or may not be the same as the dimensions of the semiconductor element 20. Specifically, the area of the semiconductor element mounting region 101a is 70% or more and 130% or less, preferably 80% or more and 120% or less, and more preferably 90% with respect to the dimensions of the semiconductor element 20. It is 110% or less. Further, the shape of the semiconductor element mounting region 101a may be rectangular, trapezoidal, circular, elliptical or the like.

図４（ｂ）は、半導体素子搭載領域１０１ａに設けられ、配線基板１０を貫通する第一群の貫通穴１０３、及び半導体素子搭載領域１０１ａ以外の領域に設けられ、配線基板１０を貫通する第二群の貫通穴１０４を形成する工程を示す。貫通穴を形成する工程としては、例えば、ドリル、パンチング、エッチング、サンドブラスト、レーザ等の手段を用いることが挙げられるが、これらに限定されない。 FIG. 4B is a second group provided in the semiconductor element mounting region 101a, provided in a region other than the through hole 103 of the first group penetrating the wiring board 10 and the semiconductor element mounting region 101a, and penetrating the wiring board 10. The process of forming the through hole 104 of two groups is shown. Examples of the step of forming the through hole include, but are not limited to, using means such as drilling, punching, etching, sandblasting, and laser.

図４（ｃ）は、配線基板１０の第一面１０１及び第二面１０２に配線パターン４０、及び第一群の貫通穴１０３の側壁及び第二群の貫通穴１０４の側壁に接続配線４２を形成する工程を示す。具体的には、配線基板１０の第一面１０１及び第二面１０２に配線パターン４０、第一群の貫通穴１０３の側壁及び第二群の貫通穴１０４の側壁に無電解銅めっき（未図示）を形成し、その次に電解銅めっき（未図示）を形成する。続いて、ドライフィルム（未図示）によって配線基板１０にラミネートしてからマスク露光、現像、エッチング等の工程を経て、所望の配線パターン４０及び接続配線４２を形成する。 FIG. 4C shows a wiring pattern 40 on the first surface 101 and the second surface 102 of the wiring board 10, and a connection wiring 42 on the side wall of the through hole 103 of the first group and the side wall of the through hole 104 of the second group. The process of forming is shown. Specifically, the wiring pattern 40 is on the first surface 101 and the second surface 102 of the wiring board 10, and the side wall of the through hole 103 of the first group and the side wall of the through hole 104 of the second group are electroless copper plated (not shown). ), And then electrolytic copper plating (not shown). Subsequently, after laminating on the wiring board 10 with a dry film (not shown), a desired wiring pattern 40 and connection wiring 42 are formed through steps such as mask exposure, development, and etching.

さらに、配線基板１０の第一面１０１の配線パターン４０の一部には、複数の第一接続パッド４０１を形成し、配線基板１０の第二面１０２の配線パターン４０の一部には、複数の第二接続パッド４０２を形成する。その後、ドライフィルムを剥がして、次の工程に入る。 Further, a plurality of first connection pads 401 are formed on a part of the wiring pattern 40 on the first surface 101 of the wiring board 10, and a plurality of wiring patterns 40 on the second surface 102 of the wiring board 10 are formed. The second connection pad 402 of the above is formed. After that, the dry film is peeled off and the next step is started.

配線パターン４０、第一接続パッド４０１、第二接続パッド４０２及び接続配線４２の主要構成材料としては、金、銀、銅、スズ、ニッケル、鉛又はこれらの合金を含有していることが挙げられるが、これらに限定されない。また、配線パターン４０、第一接続パッド４０１、第二接続パッド４０２及び接続配線４２の主要構成材料は同一でも良く、同一でなくても良い。 The main constituent materials of the wiring pattern 40, the first connection pad 401, the second connection pad 402 and the connection wiring 42 include gold, silver, copper, tin, nickel, lead or alloys thereof. However, it is not limited to these. Further, the main constituent materials of the wiring pattern 40, the first connection pad 401, the second connection pad 402, and the connection wiring 42 may or may not be the same.

図４（ｄ）は、配線基板１０の第一面１０１、第二面１０２、第一群の貫通穴１０３、及び第二群の貫通穴１０４に絶縁部材５０により被覆する工程を示す。具体的には、ソルダーレジストによって、配線基板１０の第一面１０１、第二面１０２に塗布する。また、第一群の貫通穴１０３及び第二群の貫通穴１０４は、ソルダーレジストによって充填される。塗布方法としては、スクリーン印刷法、ロールコート法、又はスピンコート法等が挙げられるが、これらに限定されない。 FIG. 4D shows a step of covering the first surface 101, the second surface 102, the through hole 103 of the first group, and the through hole 104 of the second group of the wiring board 10 with the insulating member 50. Specifically, the solder resist is applied to the first surface 101 and the second surface 102 of the wiring board 10. Further, the through hole 103 of the first group and the through hole 104 of the second group are filled with a solder resist. Examples of the coating method include, but are not limited to, a screen printing method, a roll coating method, a spin coating method, and the like.

また、絶縁部材５０は、温度、湿度などの環境条件、延び性、粘度、利用の容易性等を考慮して適宜選択できるが、エポキシ系樹脂を主要成分からなるソルダーレジストを用いることが好ましい。また、ソルダーレジストの中では、室温で液状、ペースト状またはフィルム状であって、熱硬化性又は光硬化性のものが挙げられる。この実施形態では、絶縁部材５０は、液状で光硬化性のソルダーレジストを用いることを例示するが、これに限定されない。 The insulating member 50 can be appropriately selected in consideration of environmental conditions such as temperature and humidity, extensibility, viscosity, ease of use, etc., but it is preferable to use a solder resist containing an epoxy resin as a main component. Further, among the solder resists, those which are liquid, paste-like or film-like at room temperature and which are thermosetting or photocurable can be mentioned. In this embodiment, the insulating member 50 exemplifies the use of a liquid and photocurable solder resist, but is not limited thereto.

図４（ｅ）は、所定領域でのマスキング、露光及び現像プロセスにより、絶縁部材５０を除去して第一群の貫通穴１０３を露出する工程を示す。所定領域としては、配線基板１０の第一面１０１には、少なくとも第一群の貫通穴１０３、配線パターン４０の一部及び複数の第一接続パッド４０１が含まれ、配線基板１０の第二面１０２には、少なくとも第一群の貫通穴１０３、配線パターン４０の一部及び複数の第二接続パッド４０２が含まれる。また、必要によって、さらに第一面１０１及び第二面１０２の他の部分が所定領域に含まれることも可能である。この実施形態では、第一群の貫通穴１０３は、配線基板１０において露出されており、第一群の貫通穴１０３の中に充填されていた絶縁部材５０は除去される。また、第二群の貫通穴１０４は、所定領域以外の領域に位置されているため、絶縁部材５０によって被覆、充填され、配線基板１０において露出されていない。 FIG. 4 (e) shows a step of removing the insulating member 50 to expose the through hole 103 of the first group by a masking, exposure and development process in a predetermined region. As a predetermined area, the first surface 101 of the wiring board 10 includes at least a through hole 103 of the first group, a part of the wiring pattern 40, and a plurality of first connection pads 401, and the second surface of the wiring board 10 is included. 102 includes at least a first group of through holes 103, a portion of the wiring pattern 40, and a plurality of second connection pads 402. Further, if necessary, other parts of the first surface 101 and the second surface 102 can be further included in the predetermined area. In this embodiment, the through hole 103 of the first group is exposed in the wiring board 10, and the insulating member 50 filled in the through hole 103 of the first group is removed. Further, since the through hole 104 of the second group is located in a region other than a predetermined region, it is covered and filled with the insulating member 50 and is not exposed on the wiring board 10.

なお、別の実施形態（未図示）では、第一群の貫通穴１０３及び第二群の貫通穴１０４両方とも配線基板１０において露出されており、また、第一群の貫通穴１０３及び第二群の貫通穴１０４の中に充填されていた絶縁部材５０も除去される。 In another embodiment (not shown), both the through hole 103 of the first group and the through hole 104 of the second group are exposed on the wiring board 10, and the through hole 103 and the second through hole 103 of the first group are exposed. The insulating member 50 filled in the through holes 104 of the group is also removed.

また、配線基板１０については、この実施形態で示す単層基板構造のものでも良く、多層基板構造のものでも良い。多層基板構造の場合について、ビルドアップ層形成してから前述した工程を続いてゆくので、ここでは適宜、説明を省略する。 Further, the wiring board 10 may have a single-layer board structure or a multi-layer board structure shown in this embodiment. In the case of a multilayer board structure, the above-mentioned steps will be continued after the build-up layer is formed, so the description thereof will be omitted here as appropriate.

（実施形態３）
次に、本発明の実施形態３は、実施形態１における半導体装置１の製造方法の一例について説明する。図５（ａ）～（ｂ）は、本実施形態２において製造された配線基板１０を利用し、実施形態１の半導体装置１を製造する工程を示す断面図である。 (Embodiment 3)
Next, the third embodiment of the present invention will explain an example of the manufacturing method of the semiconductor device 1 in the first embodiment. 5 (a) to 5 (b) are cross-sectional views showing a process of manufacturing the semiconductor device 1 of the first embodiment by using the wiring board 10 manufactured in the second embodiment.

図５（ａ）は、半導体素子２０を配線基板１０の半導体素子搭載領域（未図示）に搭載する工程、及び半導体素子２０と配線パターン４０とを電気的に接続する工程を示す。具体的には、半導体素子２０は、半導体素子搭載領域の直上方に位置されるように、接着部材６０を介して配線基板１０の第一面１０１の半導体素子搭載領域に搭載される。そして、半導体素子２０の電極パッド２０２は、ワイヤ２０１を介して第一接続パッド４０１と接続される。 FIG. 5A shows a step of mounting the semiconductor element 20 in a semiconductor element mounting region (not shown) of the wiring substrate 10 and a step of electrically connecting the semiconductor element 20 and the wiring pattern 40. Specifically, the semiconductor element 20 is mounted in the semiconductor element mounting region of the first surface 101 of the wiring substrate 10 via the adhesive member 60 so as to be located directly above the semiconductor element mounting region. Then, the electrode pad 202 of the semiconductor element 20 is connected to the first connection pad 401 via the wire 201.

半導体素子２０の個数は特に限定されていない。この実施形態で示すように、1つの半導体素子２０を搭載してもよいが、複数の半導体素子２０を搭載してもよい。複数の半導体素子２０の場合について、半導体素子２０は、Ｘ方向及びＹ方向の少なくとも一方向に沿って、配線基板１０の第一面１０１に搭載される。また、複数の半導体素子２０の場合は、少なくとも１つの半導体素子２０が半導体素子搭載領域１０１aの直上方に搭載されれば良い。 The number of semiconductor elements 20 is not particularly limited. As shown in this embodiment, one semiconductor element 20 may be mounted, or a plurality of semiconductor elements 20 may be mounted. In the case of the plurality of semiconductor elements 20, the semiconductor elements 20 are mounted on the first surface 101 of the wiring board 10 along at least one direction in the X direction and the Y direction. Further, in the case of a plurality of semiconductor elements 20, at least one semiconductor element 20 may be mounted directly above the semiconductor element mounting region 101a.

図５（ｂ）は、半導体素子２０、配線基板１０の第一面１０１及び配線パターン４０を封止樹脂３０によって被覆して封止体８０を形成し、配線基板１０の第二面１０２に露出されている複数の第二接続パッド４０２に外部端子７０を形成する工程を示す。具体的には、樹脂成形プロセスによる樹脂封止を行い、半導体素子２０、配線基板１０の第一面１０１及び配線パターン４０を封止樹脂３０によって封止する。封止樹脂３０は、例えば、エポキシ系樹脂、フェノール系樹脂等の各種樹脂材料で構成されている。また、外部端子７０は、配線基板１０の第二面１０２の外周に、アレイ状に配置される（図３を参照する）。その外部端子７０を介してマザーボード等の電子装置（未図示）と接続される。 In FIG. 5B, the semiconductor element 20, the first surface 101 of the wiring board 10, and the wiring pattern 40 are covered with the sealing resin 30 to form the encapsulating body 80, which is exposed on the second surface 102 of the wiring board 10. The process of forming the external terminal 70 on the plurality of second connection pads 402 which is made is shown. Specifically, resin sealing is performed by a resin molding process, and the semiconductor element 20, the first surface 101 of the wiring board 10, and the wiring pattern 40 are sealed with the sealing resin 30. The sealing resin 30 is made of various resin materials such as epoxy-based resin and phenol-based resin. Further, the external terminals 70 are arranged in an array on the outer periphery of the second surface 102 of the wiring board 10 (see FIG. 3). It is connected to an electronic device (not shown) such as a motherboard via the external terminal 70.

図５（ｃ）は封止体８０を個片化にして、半導体装置１を形成する工程を示す。個片化する手段としては、例えば、ダイシングブレードにより封止体８０を所望の形状に切断する。 FIG. 5C shows a step of forming the semiconductor device 1 by disassembling the sealing body 80 into individual pieces. As a means for individualizing, for example, the sealing body 80 is cut into a desired shape by a dicing blade.

以上説明した実施形態によれば、配線基板の貫通穴における絶縁樹脂の気泡に起因したクラック問題を解消し、熱応力に対する耐性を向上した信頼性の高い配線基板、半導体装置及びその製造方法を提供することができる。 According to the embodiment described above, a highly reliable wiring board, a semiconductor device, and a method for manufacturing the same are provided, which eliminates the crack problem caused by bubbles of the insulating resin in the through hole of the wiring board and improves the resistance to thermal stress. can do.

本発明の幾つかの実施形態を説明したが、上記実施形態は、例示であり、本発明を上記形態に限定することを意図するものではない。上記実施形態は、その他の様々な形態で実施することが可能であり、発明の要旨を逸脱しない範囲で種々の省略、置き換え、変更を行うことができる。 Although some embodiments of the present invention have been described, the above embodiments are exemplary and are not intended to limit the invention to the above embodiments. The above embodiment can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention.

１ 半導体装置
１０ 配線基板
１２ コア基板
２０ 半導体素子
３０ 封止樹脂
４０ 配線パターン
４２ 接続配線
５０ 絶縁部材
６０ 接着部材
７０ 外部端子
８０ 封止体
１０１ 第一面
１０１ａ 半導体素子搭載領域
１０２ 第二面
１０３ 第一群の貫通穴
１０４ 第二群の貫通穴
２０１ ワイヤ
２０２ 電極パッド
４０１ 第一接続パッド
４０２ 第二接続パッド 1 Semiconductor device 10 Wiring board 12 Core board 20 Semiconductor element 30 Encapsulation resin 40 Wiring pattern 42 Connection wiring 50 Insulation member 60 Adhesive member 70 External terminal 80 Encapsulant 101 First surface 101a Semiconductor element mounting area 102 Second surface 103 First Group of through holes 104 Second group of through holes 201 Wire 202 Electrode pad 401 First connection pad 402 Second connection pad

Claims (10)

互いに対向する第一面及び第二面を有する配線基板と、
前記配線基板の前記第一面に設けられた半導体素子搭載領域と、
前記半導体素子搭載領域に搭載された半導体素子と、
前記半導体素子及び前記配線基板の前記第一面を被覆する封止樹脂と、
を備える半導体装置であって、
前記配線基板は、
前記配線基板の前記第一面及び前記第二面に形成され、前記半導体素子と電気的に接続された配線パターンと、
前記半導体素子搭載領域に設けられ、前記配線基板を貫通する第一群の貫通穴と、
前記半導体素子搭載領域以外の領域に設けられ、前記配線基板を貫通する第二群の貫通穴と、を備え、
前記第一群の貫通穴の側壁、及び前記第二群の貫通穴の側壁に接続配線が形成られ、前記接続配線は、前記配線パターンと電気的に接続され、
前記配線基板の前記第一面及び前記第二面は、絶縁部材により被覆され、
前記第一群の貫通穴は、前記配線基板において露出されている、半導体装置。 A wiring board having a first surface and a second surface facing each other,
A semiconductor element mounting area provided on the first surface of the wiring board,
The semiconductor element mounted in the semiconductor element mounting area and
A sealing resin that covers the first surface of the semiconductor element and the wiring board, and
It is a semiconductor device equipped with
The wiring board is
A wiring pattern formed on the first surface and the second surface of the wiring board and electrically connected to the semiconductor element,
The first group of through holes provided in the semiconductor element mounting area and penetrating the wiring board, and
A second group of through holes provided in an area other than the semiconductor element mounting area and penetrating the wiring board are provided.
Connection wiring is formed on the side wall of the through hole of the first group and the side wall of the through hole of the second group, and the connection wiring is electrically connected to the wiring pattern.
The first surface and the second surface of the wiring board are covered with an insulating member, and the first surface and the second surface are covered with an insulating member.
The through hole of the first group is a semiconductor device exposed in the wiring board. 前記第一群の貫通穴は、前記絶縁部材により充填されていない、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the through holes in the first group are not filled with the insulating member. 前記第二群の貫通穴は、前記絶縁部材により充填されている、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the through holes of the second group are filled with the insulating member. 互いに対向する第一面及び第二面を有する配線基板であって、
前記配線基板の前記第一面に設けられた半導体素子搭載領域と、
前記配線基板の前記第一面及び前記第二面に形成された配線パターンと、
前記半導体素子搭載領域に設けられ、前記配線基板を貫通する第一群の貫通穴と、
前記半導体素子搭載領域以外の領域に設けられ、前記配線基板を貫通する第二群の貫通穴と、
を備え、
前記第一群の貫通穴の側壁、及び前記第二群の貫通穴の側壁に接続配線が形成られ、前記接続配線は、前記配線パターンと電気的に接続され、
前記配線基板の前記第一面及び前記第二面は、絶縁部材により被覆され、
前記第一群の貫通穴は、前記配線基板において露出されている、配線基板。 A wiring board having a first surface and a second surface facing each other.
A semiconductor element mounting area provided on the first surface of the wiring board,
The wiring patterns formed on the first surface and the second surface of the wiring board,
The first group of through holes provided in the semiconductor element mounting area and penetrating the wiring board, and
A second group of through holes provided in an area other than the semiconductor element mounting area and penetrating the wiring board, and
Equipped with
Connection wiring is formed on the side wall of the through hole of the first group and the side wall of the through hole of the second group, and the connection wiring is electrically connected to the wiring pattern.
The first surface and the second surface of the wiring board are covered with an insulating member, and the first surface and the second surface are covered with an insulating member.
The through hole of the first group is a wiring board exposed in the wiring board. 前記第一群の貫通穴は、前記絶縁部材により充填されていない、請求項4に記載の配線基板。 The wiring board according to claim 4, wherein the through holes in the first group are not filled with the insulating member. 前記第二群の貫通穴は、前記絶縁部材により充填されている、請求項4に記載の配線基板。 The wiring board according to claim 4, wherein the through holes of the second group are filled with the insulating member. 互いに対向する第一面及び第二面を有する配線基板であって、前記配線基板の前記第一面における半導体素子搭載領域を設ける工程と、
前記半導体素子搭載領域に設けられ、前記配線基板を貫通する第一群の貫通穴、及び前記半導体素子搭載領域以外の領域に設けられ、前記配線基板を貫通する第二群の貫通穴を形成する工程と、
前記第一面及び前記第二面に配線パターン、前記第一群の貫通穴の側壁、及び前記第二群の貫通穴の側壁に接続配線を形成する工程と、
前記配線基板の前記第一面、前記第二面、前記第一群の貫通穴、及び前記第二群の貫通穴に絶縁部材により被覆する工程と、
所定領域でのマスキング、露光及び現像プロセスにより、前記配線基板において前記第一群の貫通穴を露出する工程と、を含む半導体装置の製造方法。 A wiring board having a first surface and a second surface facing each other, and a step of providing a semiconductor element mounting region on the first surface of the wiring board.
A first group of through holes provided in the semiconductor element mounting region and penetrating the wiring board, and a second group of through holes provided in a region other than the semiconductor element mounting region and penetrating the wiring board are formed. Process and
A step of forming a wiring pattern on the first surface and the second surface, a side wall of the through hole of the first group, and a connection wiring on the side wall of the through hole of the second group.
A step of covering the first surface, the second surface, the through hole of the first group, and the through hole of the second group of the wiring board with an insulating member.
A method for manufacturing a semiconductor device, comprising a step of exposing the through holes of the first group in the wiring substrate by a masking, exposure, and development process in a predetermined region. 前記第一群の貫通穴は、前記絶縁部材により充填されていない、請求項７に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 7, wherein the through holes in the first group are not filled with the insulating member. 前記第二群の貫通穴は、前記絶縁部材により充填されている、請求項7に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 7, wherein the through holes in the second group are filled with the insulating member. 半導体素子を前記配線基板の前記半導体素子搭載領域に搭載する工程と、
前記半導体素子と前記配線パターンとを電気的に接続する工程と、
前記半導体素子、前記配線基板の前記第一面、及び前記配線パターンを封止樹脂によって被覆し、封止体を形成する工程と、
前記封止体を個片化する工程と、
をさらに含む、請求項7に記載の半導体装置の製造方法。 A process of mounting a semiconductor element in the semiconductor element mounting area of the wiring board, and
The process of electrically connecting the semiconductor element and the wiring pattern,
A step of covering the semiconductor element, the first surface of the wiring board, and the wiring pattern with a sealing resin to form a sealed body.
The step of disassembling the sealed body and
7. The method for manufacturing a semiconductor device according to claim 7.
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JP2001196490A (en) * 1999-11-04 2001-07-19 Fujitsu Ltd Semiconductor device
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Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982841A (en) * 1995-07-05 1997-03-28 Anam Ind Co Inc Ball grid array semiconductor package that heat dissipation property and dehumidifying are enhanced
JP2001196490A (en) * 1999-11-04 2001-07-19 Fujitsu Ltd Semiconductor device
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