JP2008263509A5 - - Google Patents

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Publication number
JP2008263509A5
JP2008263509A5 JP2007105959A JP2007105959A JP2008263509A5 JP 2008263509 A5 JP2008263509 A5 JP 2008263509A5 JP 2007105959 A JP2007105959 A JP 2007105959A JP 2007105959 A JP2007105959 A JP 2007105959A JP 2008263509 A5 JP2008263509 A5 JP 2008263509A5
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JP
Japan
Prior art keywords
phase
signal
integrator
clock
correction control
Prior art date
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Granted
Application number
JP2007105959A
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English (en)
Japanese (ja)
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JP2008263509A (ja
JP4971861B2 (ja
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Publication date
Application filed filed Critical
Priority to JP2007105959A priority Critical patent/JP4971861B2/ja
Priority claimed from JP2007105959A external-priority patent/JP4971861B2/ja
Priority to US12/081,102 priority patent/US8199868B2/en
Publication of JP2008263509A publication Critical patent/JP2008263509A/ja
Publication of JP2008263509A5 publication Critical patent/JP2008263509A5/ja
Application granted granted Critical
Publication of JP4971861B2 publication Critical patent/JP4971861B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2007105959A 2007-04-13 2007-04-13 クロックアンドデータリカバリ回路 Expired - Fee Related JP4971861B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007105959A JP4971861B2 (ja) 2007-04-13 2007-04-13 クロックアンドデータリカバリ回路
US12/081,102 US8199868B2 (en) 2007-04-13 2008-04-10 Clock and data recovery circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007105959A JP4971861B2 (ja) 2007-04-13 2007-04-13 クロックアンドデータリカバリ回路

Publications (3)

Publication Number Publication Date
JP2008263509A JP2008263509A (ja) 2008-10-30
JP2008263509A5 true JP2008263509A5 (enExample) 2010-05-06
JP4971861B2 JP4971861B2 (ja) 2012-07-11

Family

ID=39853692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007105959A Expired - Fee Related JP4971861B2 (ja) 2007-04-13 2007-04-13 クロックアンドデータリカバリ回路

Country Status (2)

Country Link
US (1) US8199868B2 (enExample)
JP (1) JP4971861B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5300671B2 (ja) * 2009-09-14 2013-09-25 株式会社東芝 クロックリカバリ回路およびデータ再生回路
US8879185B1 (en) * 2010-11-03 2014-11-04 Marvell International Ltd. Disk synchronous write architecture for bit-patterned recording
US9077349B2 (en) * 2012-02-21 2015-07-07 Qualcomm Incorporated Automatic detection and compensation of frequency offset in point-to-point communication
JP6135217B2 (ja) 2013-03-18 2017-05-31 富士通株式会社 信号補正装置、送信装置、信号補正方法、及び伝送システム
TWI598737B (zh) * 2017-01-20 2017-09-11 群聯電子股份有限公司 參考時脈訊號產生方法、記憶體儲存裝置及連接介面單元
CN116545818A (zh) * 2023-05-08 2023-08-04 上海米硅科技有限公司 一种应用于伪随机二进制序列的时钟数据对齐方法及装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003073280A1 (en) * 2002-02-26 2003-09-04 Advantest Corporation Measuring apparatus and measuring method
US7486894B2 (en) * 2002-06-25 2009-02-03 Finisar Corporation Transceiver module and integrated circuit with dual eye openers
JP3973502B2 (ja) * 2002-07-09 2007-09-12 Ｎｅｃエレクトロニクス株式会社 クロックデータリカバリー回路
JP4335586B2 (ja) * 2003-06-11 2009-09-30 Ｎｅｃエレクトロニクス株式会社 クロックアンドデータリカバリ回路
JP4651298B2 (ja) * 2004-04-08 2011-03-16 三菱電機株式会社 周波数自動補正ｐｌｌ回路
US7336755B1 (en) * 2004-06-08 2008-02-26 Xilinx, Inc. PLL with low phase noise non-integer divider
US7574146B2 (en) * 2004-07-09 2009-08-11 Infinera Corporation Pattern-dependent error counts for use in correcting operational parameters in an optical receiver
JP4657662B2 (ja) * 2004-09-10 2011-03-23 ルネサスエレクトロニクス株式会社 クロックアンドデータリカバリ回路
US7164322B1 (en) * 2005-07-21 2007-01-16 Agilent Technologies, Inc. Establishing a tuning signal window for use in centering a multi-band voltage controlled oscillator

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