JP4971861B2 - クロックアンドデータリカバリ回路 - Google Patents

クロックアンドデータリカバリ回路 Download PDF

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Publication number
JP4971861B2
JP4971861B2 JP2007105959A JP2007105959A JP4971861B2 JP 4971861 B2 JP4971861 B2 JP 4971861B2 JP 2007105959 A JP2007105959 A JP 2007105959A JP 2007105959 A JP2007105959 A JP 2007105959A JP 4971861 B2 JP4971861 B2 JP 4971861B2
Authority
JP
Japan
Prior art keywords
phase
integrator
clock
signal
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007105959A
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English (en)
Japanese (ja)
Other versions
JP2008263509A5 (enExample
JP2008263509A (ja
Inventor
森繁 青山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2007105959A priority Critical patent/JP4971861B2/ja
Priority to US12/081,102 priority patent/US8199868B2/en
Publication of JP2008263509A publication Critical patent/JP2008263509A/ja
Publication of JP2008263509A5 publication Critical patent/JP2008263509A5/ja
Application granted granted Critical
Publication of JP4971861B2 publication Critical patent/JP4971861B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
JP2007105959A 2007-04-13 2007-04-13 クロックアンドデータリカバリ回路 Expired - Fee Related JP4971861B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007105959A JP4971861B2 (ja) 2007-04-13 2007-04-13 クロックアンドデータリカバリ回路
US12/081,102 US8199868B2 (en) 2007-04-13 2008-04-10 Clock and data recovery circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007105959A JP4971861B2 (ja) 2007-04-13 2007-04-13 クロックアンドデータリカバリ回路

Publications (3)

Publication Number Publication Date
JP2008263509A JP2008263509A (ja) 2008-10-30
JP2008263509A5 JP2008263509A5 (enExample) 2010-05-06
JP4971861B2 true JP4971861B2 (ja) 2012-07-11

Family

ID=39853692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007105959A Expired - Fee Related JP4971861B2 (ja) 2007-04-13 2007-04-13 クロックアンドデータリカバリ回路

Country Status (2)

Country Link
US (1) US8199868B2 (enExample)
JP (1) JP4971861B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5300671B2 (ja) * 2009-09-14 2013-09-25 株式会社東芝 クロックリカバリ回路およびデータ再生回路
US8879185B1 (en) * 2010-11-03 2014-11-04 Marvell International Ltd. Disk synchronous write architecture for bit-patterned recording
US9077349B2 (en) * 2012-02-21 2015-07-07 Qualcomm Incorporated Automatic detection and compensation of frequency offset in point-to-point communication
JP6135217B2 (ja) 2013-03-18 2017-05-31 富士通株式会社 信号補正装置、送信装置、信号補正方法、及び伝送システム
TWI598737B (zh) * 2017-01-20 2017-09-11 群聯電子股份有限公司 參考時脈訊號產生方法、記憶體儲存裝置及連接介面單元
CN116545818A (zh) * 2023-05-08 2023-08-04 上海米硅科技有限公司 一种应用于伪随机二进制序列的时钟数据对齐方法及装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003073280A1 (en) * 2002-02-26 2003-09-04 Advantest Corporation Measuring apparatus and measuring method
US7486894B2 (en) * 2002-06-25 2009-02-03 Finisar Corporation Transceiver module and integrated circuit with dual eye openers
JP3973502B2 (ja) * 2002-07-09 2007-09-12 Ｎｅｃエレクトロニクス株式会社 クロックデータリカバリー回路
JP4335586B2 (ja) * 2003-06-11 2009-09-30 Ｎｅｃエレクトロニクス株式会社 クロックアンドデータリカバリ回路
JP4651298B2 (ja) * 2004-04-08 2011-03-16 三菱電機株式会社 周波数自動補正ｐｌｌ回路
US7336755B1 (en) * 2004-06-08 2008-02-26 Xilinx, Inc. PLL with low phase noise non-integer divider
US7574146B2 (en) * 2004-07-09 2009-08-11 Infinera Corporation Pattern-dependent error counts for use in correcting operational parameters in an optical receiver
JP4657662B2 (ja) * 2004-09-10 2011-03-23 ルネサスエレクトロニクス株式会社 クロックアンドデータリカバリ回路
US7164322B1 (en) * 2005-07-21 2007-01-16 Agilent Technologies, Inc. Establishing a tuning signal window for use in centering a multi-band voltage controlled oscillator

Also Published As

Publication number Publication date
JP2008263509A (ja) 2008-10-30
US8199868B2 (en) 2012-06-12
US20080253494A1 (en) 2008-10-16

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