JP2008228971A - Random number generator and game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To change initial value at least for every prescribed count number, without putting a load on software, in a random number generation circuit of a hardware structure and to prevent random number value from being illegally acquired in the case of drawing executed depending on a game progress condition, without causing delay of game processing or deterioration of performance variation. <P>SOLUTION: By generating adjustment count value by a random number generator 300 of the hardware structure, a fraudulent practice is reduced. Since irregular value is added every time when the count value goes around, the initial value is made changeable under high speed count, and security for the fraudulent practice prevention can be strengthened. Since the initial value is changed in the random number generator 300, loads are not put on program processing by software of a main control unit 150 or performance variation of design fluctuation pattern performance is not degraded. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a random number generator for acquiring a random number based on a trigger signal and a gaming machine using the random number generator.

  Conventionally, in game machines, for example, pachinko machines, when a game ball wins a special symbol start winning opening provided on the game board surface, the winning / losing lottery (hereinafter referred to as “special symbol lottery”) is internally performed for control purposes. Executed.

  This special symbol lottery will be explained in more detail. The winning sensor detects that a game ball has won the start winning opening, acquires a random number from the random number counter at that time, and whether the acquired random number is a preset hit value. This is a process for determining whether or not.

  The result of the special symbol lottery corresponds to the special symbol by using a display device (generally an LCD (liquid crystal display device) is applied as a component of the center accessory) provided on the game board surface. The notification is performed by executing the symbol variation pattern effect by the effect symbol.

  As a result of this special symbol lottery, when winning a “bonus”, as a jackpot process, in a normal gaming state, the winning mouth that is always closed (may be called “big winning mouth”, “attacker”, etc.) is opened. A gaming state advantageous to the player (hereinafter referred to as “special gaming state”) is given.

  The big prize opening is generally opened for 30 seconds and then closed once for about 15 rounds (16 rounds at maximum). In addition, 10 game balls won during the opening of the attacker (the number of payouts by winning is 15), so it closes without waiting for 30 seconds and moves to the next round. In the special game state, about 150 winnings can be expected in a short time (the number of prize balls is about 2250).

  Thus, since the jackpot is a very advantageous gaming state for the player, the special symbol lottery needs to be strict.

  Generally, the random number counter is formed by software processing. Software processing means, for example, programming so that a predetermined count (1 count) is made every time a program loops. For example, if one cycle is 1024 counts, 3 counts are included in the count value. By setting a winning value of, a winning probability of about 1/350 can be obtained.

  By the way, in a so-called soft random number counter, one count is incremented from 2 msec to 4 msec (count value i ← i + 1). It is possible to perform a so-called fraudulent act such as adjusting the launch intensity so that the winning timing is reached.

  For this reason, by changing the initial value every time the count value makes one turn, the acquisition timing of the count value corresponding to the winning value is made random while maintaining the winning probability.

  On the other hand, in recent years, it has been proposed to provide a so-called hardware random number counter (random number generation circuit) instead of a so-called soft random number counter (see Patent Document 1, Patent Document 2, and Patent Document 3). Some of the above-mentioned patent documents 1 to 3 also disclose changing the initial value of the random number counter.

In a random number generation circuit configured by hardware, for example, when a 16-MHz counter is used with a 10 MHz count-up clock, one count (period T) is 10 ⁻⁷ sec (T = 1 / f: f = 10 MHz).

In addition, since the total number of counts is a 16-bit counter, 2 ¹⁶ = 65536 counts, and if the winning value is one of 65536 counts, the winning value is 6.5536 × 10 ^−3. It is a timing that appears periodically every sec (about 6 msec).

  In this way, even in a hardware-generated random number generation circuit that makes one round in about 6 msec, there is a possibility of timing and predicting the appearance timing of the winning value, so the initial value changes in the same way as a software random number counter. However, it is necessary to control the change of the initial value by software.

The number of winning values in one lap varies depending on the winning probability setting of lottery and the processing after obtaining the count value. However, in the above, at least one of the counters makes a winning value during one lap. Illustrated.
JP 2003-117125 A JP 2005-13764 A JP 2002-78945 A

  However, the control of changing the initial value for each round under a very high-speed count-up process, such as a hardware-configured random number counter, places a great burden on the software and is not practical.

In the above specific example, one count is 2 msec to 4 msec in software processing, but in hardware processing, one round is about 6 msec (1 count is 10 ⁻⁷ sec), and the processing speed is an order of magnitude. There is a difference.

  Further, even if the initial value change control by software can be realized, this burden will adversely affect the entire gaming machine, such as delays in other processes and reduction in production variations.

  In view of the above facts, the present invention provides a hardware random number generator capable of realizing a change in initial value at least for each predetermined count number in a hardware-structured random number generation circuit without burdening software. Is the purpose.

  In addition to the above purpose, a gaming machine capable of preventing illegal random value acquisition at the time of a lottery executed in accordance with the progress of the game without causing a delay in game processing or a reduction in production variation. Is the purpose.

  According to a first aspect of the present invention, a clock generation circuit for generating a reference clock having a predetermined period, and counting repeatedly up to a predetermined number based on the clock period generated by the clock generation circuit, and the predetermined number of counts A counter circuit for generating a carry signal every time, an irregular value generating circuit for generating an irregular numerical value based on the input timing of the carry signal from the counter circuit, a count value from the counter circuit, An addition circuit that generates an adjustment count value by adding the irregular value from the irregular value generation circuit, and the adjustment count value that is output from the addition circuit when a predetermined trigger signal is input And a latch circuit for latching.

According to the first aspect of the present invention, the clock generation circuit generates the reference clock. This reference clock has a predetermined period (frequency) (for example, about 10 ⁻⁷ sec (10 MHz)).

  Based on the clock cycle generated by the clock generation circuit, the counter circuit repeatedly counts up to a predetermined number. For example, if it is an 8-bit counter, 0 to 255 are repeatedly counted, and if it is a 16-bit counter, 0 to 65535 are repeatedly counted.

  The counter circuit generates a carry signal every predetermined number of counts (“255” → “0” in the case of 8 bits, “65535” → “0” in the case of 16 bits).

  This carry signal is input to the irregular value generation circuit. The irregular value generating circuit generates an irregular value based on the input timing of the carry signal from the counter circuit and outputs the irregular value to the adding circuit.

  On the other hand, the count value of the counter circuit is input to the adder circuit. For this reason, the count value and the irregular value are added. The added value (adjusted count value) has an initial value that changes every time the count in the counter circuit makes one round (the predetermined number of counts are completed), and does not regularly become the same count value. . As a result, it is possible to make it difficult to specify the adjustment count value to be latched according to the input of the trigger signal.

  The invention according to claim 2 is characterized in that, in the invention according to claim 1, the reference clock of the predetermined period is a period that cannot be counted by software processing.

According to the second aspect of the present invention, the count under the current software processing is 1 count / several milliseconds, and the count required by the present invention is a period that cannot be counted by this software processing, that is, 1 Faster than count / several msec. For example, it is 10 ⁻⁶ sec (1 MHz) or more, preferably about 10 ⁻⁷ sec (10 MHz).

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the total number of irregular values that can be generated by the irregular value generating circuit is the total number of maximum count values of the counter circuit. It is characterized by being identical.

  According to the third aspect of the invention, since the count values have the same number of digits, there is no biased adjustment count value.

  According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, the input timing of the trigger signal to the latch circuit is applied at a clock cycle of counting in the counter circuit. It is characterized in that it is synchronized with the inverted signal of the clock signal.

  According to the fourth aspect of the present invention, since the phase is inverted, the increment timing of the count value does not coincide with the acquisition timing of the adjustment count value based on the trigger signal, and the adjustment count value is erroneously acquired. Can be prevented.

  The invention according to claim 5 is a gaming machine to which the random number generator according to any one of claims 1 to 4 is applied, and is adjusted from the random number generator by using a start signal as a trigger signal. A count value is acquired, and a winning / losing lottery is performed by comparing the acquired adjusted count value with a winning value. When the winning / losing lottery result is winning, a predetermined jackpot processing is executed and the jackpot processing In this case, the condition relating to the winning / losing lottery after the next is displayed on the display device together with the effect image and is notified.

  According to the fifth aspect of the present invention, the start signal of the gaming machine is applied as the trigger signal, and the count value is compared with the winning value at the time of winning / losing lottery based on the start signal. By applying the adjustment count value generated by the random number generator according to any one of the items 4, it is possible to take a strong security measure against fraud.

  That is, it is possible to realize the double fraudulent difficulty that is a high-speed count process and a weekly initial value change under this high-speed count process.

  As described above, the present invention has an excellent effect that a change in the initial value can be realized at least every predetermined count number in a hardware-generated random number generation circuit without imposing a burden on software.

  In addition to the above effects, it is possible to prevent illegal random value acquisition at the time of a lottery executed in accordance with the progress of the game without causing a delay in game processing or a decrease in production variation. Have

(Configuration of pachinko machine)
As shown in FIGS. 1 and 2, a lower decoration 12 serving as a decorative panel is attached to the lower front portion of the pachinko machine 10.

  Further, a glass frame 16 fitted with a glass plate 14 is arranged on the upper part of the undergarment 12 of the pachinko machine 10, and the glass frame 16 is attached so that it can be opened and closed with its left end portion pivotally supported. On the back side of the glass frame 16, a rectangular opening is provided, and a game board 100 that can be replaced is set. The game board 100 is attached to the glass plate 14 with the glass frame 16 closed. It comes to oppose.

  Around the glass plate 14 in the glass frame 16, an indicator lamp 20 for lighting effect is generated to produce an effect effect by lighting by turning on, turning off and flashing according to the progress of the game. Speakers 22L and 22R for outputting sound effects in stereo are arranged.

  An integrated dish 24 is disposed below the glass frame 16. A firing handle 26 for adjusting the firing force (flying distance) of the hit ball is attached to the lower right portion of the integrated dish 24.

(Game board configuration)
FIG. 3 shows a game board 100 according to the present embodiment.

  The game board 100 is hereinafter referred to as a transparent game board 100 because a transparent flat synthetic resin material is applied as a substrate.

  In the transparent gaming board 100, an arc-shaped outer rail 102, a backflow prevention valve 103, and an inner rail 104 are attached in the vicinity of the outer peripheral end portion. A circular region surrounded by the outer rail 102, the backflow prevention valve 103 and the inner rail 104 is fired from a launching device (not shown) and jumps out of the discharge port 105 partitioned by the backflow prevention valve 103. The played game ball PB can be moved by its own weight drop, and this area is a game area 101 in which a game is played.

  On the back side of the transparent gaming board 100, a large liquid crystal display device (LCD) 200 having a display surface facing at least substantially the entire game area 101 is disposed. That is, the game area 101 is the display area 201 of the LCD 200, and almost the entire field of view of the player is covered.

  In the game area 101, a passing gate (through chucker) 118 is arranged on the left side of FIG. In addition, a special symbol start winning opening (start chucker) 108 is arranged at the lower part of FIG. 3, and further below the special symbol starting winning opening 108 is located near the lower end of the game area 101. Thus, an attacker 112 is arranged.

  The attacker 112 is provided with an opening / closing door 116, which opens or closes when the opening / closing door 116 is opened or closed. When the open / close door 116 is opened, the game ball dropped on the open / close door 116 is guided by the open / close door 116 and wins the attacker 112.

  In addition, the game area 101 is provided with a windmill 122 and a large number of game nails 123 that guide a game ball that falls by itself in the game area 101 to a predetermined route.

  Further, below the center of the transparent gaming board 100, a stage 124 is provided in which a path for the game ball PB is provided in the back side passage and the front side passage of the transparent gaming board 100. The game ball PB is a windmill 122. It is guided on the stage 124 by the game nail 123 or the like. The game ball PB guided on the stage 124 can easily win the special symbol start winning opening 108.

  Further, at the lowest position of the transparent game board 100, an out port 125 for discharging the off-ball to the back side of the transparent game board 100 is provided.

(Control system configuration)
Next, the control system of the pachinko machine 10 will be described with reference to FIG. As shown in FIG. 4, the control system of the pachinko machine 10 according to the present embodiment is configured around a main control unit 150. The main control unit 150 stores a basic program relating to games, and the operation of each unit is controlled based on a command signal from the main control unit 150.

  The main control unit 150 includes a start winning sensor 180 for detecting a winning ball to the special symbol starting winning port 108, a passing gate winning sensor 184 for detecting a winning ball to the passing gate 118 which is a normal symbol starting port, and a special game state. A big winning sensor 186 for detecting a winning ball to the attacker 112 that is opened at the time of the winning is connected to each of the sensors, and each of these sensors outputs a detection signal to the main control unit 150 when the winning ball is detected. If necessary, if there is a V zone in the attacker 112 that triggers the round of big hit processing, a V zone sensor 188 that detects that the V zone has been passed is arranged. Established.

  Further, a solenoid 174 for operating the electric tulip 110 and a solenoid 175 for opening / closing the opening / closing door 116 of the attacker 112 are connected to the main control unit 150. In addition, a holding lamp (not shown) indicating the number of holdings of special drawing lottery (described later) by the number of lighting is also connected to the main control unit 150.

  Here, when the game ball PB passes through the passing gate 118, the winning symbol winning sensor 184 detects this and the lottery of winning or losing the normal symbol (hereinafter referred to as “normal drawing lottery”) is sent to the main control unit 150. The lottery result is notified using the LCD 200, and when the winning is achieved, the main control unit 150 drives and controls the ordinary electric accessory solenoid 174 to open the electric tulip 110 for a predetermined time.

  Further, when the game ball PB wins the special symbol start winning port 108, the main winning part winning / losing lottery (special symbol lottery) is executed by the main control unit 150 by detecting this with the start winning sensor 180. The special drawing lottery is notified using the LCD 200, and in the case of winning, the main control unit 150 controls the game state to shift from the normal game state to the special game state as a big hit process.

  The special game state is a game state that is repeated for a plurality of rounds (generally 15 rounds) when the attacker 112 opens for a predetermined time (generally 30 seconds) and then closes the operation for one round. Many game balls PB win the attacker 112, and a lot of winnings can be expected. Normally, the maximum number of winnings in one round is limited to 10. During the jackpot process (special gaming state), the LCD 200 is used to execute an image effect having a series of stories that spans a plurality of rounds.

  Information (start winning signal, jackpot signal, symbol determination signal) indicating the progress of the game is transmitted from the main control unit 150 to the hall computer via the board external terminal 190.

  Furthermore, an effect control unit 152 and a payout control unit 154 are respectively connected to the main control unit 150, and these control units are controlled by command transmission from the main control unit 150.

  The LCD 200 is connected to the effect control unit 152 via the symbol control unit 156. Further, the effect control unit 152 controls lighting, extinction, and blinking of the light emitting elements 126 for lighting effects provided in various game components of the game board 100 and the indicator lamp 20 provided in the glass frame 16, Furthermore, the output of a sound effect etc. is controlled by operating the speakers 22L and 22R provided on the front surface of the glass frame 16.

  The LCD 200 controlled by the effect control unit 152 displays an effect video of a symbol variation pattern for informing the result of the special symbol lottery, and BGM at the time of the symbol variation pattern effect is output from the speakers 22L and 22R. The Thereby, the player can enjoy the production | presentation by the design symbol corresponding to the result of special drawing lottery through vision and hearing.

  Further, the payout control unit 154 is connected to the payout device 160 and the launch control unit 164, and the launch control unit 164 is connected to the launch device 40. The payout control unit 154 operates the payout device 160 provided in the pachinko machine 10 to control the payout and lending ball payout and stop operations and the number of payouts. Further, the launch control unit 164 activates the launch device 40 by operating the launch handle 26 (see FIG. 1) by the player to start launching the game ball PB and launch force according to the operation amount of the launch handle 39. To control.

  Further, the payout control unit 154 transmits payout information to the hall computer installed in the hall via the frame external terminal 191.

  Here, in the main control unit 150 of the present embodiment, as described above, the special symbol winning / losing lottery (special drawing lottery) is executed.

  In this special drawing lottery, the start winning sensor 180 detects that the pachinko ball PB has won the start winning opening 108, and the main control unit 150 acquires a random number of the input timing of the detection signal of the start winning sensor 180. Then, it is determined whether or not the winning value by comparing with the winning value.

  With respect to this random number acquisition, in the present embodiment, the main control unit 150 includes the random number generation device 300 as hardware. Actually, it is composed of a one-chip IC, is attached to a main control board (not shown) that constitutes the main control unit 150, and a random number (adjustment count) according to software program execution in the main control unit 150 Value) is output.

  In other words, the random number generator 30 itself operates independently regardless of the software program.

  FIG. 5 is a block diagram illustrating the hardware configuration of the random number generation device 300 including the one-chip IC, and will be described in detail.

  The reference clock is generated by the clock pulse oscillator 302 and the first D flip-flop circuit 304. In this embodiment, the clock pulse oscillator 302 outputs a 20 MHz clock. The output terminal 302A of the clock pulse oscillator 302 is connected to the CLK terminal 304A of the first D flip-flop circuit 304, and inputs the clock signal (20 MHz) to the first D flip-flop circuit 304.

  The first D flip-flop circuit 304 divides the input clock signal by 1/2 to generate a clock signal (10 MHz), outputs the clock signal from the Q terminal 304B, and inverts the clock signal (reference clock). Signal) is output from the Qr terminal 304C. The Qr terminal 304C is connected to the D terminal 304D to realize the 1/2 frequency division.

The Qr terminal 304C is connected to the count clock terminal 306A of the n-bit counter 306. The n-bit counter 306 of this embodiment is applied with n = 16, that is, a 16-bit counter, and repeatedly counts 65536 (= 2 ¹⁶ ) as a predetermined number by 16-digit bit data (0 to 0). 65535).

  The n-bit counter 306 is provided with a Cn terminal group (n is 1 to 16) 306B, and the count value is output from the Cn terminal group 306B.

  The Cn terminal group 306B is connected to the Bn terminal group 308B of the n-bit adder 308. As a result, the count value in the n-bit counter 306 is input to the n-bit adder 308.

  The n-bit counter 308 is provided with a carry terminal 306C. A carry signal is output from the carry terminal 306C every time the count value makes one round (each time the digit is reset from 1111111111111111 to 0000000000000000).

  The carry terminal 306C is connected to the irregular value output instruction terminal 310A of the n-bit random number generator 310.

The n-bit random number generator 310 generates a numerical value (irregular value) randomly from n = 16, that is, 16-digit bit data (65536 (= 2 ¹⁶ )), and has no periodicity.

  Here, the n-bit random number generator 310 outputs an irregular value when the carry signal is input to the irregular value output instruction terminal 310A from the Rn terminal group (n is 1 to 16) 310B.

  The Rn terminal group 310B is connected to the An terminal group (n is 1 to 16) 308A of the n-bit adder 308, and the irregular value is input to the n-bit adder.

  That is, the n-bit adder 308 always receives a count value from the n-bit counter 306 (Bn terminal group 308B) and receives an irregular value from the n-bit random number generator 310 as appropriate (An terminal group 308A). The n-bit adder 308 always adds these to generate an adjustment count value.

  In other words, since an irregular value is added to the adjustment count value every time the basic count value is reset, the initial value is changed every 65536 counts.

  The n-bit adder 308 outputs an output terminal group Yn (n is 0 to 16) for outputting an adjusted count value that is an addition value of the irregular value of the An terminal group 308A and the count value of the Bn terminal group 308B. 308C, which are connected to the Dn terminal group (n is 0 to 16) 312A of the n-bit latch circuit 312 respectively.

  The n-bit latch circuit 312 is provided with an output clock terminal 312B.

  The output clock terminal 312B is connected to the Q terminal 314A of the second D flip-flop circuit 314. An output signal from the Q terminal 304B of the first D flip-flop circuit 304 is input to the CLK terminal 314B of the second D flip-flop circuit 314. This is an inverted signal of the reference clock signal sent from the Qr terminal 304B of the first D flip-flop circuit 304 to the n-bit counter 306.

  Also, a winning signal 180A based on the detection signal of the starting winning sensor 180 shown in FIG. 4 is input to the D terminal 314C of the second D flip-flop circuit 314.

  That is, in the second D flip-flop circuit 314, when a winning signal is input to the D terminal 314C, an output signal is output from the Q terminal 314A in synchronization with the inverted signal input to the CLK terminal 314B. It has become.

  Here, in the n-bit latch circuit 312, when an output signal is input from the second D flip-flop circuit 314 to the output clock terminal 312B, a Dn terminal group (n is 0 to 16) at the time of input. The adjustment count value input and latched from 312A is output from the Qn terminal group (n is 0 to 16) 312C. The Qn terminal group 312B is input to an In terminal group (n is 0 to 16) 150B set in the CPU 150A constituting a part of the main control unit 150 (see FIG. 4).

  Note that the reference clock signal, which is the synchronization signal of the count processing in the n-bit counter 306, is synchronized with the inverted signal of the winning signal so that the winning signal does not overlap when the count value is incremented, and the adjusted count value This is to prevent erroneous acquisition of.

  By using the random number generation device 300 having the above hardware configuration, in addition to high-speed counting processing, even if high-speed counting is performed, an initial value is set for each cycle without imposing a burden on software execution in the main control unit 150. It is possible to change.

  The operation of this embodiment will be described below.

(Game flow of the pachinko machine 10 (refer to the flowchart of FIG. 6))
In the game using the pachinko machine 10, when the player operates the launch handle 26, the ball is supplied to the launch device 40 (see FIG. 4) one by one and is launched upward by the launch device 40. The launched game ball PB is driven into the game area 101 of the game board 100 along the outer rail 102 and falls in the game area 101 while changing the direction by hitting the game nail 123. Then, the game ball PB that has reached the lower end of the game area 101 without winning a prize is collected into the pachinko machine 10 from the out port 125.

  Here, when a special symbol start winning opening 108 is won, the start winning sensor 180 detects this and outputs a detection signal to the main control unit 150.

  The main control unit 150 determines that a start winning has been made based on a detection signal from the start winning sensor 180 (affirmative determination in step 350), and a special symbol winning / losing lottery (special drawing lottery processing) is executed. (Lottery process in step 352).

  The special drawing lottery result is displayed in a special pattern for effect variation on the LCD 200 in a predetermined pattern, and is stopped and displayed after the variation pattern (design variation pattern effect display control in step 354).

(Big jackpot processing)
In the special symbol lottery, when a big hit is made as a notification of the lottery result (design variation pattern production) (affirmative determination in step 356), a predetermined area such as “444” or “777” is set in advance in the display area of the LCD 200. A combination of a predetermined jackpot symbol is displayed, and a player is informed that a jackpot has occurred by adding effects such as blinking of the indicator lamp 20 for lighting effects and output of sound effects from the speakers 22L and 22R. A predetermined jackpot process is executed (step 358). In the case of losing (negative determination in step 356), the game returns to the normal game.

  As the jackpot processing, the attacker 112 is opened by, for example, 10 counts (winning number) or a maximum of 30 seconds (one open time) / a maximum of 15 or 16 rounds by the opening / closing operation of the door 116.

  In the case of a game specification in which a V zone is provided in the attacker 112, an operation of continuing the next round by performing winning in the V zone when the attacker 112 is released once is performed.

  Accordingly, the player can easily win a lot of prize balls by, for example, receiving 15 payouts per winning prize, for example, by making the released gaming balls PB win the attacker 112 easily.

  FIG. 7 shows details of the lottery process in step 352 of FIG.

  In step 360, the adjustment count value is acquired from the random number generator 300, and then in step 362, the winning value is read, and the process proceeds to step 364 to compare the two.

  In step 366, based on the comparison result in step 364, a command to each unit is output, and this routine ends.

  Next, according to the timing chart of FIG. 8, a signal flow in the random number generation device 300 according to the present embodiment will be described.

  The clock pulse oscillator 302 outputs a 20 MHz clock, and sends it to the CLK terminal 304A of the first D flip-flop circuit 304, which divides the frequency by 1/2 to generate a reference clock signal (10 MHz).

  As a result, a clock signal is output from the Q terminal 304B, and an inverted signal (reference clock signal) of the clock signal is output from the Qr terminal 304C.

In the n-bit counter 306, n = 16, that is, a 16-bit counter is applied, and the number of 65536 (= 2 ¹⁶ ) is repeatedly counted as a predetermined number by 16-digit bit data (0000000000000000 → 0000000000000001 → 0000000000000010). → 0000000000000011 → ・ ・ ・ 1111111111111110 → 1111111111111111 → 0000000000000000 → 0000000000000001 → ...). The count value is output from the Cn terminal group 306B to the n-bit adder 308.

  When a carry signal is output from the n-bit counter 306, the n-bit random number generator 310 outputs an irregular value at the time when the carry signal is input from the Rn terminal group 310B.

  As a result, the count value is always input from the n-bit counter 306 (Bn terminal group 308B) to the n-bit adder 308, and irregular values are appropriately input from the n-bit random number generator 310 (An terminal group 308A). These are always added to generate an adjustment count value.

  As a result, since the irregular value is added to the adjustment count value every time the basic count value is reset, the initial value changes every 65536 counts.

  The adjustment count value is output to the n-bit latch circuit 312, and when the winning signal 180A based on the detection signal of the start winning sensor 180 is input to the n-bit latch circuit 312, the adjustment count latched at the time of input. The value is output from the Qn terminal group (n is 0 to 16) 312C.

  The adjustment count value output from the Qn terminal group 312C corresponds to the adjustment value acquisition in step 360 of FIG.

  Here, the reference clock signal, which is the synchronization signal for the counting process in the n-bit counter 306, is synchronized with the inverted signal of the winning signal. This is a measure for preventing the winning signals from overlapping when the count value is incremented, thereby preventing erroneous acquisition of the adjustment count value.

  As described above, in the present embodiment, since the random number (adjusted count value) is generated by the hardware-configured random number generator 300, the random number (adjusted count value) is acquired under the high-speed count process. And this alone can reduce fraud. However, in the present embodiment, the random number generation device 300 with this hardware configuration is configured to add an irregular value every time the base count value makes one round, so that under a high-speed count (here, 10 MHz) The initial value can be changed, and security for preventing fraud can be further strengthened. Moreover, since the initial value change is performed in the random number generation device 300, there is no burden on the program processing by the software of the main control unit 150.

  For this reason, for example, there is no adverse effect on other processing such as reducing the production variation of the symbol variation pattern effect.

  Further, the adjustment count value input to the CPU of the main control unit 150 has been described as 16 bits. However, when the number of input bits to the CPU of the main control unit 150 is limited for some reason (for example, up to 8 bits). The upper 8 digits and the lower 8 digits of the 16-bit adjustment count value may be separated and transferred serially or in parallel.

  Furthermore, in the present embodiment, the number of bits handled (n bits) is 16 bits, but other numbers of bits such as 8 bits may be used. The n values (number of bits) of the n-bit counter 306, the n-bit random number generator 310, the n-bit adder 308, and the n-bit latch circuit 312 do not necessarily match.

It is a front view which shows the pachinko machine which concerns on this Embodiment. It is a perspective view which shows the pachinko machine concerning this Embodiment. It is a front view which shows the game board which concerns on this Embodiment. It is a block diagram which shows schematic structure of the control system of the pachinko machine concerning this Embodiment. It is a schematic block diagram of the random number generator which concerns on this Embodiment. It is a control flowchart explaining the flow of the game of the gaming machine according to the present embodiment. It is a control flowchart which shows the lottery process subroutine in step 352 of FIG. It is a timing chart which shows the flow of the signal of the random number generator which concerns on this Embodiment.

Explanation of symbols

PB game ball 10 Pachinko machine 26 Launch handle 100 Game board 108 Special symbol start prize opening 110 Electric tulip 112 Attacker 150 Main controller 150A CPU
150B In terminal group 152 Production control unit 154 Payout control unit 156 Symbol control unit 180 Start winning sensor 180A Winning signal 200 Liquid crystal display device (display device)
300 random number generator 302 clock pulse generator (clock generation circuit)
304 1st D flip-flop circuit (clock generation circuit)
306 n-bit counter (counter circuit)
308 n-bit adder (adder circuit)
310 n-bit random number generator (irregular value generator)
312 n-bit latch circuit (latch circuit)
314 Second D flip-flop circuit

Claims (5)

A clock generation circuit for generating a reference clock having a predetermined period;
A counter circuit that repeatedly counts up to a predetermined number based on a clock cycle generated by the clock generation circuit and generates a carry signal for each predetermined number of counts;
An irregular value generating circuit for generating an irregular numerical value based on the input timing of the carry signal from the counter circuit;
An adding circuit for generating an adjusted count value by adding the count value from the counter circuit and the irregular value from the irregular value generating circuit;
A latch circuit that latches the adjustment count value output from the adder circuit when a predetermined trigger signal is input;
Random number generator.   2. The random number generator according to claim 1, wherein the reference clock having the predetermined period is a period that cannot be counted by software processing.   3. The random number generator according to claim 1, wherein the total number of irregular values that can be generated by the irregular value generation circuit is the same as the total number of maximum count values of the counter circuit.   4. The input timing of the trigger signal to the latch circuit is synchronized with an inverted signal of a clock signal applied at a count clock period in the counter circuit. Random number generator. A gaming machine to which the random number generator according to any one of claims 1 to 4 is applied,
When a start signal is used as a trigger signal, an adjustment count value is acquired from the random number generator, and a winning / losing lottery is performed by comparing the acquired adjusting count value with a winning value. A game machine characterized in that a predetermined jackpot process is executed at the same time, and a condition related to the next winning / losing lottery is displayed on a display device together with an effect image during the jackpot process.

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