JP2008227525A - Method for manufacturing silicon wafer with no aggregate of point defect - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow a uniform gettering effect to be obtained in a wafer plane even if a silicon wafer is cut from an ingot including a perfect region (P). <P>SOLUTION: The silicon wafer is manufactured by forming a polysilicon layer having a thickness of 0.1 to 1.6 μm on the backside of a mirror plane silicon wafer after drawing up the ingot adding pure carbon to a polycrystal silicon raw material so as to provide the carbon concentration in the ingot with 1 to 5×10<SP>15</SP>/cm<SP>3</SP>, and by controlling V/G(mm<SP>2</SP>/min°C) so as to provide the oxygen concentration in the ingot with 1×10<SP>18</SP>to 1.45×10<SP>18</SP>/cm<SP>3</SP>(old ASTM), and also include both a region (P<SB>V</SB>) and a region (P<SB>I</SB>) with an area ratio of region (P<SB>V</SB>)/region (P<SB>I</SB>) at about 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention is Czochralski method (hereinafter, referred to as CZ method.) Made by a method of manufacturing a silicon wafer used for manufacturing semiconductor integrated circuits. More particularly, the present invention relates to a method for manufacturing a silicon wafer having a gettering source and free of agglomerates of point defects.

  In recent years, in the process of manufacturing a semiconductor integrated circuit, as a cause of decreasing the yield, microscopic defects of oxygen precipitates that are the core of oxidation-induced stacking faults (hereinafter referred to as OSF) and particles caused by crystals (Crystal Originated Particles, hereinafter referred to as COP) or the presence of interstitial-type large dislocation (hereinafter referred to as LD). OSF is introduced with a micro defect that becomes a nucleus at the time of crystal growth, and becomes apparent in an oxidation process or the like when manufacturing a semiconductor device, and causes a defect such as an increase in leakage current of the manufactured device. When the mirror-polished silicon wafer is washed with a mixture of ammonia and hydrogen peroxide, pits are formed on the wafer surface. When this wafer is measured with a particle counter, the pits are detected as particles together with the original particles. The pits are caused by crystals and are called COPs to distinguish them from the original particles. COPs that are pits on the wafer surface cause deterioration of electrical characteristics such as oxide dielectric breakdown characteristics (Time Dependent Dielectric Breakdown (TDDB), oxide breakdown voltage characteristics (Time Zero Dielectric Breakdown, TZDB). Further, if COP exists on the wafer surface, a step is generated in the device wiring process, and this step causes disconnection and lowers the product yield. Furthermore, LD is also called a dislocation cluster, or a pit is formed when a silicon wafer having such a defect is immersed in a selective etching solution containing hydrofluoric acid as a main component.

From the above, it is necessary to reduce OSF, COP and LD from a silicon wafer used for manufacturing a semiconductor integrated circuit.
The OSF, are shown a silicon wafer is opened defect-free having no COP and LD (e.g., see Patent Document 1.). This defect-free silicon wafer has a perfect region [P] where a perfect region where agglomerates of vacancy-type point defects and agglomerates of interstitial silicon-type point defects do not exist in a silicon single crystal ingot, respectively. P] is a silicon wafer cut out from an ingot. The perfect region [P] is between a region [I] where interstitial silicon type point defects exist predominantly and a region [V] where hole type point defects exist predominantly within the silicon single crystal ingot. Intervene.
On the other hand, among semiconductor device manufacturers, there is a manufacturer that does not have OSF, COP, and LD, and that requires a silicon wafer that has the ability to getter the contamination generated in the device process. In a wafer that does not have sufficient gettering capability, a junction leak or the like occurs due to contamination in the device process, thereby reducing the product yield.
Japanese Patent Application Laid-Open No. 11-1393

However, among silicon wafers cut out from the ingot consisting of the perfect region [P], a wafer having a relatively low vacancy-type point defect concentration causes uniform oxygen precipitation in the wafer surface during the heat treatment in the device process. In this case, the gettering effect may not be sufficiently obtained.
An object of the present invention is to provide a method of manufacturing a silicon wafer that can obtain a uniform gettering effect within the wafer surface even if it is a silicon wafer cut out from an ingot consisting of a perfect region [P]. .

According to the first aspect of the present invention, a perfect region [P] is obtained by adding pure carbon to a polycrystalline silicon raw material , melting the raw material , and controlling V / G (mm ² / min · ° C.) from the silicon melt . After pulling up the silicon single crystal ingot composed of the above, lapping the silicon wafer cut out from the ingot composed of the perfect region [P], chamfering, and then removing the damage on the wafer surface by chemical etching treatment. In the method for producing a mirror-surface silicon wafer having no aggregate, the pure carbon is added to the polycrystalline silicon raw material so that the carbon concentration in the ingot is 1 to 5 × 10 ¹⁵ / cm ³ , The oxygen concentration is 1 × 10 ^{18 to} 1.45 × 10 ¹⁸ / cm ³ (former ASTM) , and the region [P _V ] and the region [P _I The ingot is pulled up by controlling the V / G (mm ² / min · ° C.) so that the area [P _V ] / area [P _I ] is about 1 in area ratio. A silicon wafer is manufactured by forming a polysilicon layer having a thickness of 0.1 to 1.6 μm on the back surface of the silicon wafer. The manufactured silicon wafer is heat-treated at 800 ° C. for 4 hours in an oxygen atmosphere, and then at 1000 ° C. Heat treatment 16 hours, the wafer in which oxygen precipitates ^{1 × 10 8 / cm 3 ~} 1 × 10 11 / cm 3 is produced in both the near half the radius of the wafer center and the wafer at a depth of 300μm from the wafer surface it characterized in that it is.
V of V / G is the ingot pulling speed (mm / min), G is the temperature gradient (° C./mm) of the contact surface of the ingot-silicon melt, and the perfect region [P] is pulled up. When a region where interstitial silicon type point defects exist predominantly in a silicon single crystal ingot is [I] and a region where vacancy type point defects exist predominantly is [V], the interstitial silicon type refers to a region where the aggregate is not present in the aggregates and vacancy type point defects of the point defect, the area [P _I] is between the lowest lattice capable of forming a contiguous, and interstitial dislocation in the region [I] This refers to a region having an interstitial silicon type point defect concentration less than the silicon type point defect concentration, and the region [P _V ] is adjacent to the region [V] and can form an oxidation-induced stacking fault. a region having a vacancy type point defect concentration below the point defect concentration Cormorant.

According to the present invention, realm [P _V] / area [P _I] to is about 1 in area ratio, comprising a carbon concentration in the wafer higher than usual CZ wafer 1~5 × 10 ¹⁵ / cm ³ and a polysilicon layer having a thickness of 0.1~1.6μm in wafer backside while controlled respectively so that the oxygen concentration ^{1 × 10 18 ~1.45 × 10 18} / cm 3 ( old ASTM) Thus, even if the wafer is rich in the region [P _I ], that is, the wafer is rich in interstitial silicon type point defects rather than vacancy type point defects, the wafer is heat-treated at 800 ° C. for 4 hours in an oxygen atmosphere. Then, if heat treatment is performed at 1000 ° C. for 16 hours, oxygen precipitates are formed on all surfaces of the wafer, and a uniform intrinsic gettering effect with no variation between the wafer periphery and the wafer center can be obtained.

The silicon wafer of the present invention is produced by slicing an ingot from a silicon melt in a hot zone furnace with a predetermined pulling speed profile based on Boronkov theory by the CZ method.
In general, when a silicon single crystal ingot is pulled from a silicon melt in a hot zone furnace by the CZ method, point defects and agglomerates (agglomerates: three-dimensional) Defect) occurs. There are two general forms of point defects: vacancy-type point defects and interstitial silicon-type point defects. A vacancy-type point defect is one in which one silicon atom leaves one of the normal positions in the silicon crystal lattice. Such holes become hole-type point defects. On the other hand, when an atom is found at a position (interstitial site) other than the lattice point of the silicon crystal, this becomes an interstitial silicon point defect.

  Point defects are generally formed at the contact surface between a silicon melt (molten silicon) and an ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface begins to cool as it is pulled up. During cooling, vacancy point defects or interstitial silicon point defects merge with each other by diffusion to form vacancy agglomerates or interstitial agglomerates. Is formed. In other words, the aggregate is a three-dimensional structure generated due to the merge of point defects. The agglomerates of vacancy-type point defects include defects called LSTD (Laser Scattering Tomograph Defects) or FPD (Flow Pattern Defects) in addition to the above-mentioned COP. Contains a defect called. FPD is a source of traces that exhibit a unique flow pattern that appears when a silicon wafer produced by slicing an ingot is chemically etched with a Secco etchant for 30 minutes. This is a source having a refractive index different from that of silicon when irradiated with infrared rays.

Boronkov's theory is that in order to grow a high-purity ingot with a small number of defects, the ingot pulling speed is V (mm / min), and the temperature gradient at the contact surface of the ingot-silicon melt is G (° C. in a hot zone structure. / Mm), V / G (mm ² / min · ° C.) is controlled. In this theory, as shown in FIG. 1, V / G is taken as the horizontal axis, and V / G and point defect concentration are set to the same vertical axis for the vacancy type point defect concentration and the interstitial silicon type point defect concentration. The relationship is represented schematically, and it is explained that the boundary between the void region and the interstitial silicon region is determined by V / G. More specifically, an ingot having an increased vacancy point defect concentration is formed when the V / G ratio is higher than the critical point, whereas an ingot having an increased interstitial silicon point defect concentration is formed when the V / G ratio is lower than the critical point. It is formed. In FIG. 1, [I] indicates a region where an interstitial silicon type point defect is dominant and an interstitial silicon type point defect exists ((V / G) ₁ or less), and [V] indicates an ingot. The vacancy-type point defect is dominant and indicates a region ((V / G) ₂ or more) where the vacancy-type point defect aggregate exists, [P] A perfect region ((V / G) ₁ to (V / G) ₂ ) in which an aggregate of interstitial silicon type point defects does not exist is shown. In the region [V] adjacent to the region [P], there are regions ((V / G) ₂ to (V / G) ₃ ) that form OSF nuclei.

The perfect region [P] is further classified into a region [P _I ] and a region [P _V ]. [P _I ] is a region where the V / G ratio is from the above (V / G) ₁ to the critical point, and [P _V ] is a region where the V / G ratio is from the critical point to the above (V / G) _2. is there. That is, [P _I ] is a region adjacent to the region [I] and having an interstitial silicon type point defect concentration lower than the lowest interstitial silicon type point defect concentration capable of forming interstitial dislocations, and [P _V]. ] Is a region adjacent to the region [V] and having a vacancy-type point defect concentration lower than the lowest vacancy-type point defect concentration capable of forming an OSF.

The predetermined pulling rate profile of the present invention shows that when the ingot is pulled from the silicon melt in the hot zone furnace, the ratio of the pulling rate to the temperature gradient (V / G) indicates the formation of agglomerates of interstitial silicon type point defects. The first critical ratio to be prevented ((V / G) ₁ ) or higher, and the agglomeration of vacancy-type point defects is limited to a region where the vacancy-type point defects in the center of the ingot are dominantly present. It is determined so as to be maintained below the two critical ratio ((V / G) ₂ ).

  The profile of the pulling speed is determined based on the above-mentioned Boronkov theory by simulation by experimentally slicing the reference ingot in the axial direction, or by combining these techniques. That is, this determination is made by checking the axial slice of the ingot and the sliced wafer after the simulation, and further repeating the simulation. For the simulation, a plurality of types of pulling speeds are determined within a predetermined range, and a plurality of reference ingots are grown. As shown in FIG. 2, the pulling speed profile for the simulation is from a high pulling speed (a) such as 1.2 mm / min to a low pulling speed (c) of 0.5 mm / min and again a high pulling speed (d) Adjusted to The low pulling speed may be 0.4 mm / min or less, and the change in pulling speeds (b) and (d) is preferably linear.

  A plurality of reference ingots pulled at different speeds are sliced in the axial direction. The optimal V / G is determined from the correlation between the axial slice, wafer verification and simulation results, and then the optimal pulling speed profile is determined and the ingot is manufactured with that profile. The actual pull rate profile will depend on many variables including, but not limited to, the desired ingot diameter, the particular hot zone furnace used and the quality of the silicon melt.

Drawing the cross-sectional view of the ingot when V / G is continuously reduced by gradually reducing the pulling speed, the fact shown in FIG. 3 can be seen. FIG. 3 shows a region [V] in which vacancy type point defects exist predominantly in the ingot [V], a region in which interstitial silicon type point defects exist predominantly [I], and vacancy type point defects. A perfect region where no agglomerates and no agglomerates of interstitial silicon type point defects exist is indicated as [P]. As shown in FIG. 3, the axial position P ₁ of the ingot includes a region where a vacancy-type point defect exists predominantly in the center. The position P ₃ includes a ring region in which an interstitial silicon type point defect exists dominantly and a perfect region in the center. Further, the position P ₂ is a perfect region because there is no aggregate of void type point defects in the center related to the present invention and no aggregate of interstitial silicon type point defects in the edge portion.

As is apparent from FIG. 3, the wafer W ₁ corresponding to the position P ₁ includes a region where a vacancy-type point defect exists predominantly in the center. The wafer W ₃ corresponding to the position P ₃ includes a ring in which interstitial silicon type point defects exist predominantly and a central perfect region. Further, the wafer W ₂ corresponding to the position P ₂ is a wafer according to the present invention, and there is no agglomeration of vacancy type point defects in the center and no agglomeration of interstitial silicon type point defects at the edge part. Perfect area. A slight region ((V / G) ₂ to (V / G) _{3 in} FIG. 1) in contact with the perfect region of the region where the vacancy-type point defects exist dominantly generates COP and LD within the wafer surface. It is an area that is not. However, this silicon wafer W ₁ was heat-treated at a temperature of 1000 ° C. ± 30 ° C. for 2 to 5 hours in an oxygen atmosphere according to the conventional OSF clarification heat treatment, and subsequently ₁ to 1130 ° C. ± 30 ° C. Heat treatment for 16 hours produces OSF. As shown in FIG. 4, OSF ring is generated in the vicinity of half the radius of the wafer W ₁ in the wafer. COP tends to appear in the region where the vacancy-type point defects surrounded by the OSF ring are dominant.

As described above, when the area [P _V ] / area [P _I ] of the silicon wafer of the present invention is about 1, the vacancy-type point defect concentration is low. The oxygen concentration is controlled to be 5 × 10 ¹⁵ / cm ³ and the oxygen concentration is 1 × 10 ^{18 to} 1.45 × 10 ¹⁸ / cm ³ (former ASTM). A polysilicon layer having a thickness of 1 to 1.6 μm is formed. By performing the above control and processing, even if the vacancy point defect concentration is low, oxygen precipitates are formed by a predetermined heat treatment, and the wafer has a uniform intrinsic gettering effect. This predetermined heat treatment is, for example, wafer heat treatment in the device manufacturing process. For example, after heat treatment at 800 ° C. for 4 hours in a nitrogen or oxygen atmosphere, heat treatment is performed at 1000 ° C. for 16 hours in a nitrogen or oxygen atmosphere.

The carbon concentration in the wafer is controlled by adding pure carbon when melting polycrystalline silicon based on the CZ method so that the carbon concentration [Cs] in the ingot becomes 1 to 5 × 10 ¹⁵ / cm ^3. To be done. When the carbon concentration is less than 1 × 10 ¹⁵ / cm ³ , the intrinsic gettering effect is poor, and when it exceeds 5 × 10 ¹⁵ / cm ³ , excessive precipitation of oxygen precipitation nuclei occurs during a predetermined heat treatment, resulting in excessive oxygen precipitates. There is a bug.
Further, the polysilicon layer on the back surface of the wafer is formed at 650 ° C. ± 30 ° C. by using, for example, SiH ₄ on the back surface of the silicon wafer produced by slicing the ingot pulled up under the above conditions by using a CVD (Chemical Vapor Deposition) method. The polysilicon layer is formed at a temperature of 0.1 to 1.6 μm, preferably 0.5 to 1.0 μm. If the thickness of the polysilicon layer is less than 0.1 μm, the intrinsic gettering effect is poor, and if it exceeds 1.6 μm, the productivity decreases. In addition, the oxygen concentration in the silicon wafer of the present invention is controlled to 1 × 10 ^{18 to} 1.45 × 10 ¹⁸ / cm ³ (former ASTM).

Next, examples of the present invention will be described together with comparative examples.
<Example 1>
Pure carbon is added to the raw material polycrystalline silicon to melt it, and the total length of the ingot from this silicon melt corresponds to the position P ₂ shown in FIG. 3, and V / G shown in FIG. The ingot was pulled up so that it entered the region of V / G) ₁ or more and (V / G) ₂ or less and the region [P _V ] / region [P _I ] was about 1 in area ratio. The silicon wafer sliced from the pulled ingot was lapped and chamfered, and then the wafer surface was damaged by chemical etching to obtain a mirror silicon wafer. A polysilicon layer having a thickness of 1.0 μm was formed at 650 ° C. on the back surface of the mirror silicon wafer by CVD using SiH ₄ . Thereafter, mirror polishing was performed to obtain a silicon wafer.
<Example 2>
A mirror wafer was obtained in the same manner as in Example 1 except that the amount of pure carbon added to the raw material polycrystalline silicon was increased.
<Example 3>
A mirror wafer was obtained in the same manner as in Example 1 except that the thickness of the polysilicon layer on the back surface of the wafer was 1.5 μm.
<Example 4>
A mirror wafer was obtained in the same manner as in Example 2 except that the thickness of the polysilicon layer on the back surface of the wafer was changed to 1.5 μm.

<Comparative Example 1>
The total length of the ingot corresponds to the position P ₂ shown in FIG. 3, and the V / G shown in FIG. 1 enters the region not less than the critical point (V / G) _{2 and not} less than the region [P _V ] / The ingot was pulled up so that the region [P _I ] was about 1 in area ratio. The silicon wafer sliced from the pulled ingot was lapped and chamfered, and then the wafer surface damage was removed by chemical etching to obtain a mirror wafer.
<Comparative example 2>
The amount of pure carbon added to the raw material polycrystalline silicon was larger than that in Comparative Example 1, and a polysilicon layer was formed to a thickness of 1.0 μm on the back surface of the wafer in the same manner as in Example 1. Otherwise, a mirror wafer was obtained in the same manner as in Comparative Example 1.

<Comparative Example 3>
A mirror wafer was obtained in the same manner as in Comparative Example 2 except that the thickness of the polysilicon layer on the back surface of the wafer was 1.5 μm.

<Comparison evaluation>
The carbon concentration in each silicon wafer of Examples 1 to 4 and Comparative Examples 1 to 3 was measured by charged particle activation analysis, and the oxygen concentration in the wafer was measured by Fourier transform infrared spectroscopy (FT-IR). Further, each wafer was heat-treated at 800 ° C. for 4 hours in an oxygen atmosphere, and then heat-treated at 1000 ° C. for 16 hours in an oxygen atmosphere. After the heat treatment, each wafer is cleaved, and the wafer surface is further selectively etched with a Wright etchant. By observation with an optical microscope, the wafer center at a depth of 300 μm from the wafer surface and 1 / of the radius of the wafer. The density of oxygen precipitates (Bulk Micro Defect, hereinafter referred to as BMD) in the vicinity of 2 was measured. These results are shown in Table 1.

As is evident from Table 1, 1 after heat treatment of the silicon wafer, in both near half the radius of the center of the wafer in Comparative Examples 1 to 3 and the wafer, BMD density is that there is intrinsic gettering effect While the silicon wafers of Examples 1 to 4 did not fall within the range of × 10 ⁸ / cm ³ to 1 × 10 ¹¹ / cm ³ , both in the wafer central portion and in the vicinity of ½ of the wafer radius, The BMD density was in the range of 1 × 10 ⁸ / cm ³ to 1 × 10 ¹¹ / cm ³ , which is considered to have an intrinsic gettering effect.

The figure which shows that a void | hole rich ingot is formed when a V / G ratio is more than a critical point based on the Boronkov theory, and an interstitial silicon rich ingot is formed when a V / G ratio is below a critical point. The characteristic view which shows the change of the pulling speed for determining a desired pulling speed profile. FIG. 3 is a schematic diagram of an X-ray topography showing a region where vacancies are dominant in a reference ingot according to the present invention, a region where interstitial silicon is dominant and a perfect region. It shows a situation where the OSF ring appears to the silicon wafer W ₁ corresponding to the position P ₁ in FIG.

Claims (1)

By adding pure carbon to polycrystalline silicon raw material, melting the raw material and controlling V / G (mm ² / min · ° C) from this silicon melt , pulling up the silicon single crystal ingot consisting of perfect region [P] , it was subjected to lapping chamfered silicon wafer cut out from an ingot consisting of the perfect region [P], a mirror silicon wafer aggregates absence of point defects to remove the damage of the wafer surface by chemical etching In the manufacturing method ,
The pure carbon is added to the polycrystalline silicon raw material so that the carbon concentration in the ingot is 1 to 5 × 10 ¹⁵ / cm ^3, and the oxygen concentration in the ingot is 1 × 10 ^{18 to} 1.45 × 10. ¹⁸ / cm ³ so that the (old ASTM), and the area [P _V] and region area consists both _{[P I] [P V]} / area [P _I] as of about 1 in area ratio Pulling up the ingot by controlling the V / G (mm ² / min · ° C.),
A silicon wafer is manufactured by forming a polysilicon layer having a thickness of 0.1 to 1.6 μm on the back surface of the mirror silicon wafer ,
The manufactured silicon wafer was heat-treated at 800 ° C. for 4 hours in an oxygen atmosphere and then heat-treated at 1000 ° C. for 16 hours, and 1 at both the wafer center at a depth of 300 μm from the wafer surface and about half the radius of the wafer. A method for producing a silicon wafer free from agglomerates of point defects, wherein the wafer is one in which oxygen precipitates of 10 ⁸ / cm ³ to 1 × 10 ¹¹ / cm ³ are formed .
V of V / G is the ingot pulling speed (mm / min), G is the temperature gradient (° C./mm) of the contact surface of the ingot-silicon melt, and the perfect region [P] is pulled up. When a region where interstitial silicon type point defects exist predominantly in a silicon single crystal ingot is [I] and a region where vacancy type point defects exist predominantly is [V], the interstitial silicon type This refers to a region where no point defect aggregates and no vacancy type point defect aggregates exist, and the region [P _I ] is adjacent to the region [I] and is the lowest interstitial silicon capable of forming interstitial dislocations A region having an interstitial silicon type point defect concentration less than the type point defect concentration, wherein the region [P _V ] is adjacent to the region [V] and can form an oxidation-induced stacking fault. an area having a vacancy type point defect concentration below defect concentration Cormorant.

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