JP2008182243A - 複数のゲート誘電体組成およびゲート誘電体厚を有する集積半導体チップならびにその製造方法 - Google Patents
複数のゲート誘電体組成およびゲート誘電体厚を有する集積半導体チップならびにその製造方法 Download PDFInfo
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- JP2008182243A JP2008182243A JP2008014311A JP2008014311A JP2008182243A JP 2008182243 A JP2008182243 A JP 2008182243A JP 2008014311 A JP2008014311 A JP 2008014311A JP 2008014311 A JP2008014311 A JP 2008014311A JP 2008182243 A JP2008182243 A JP 2008182243A
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- 239000004065 semiconductor Substances 0.000 title description 10
- 239000000203 mixture Substances 0.000 title description 9
- 238000004519 manufacturing process Methods 0.000 title description 6
- 238000000034 method Methods 0.000 claims abstract description 114
- 239000003989 dielectric material Substances 0.000 claims abstract description 88
- 230000008569 process Effects 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 230000003647 oxidation Effects 0.000 claims abstract description 52
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 52
- 239000000463 material Substances 0.000 claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 238000000059 patterning Methods 0.000 claims abstract 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 5
- 229910004129 HfSiO Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000032798 delamination Effects 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims 1
- 239000007858 starting material Substances 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 10
- 238000001459 lithography Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000003491 array Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- -1 HfSiON Inorganic materials 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【解決手段】方法は、基板の上に材料を形成するステップと、この材料にパターンを形成して、材料の部分を除去し、その下の基板の部分を露出させるステップとを含む。この方法はさらに、酸化プロセスを実行して、基板の露出した部分の上および材料と基板の間の界面に酸化層を形成するステップを含む。回路は、非クリティカル・デバイスと、この非クリティカル・デバイスの部分として形成された酸化物とを含む。この回路内のクリティカル・デバイスの部分として、基板の上に高K誘電材料が形成される。この高K誘電材料とその下の基板の間に酸化物ベースの界面が提供される。第2の方法は、最初の材料として窒化物または酸窒化物を形成する。
【選択図】図4
Description
10a 窒化された高K誘電材料
12 レジスト層
14 薄い酸化物
16 酸化層
16a 酸窒化層
18 薄い酸化層
18a 薄い酸化または酸窒化層
20 窒化層
Claims (13)
- 基板の上に材料を形成するステップと、
前記材料にパターン化して、前記材料の部分を除去し、当該部分の下の前記基板の部分を露出させるステップと、
酸化プロセスにより、前記基板の露出した前記部分の上および前記材料と前記基板の間の界面に酸化層を形成するステップと
を含む方法。 - 前記材料を形成する前記ステップの前に前記基板を前洗浄するステップをさらに含む、請求項1に記載の方法。
- 前記材料が高K誘電材料である、請求項1に記載の方法。
- 前記高K誘電材料がHfSiOxまたはHfO2である、請求項3に記載の方法。
- パターン化する前記ステップが、前記高K誘電材料のクリティカル領域上の部分の上にレジスト層を付着させるステップと、剥離によって生じる損傷が前記クリティカル領域から非クリティカル領域へ転移するように、前記非クリティカル領域上の保護されていない高K誘電材料を除去するステップとを含む、請求項3に記載の方法。
- 前記酸化が低温で実行され、
前記高K誘電材料が前記酸化プロセスを妨げ、その結果、前記基板と前記高K誘電材料の間の前記界面が形成される、
請求項3に記載の方法。 - 前記低温が400℃以下である、請求項6に記載の方法。
- 前記酸化プロセス後に窒化プロセスを実行して、前記材料および前記酸化層の上に窒素ベースの層を形成するステップをさらに含み、前記窒化が低温で実行される、請求項1に記載の方法。
- 前記窒化プロセスが、前記酸化物内の漏れ電流を低減させ、ドーパントに対する拡散障壁を提供して、前記基板中にホウ素が入り込むことを防ぐ、請求項8に記載の方法。
- 前記酸化プロセスの前に窒化プロセスを実行するステップをさらに含み、前記窒化が低温で実行される、請求項1に記載の方法。
- 窒化物プロセスを実行して前記材料を形成するステップをさらに含む、請求項8に記載の方法。
- 基板の上に高K誘電材料を形成するステップと、
前記高K誘電材料をパターン化して、前記基板の非クリティカル部分を露出させるステップと、
低温酸化プロセスにより、前記基板の露出した前記部分の上および前記高K誘電材料と前記基板の間の界面に酸化層を形成するステップと
を含む方法。
- 酸化物ゲート誘電体を含むように形成された非クリティカル・デバイスと、
高K誘電材料を含み、前記高K誘電材料とその下の基板との間に酸化物ベースの界面を含むクリティカル・デバイスと
を含む回路。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/627,001 US7518145B2 (en) | 2007-01-25 | 2007-01-25 | Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same |
Publications (1)
Publication Number | Publication Date |
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JP2008182243A true JP2008182243A (ja) | 2008-08-07 |
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JP2008014311A Pending JP2008182243A (ja) | 2007-01-25 | 2008-01-24 | 複数のゲート誘電体組成およびゲート誘電体厚を有する集積半導体チップならびにその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7518145B2 (ja) |
JP (1) | JP2008182243A (ja) |
CN (1) | CN100580874C (ja) |
TW (1) | TW200901321A (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8039381B2 (en) | 2008-09-12 | 2011-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photoresist etch back method for gate last process |
US8779530B2 (en) | 2009-12-21 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate structure of a field effect transistor |
US20120313186A1 (en) * | 2011-06-08 | 2012-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polysilicon gate with nitrogen doped high-k dielectric and silicon dioxide |
CN108122915B (zh) * | 2016-11-30 | 2020-10-16 | 中芯国际集成电路制造(上海)有限公司 | 一种sram存储器件及制备方法、电子装置 |
Citations (11)
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JP2003282873A (ja) | 2002-03-22 | 2003-10-03 | Sony Corp | 半導体装置およびその製造方法 |
JP2004079606A (ja) | 2002-08-12 | 2004-03-11 | Fujitsu Ltd | 高誘電率膜を有する半導体装置及びその製造方法 |
JP2004179656A (ja) * | 2002-11-25 | 2004-06-24 | Texas Instruments Inc | 二重の窒化物形成処理を用いた信頼性ある高電圧ゲート誘電層と方法 |
JP2004289081A (ja) | 2003-03-25 | 2004-10-14 | Matsushita Electric Ind Co Ltd | プラズマ窒化処理装置及びその処理方法 |
JP2004349627A (ja) * | 2003-05-26 | 2004-12-09 | Semiconductor Leading Edge Technologies Inc | 半導体装置の製造方法 |
JP2005223289A (ja) * | 2004-02-09 | 2005-08-18 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2005322900A (ja) * | 2004-04-09 | 2005-11-17 | Tokyo Electron Ltd | ゲート絶縁膜の形成方法ならびにコンピュータ読取可能な記憶媒体およびコンピュータプログラム |
JP2005327902A (ja) * | 2004-05-14 | 2005-11-24 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2006210793A (ja) * | 2005-01-31 | 2006-08-10 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2008021935A (ja) * | 2006-07-14 | 2008-01-31 | Fujitsu Ltd | 電子デバイス及びその製造方法 |
JP2008066715A (ja) * | 2006-08-10 | 2008-03-21 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Family Cites Families (3)
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CN100342500C (zh) * | 2000-09-19 | 2007-10-10 | 马特森技术公司 | 形成介电薄膜的方法 |
US6787421B2 (en) | 2002-08-15 | 2004-09-07 | Freescale Semiconductor, Inc. | Method for forming a dual gate oxide device using a metal oxide and resulting device |
US6706581B1 (en) | 2002-10-29 | 2004-03-16 | Taiwan Semiconductor Manufacturing Company | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices |
-
2007
- 2007-01-25 US US11/627,001 patent/US7518145B2/en not_active Expired - Fee Related
-
2008
- 2008-01-22 TW TW097102308A patent/TW200901321A/zh unknown
- 2008-01-24 JP JP2008014311A patent/JP2008182243A/ja active Pending
- 2008-01-24 CN CN200810003807.5A patent/CN100580874C/zh not_active Expired - Fee Related
Patent Citations (11)
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JP2003282873A (ja) | 2002-03-22 | 2003-10-03 | Sony Corp | 半導体装置およびその製造方法 |
JP2004079606A (ja) | 2002-08-12 | 2004-03-11 | Fujitsu Ltd | 高誘電率膜を有する半導体装置及びその製造方法 |
JP2004179656A (ja) * | 2002-11-25 | 2004-06-24 | Texas Instruments Inc | 二重の窒化物形成処理を用いた信頼性ある高電圧ゲート誘電層と方法 |
JP2004289081A (ja) | 2003-03-25 | 2004-10-14 | Matsushita Electric Ind Co Ltd | プラズマ窒化処理装置及びその処理方法 |
JP2004349627A (ja) * | 2003-05-26 | 2004-12-09 | Semiconductor Leading Edge Technologies Inc | 半導体装置の製造方法 |
JP2005223289A (ja) * | 2004-02-09 | 2005-08-18 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2005322900A (ja) * | 2004-04-09 | 2005-11-17 | Tokyo Electron Ltd | ゲート絶縁膜の形成方法ならびにコンピュータ読取可能な記憶媒体およびコンピュータプログラム |
JP2005327902A (ja) * | 2004-05-14 | 2005-11-24 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2006210793A (ja) * | 2005-01-31 | 2006-08-10 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2008021935A (ja) * | 2006-07-14 | 2008-01-31 | Fujitsu Ltd | 電子デバイス及びその製造方法 |
JP2008066715A (ja) * | 2006-08-10 | 2008-03-21 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
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TW200901321A (en) | 2009-01-01 |
US7518145B2 (en) | 2009-04-14 |
US20080179714A1 (en) | 2008-07-31 |
CN101231942A (zh) | 2008-07-30 |
CN100580874C (zh) | 2010-01-13 |
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