JP2008177270A - 半導体装置および、その製造方法 - Google Patents
半導体装置および、その製造方法 Download PDFInfo
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- JP2008177270A JP2008177270A JP2007007962A JP2007007962A JP2008177270A JP 2008177270 A JP2008177270 A JP 2008177270A JP 2007007962 A JP2007007962 A JP 2007007962A JP 2007007962 A JP2007007962 A JP 2007007962A JP 2008177270 A JP2008177270 A JP 2008177270A
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- Prior art keywords
- semiconductor device
- diffusion layer
- fuse
- silicon substrate
- trimming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【解決手段】アルミヒューズ1の電極引き出し部である拡散層6が保護膜9によって直接被覆されている。この保護膜9の素材にはドープドポリシリコンが使用されている。
【選択図】図3B
Description
2 スルーホール
3 タングステン
4 コンタクト
5 シリコン基盤
6 拡散層
7 レーザー光
8 レーザスポット
9 保護膜(ドープドポリシリコン)
Claims (5)
- シリコン基盤の主面側に形成された、レーザートリミングが実施される1つ以上のトリミング対象素子と、該トリミング対象素子の位置よりも下方に配置された該トリミング対象素子の電極引き出し部とを有する半導体装置において、
前記電極引き出し部が、前記シリコン基盤の最表層に形成された拡散層で構成され、該拡散層が、前記シリコン基盤上に直接形成された保護膜によって被覆されていることを特徴とする半導体装置。 - 前記保護膜が、ポリシリコンに不純物を注入したドープドポリシリコンで構成されている、請求項1に記載の半導体装置。
- 前記保護膜の融点が前記トリミング対象素子の融点よりも高い、請求項1または2に記載の半導体装置。
- 前記トリミング対象素子が金属製のヒューズである、請求項1から3のいずれかに記載の半導体装置。
- シリコン基盤の主面側に形成された、レーザートリミングが実施される1つ以上のトリミング対象素子と、該トリミング対象素子の位置よりも下方に配置された該トリミング対象素子の電極引き出し部とを有する半導体装置の製造方法であって、
前記電極引き出し部を、前記シリコン基盤の最表層に形成した拡散層によって形成し、該拡散層を、ポリシリコンに不純物を注入したドープドポリシリコンで被覆し、該ドープドポリシリコンを含む前記シリコン基盤上に少なくとも層間膜を形成し、該層間膜に電気的コンタクト部を形成し、該層間膜上に前記トリミング対象素子を形成するとともに該電気的コンタクト部の上端に前記トリミング対象素子の端部を接続する、半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007007962A JP4400620B2 (ja) | 2007-01-17 | 2007-01-17 | 半導体装置および、その製造方法 |
US12/007,844 US20080211058A1 (en) | 2007-01-17 | 2008-01-16 | Semiconductor device and method of manufacturing same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007007962A JP4400620B2 (ja) | 2007-01-17 | 2007-01-17 | 半導体装置および、その製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008177270A true JP2008177270A (ja) | 2008-07-31 |
JP4400620B2 JP4400620B2 (ja) | 2010-01-20 |
Family
ID=39704097
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007007962A Expired - Fee Related JP4400620B2 (ja) | 2007-01-17 | 2007-01-17 | 半導体装置および、その製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20080211058A1 (ja) |
JP (1) | JP4400620B2 (ja) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6295721B1 (en) * | 1999-12-28 | 2001-10-02 | Taiwan Semiconductor Manufacturing Company | Metal fuse in copper dual damascene |
JP4936643B2 (ja) * | 2004-03-02 | 2012-05-23 | 株式会社リコー | 半導体装置及びその製造方法 |
JP4964472B2 (ja) * | 2006-01-31 | 2012-06-27 | 半導体特許株式会社 | 半導体装置 |
-
2007
- 2007-01-17 JP JP2007007962A patent/JP4400620B2/ja not_active Expired - Fee Related
-
2008
- 2008-01-16 US US12/007,844 patent/US20080211058A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP4400620B2 (ja) | 2010-01-20 |
US20080211058A1 (en) | 2008-09-04 |
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