JP2008526007A - アンチフューズセル及びその製造方法 - Google Patents
アンチフューズセル及びその製造方法 Download PDFInfo
- Publication number
- JP2008526007A JP2008526007A JP2007547544A JP2007547544A JP2008526007A JP 2008526007 A JP2008526007 A JP 2008526007A JP 2007547544 A JP2007547544 A JP 2007547544A JP 2007547544 A JP2007547544 A JP 2007547544A JP 2008526007 A JP2008526007 A JP 2008526007A
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- JP
- Japan
- Prior art keywords
- mos transistor
- field region
- track
- insulating field
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
Claims (10)
- ケイ素化金属膜(12, 13)で覆われたソース(7) 及びドレイン(8) 領域を有する、MOS集積回路のMOSトランジスタと、
ケイ素化金属の金属がドレイン及び/又はソース接合を通じて拡散するように加熱電流を流すべくなしてあり、MOSトランジスタを少なくとも部分的に囲む少なくとも1つの抵抗性膜のトラック(24)と
を備えることを特徴とするアンチフューズセル。 - 抵抗性のトラックは、MOSトランジスタを囲む絶縁場領域(22)上で、MOSトランジスタの近傍に設けられている。
ことを特徴とする請求項1に記載のセル。 - MOSトランジスタを囲む絶縁場領域は、同一の集積回路中の他のMOSトランジスタを囲む絶縁場領域よりも広い
ことを特徴とする請求項2に記載のセル。 - トラック(24)は、MOSトランジスタのゲート(5) を形成するのに用いられるのと同様の膜でつくられている
ことを特徴とする請求項1に記載のセル。 - トラック(24)には電流を流すための端子(25, 26)が設けられている
ことを特徴とする請求項1に記載のセル。 - ケイ素化金属の膜を含むソース及びドレイン領域を有しており、絶縁場領域により囲まれている標準的なMOSトランジスタを備える集積回路中にアンチフューズセルを製造する方法において、
各アンチフューズセルは追加のMOSトランジスタからなることを特徴とし、更に、
標準的なMOSトランジスタに関してより、追加のMOSトランジスタに関して、より広い絶縁場領域を設けるステップと、
追加のMOSトランジスタ及び標準的なMOSトランジスタを同時に形成するステップと、
絶縁場領域上で、追加のMOSトランジスタの周辺に少なくとも1つの抵抗性のトラックを形成し、同時にトランジスタのゲートの導伝膜を形成するステップと
を含むことを特徴とする方法。 - ケイ素化金属はケイ素化ニッケルであることを特徴とする請求項6に記載の方法。
- 各MOSトランジスタのゲート長は100nmより短いことを特徴とする請求項6に記載の方法。
- 絶縁場領域は、各標準的なトランジスタの周囲では約200nmの幅であり、各アンチフューズセルの周囲では5000nmの幅であり、
絶縁場領域は数百nmの深さである
ことを特徴とする請求項6に記載の方法。 - 集積回路の動作において通常印加される電圧と同様の範囲にある電圧を抵抗性のトラックに印加することによりアンチフューズセルに書き込むステップを更に含むことを特徴とする請求項6に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04107005 | 2004-12-27 | ||
PCT/EP2005/057150 WO2006069982A1 (en) | 2004-12-27 | 2005-12-23 | An anti-fuse cell and its manufacturing process |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008526007A true JP2008526007A (ja) | 2008-07-17 |
Family
ID=35976599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007547544A Pending JP2008526007A (ja) | 2004-12-27 | 2005-12-23 | アンチフューズセル及びその製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7989914B2 (ja) |
EP (1) | EP1831927B1 (ja) |
JP (1) | JP2008526007A (ja) |
CN (1) | CN100472773C (ja) |
DE (1) | DE602005020979D1 (ja) |
TW (1) | TW200629543A (ja) |
WO (1) | WO2006069982A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009004578A (ja) * | 2007-06-21 | 2009-01-08 | Toshiba Corp | 不揮発性半導体記憶装置 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100187638A1 (en) * | 2004-12-27 | 2010-07-29 | Koninklijke Philips Electronics N.V. | Anti-fuse cell and its manufacturing process |
US7820492B2 (en) * | 2007-05-25 | 2010-10-26 | Kabushiki Kaisha Toshiba | Electrical fuse with metal silicide pipe under gate electrode |
US8692310B2 (en) | 2009-02-09 | 2014-04-08 | Spansion Llc | Gate fringing effect based channel formation for semiconductor device |
US8049299B2 (en) * | 2009-02-25 | 2011-11-01 | Freescale Semiconductor, Inc. | Antifuses with curved breakdown regions |
US8542517B2 (en) | 2011-06-13 | 2013-09-24 | International Business Machines Corporation | Low voltage programmable mosfet antifuse with body contact for diffusion heating |
CN102254846B (zh) * | 2011-07-04 | 2016-01-27 | 上海华虹宏力半导体制造有限公司 | 半导体器件中金属硅化物层电阻的仿真方法 |
US8815736B2 (en) * | 2011-08-25 | 2014-08-26 | Globalfoundries Inc. | Methods of forming metal silicide regions on semiconductor devices using different temperatures |
CN103456710B (zh) * | 2012-06-04 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Mos器件及其制造方法 |
TWI511144B (zh) * | 2014-04-03 | 2015-12-01 | Sidense Corp | 抗熔絲記憶單元 |
US9455222B1 (en) * | 2015-12-18 | 2016-09-27 | Texas Instruments Incorporated | IC having failsafe fuse on field dielectric |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02294067A (ja) * | 1989-03-31 | 1990-12-05 | Texas Instr Inc <Ti> | 電界効果トランジスタの選択的プログラミング方法 |
JPH04192459A (ja) * | 1990-11-27 | 1992-07-10 | Toshiba Corp | 半導体メモリセル |
JPH04294577A (ja) * | 1991-03-22 | 1992-10-19 | Ricoh Co Ltd | プログラム可能な半導体装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5298784A (en) * | 1992-03-27 | 1994-03-29 | International Business Machines Corporation | Electrically programmable antifuse using metal penetration of a junction |
US6794726B2 (en) * | 2002-04-17 | 2004-09-21 | International Business Machines Corporation | MOS antifuse with low post-program resistance |
US20040124458A1 (en) * | 2002-12-31 | 2004-07-01 | Chandrasekharan Kothandaraman | Programmable fuse device |
JP2004241558A (ja) * | 2003-02-05 | 2004-08-26 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法、半導体集積回路及び不揮発性半導体記憶装置システム |
US7180102B2 (en) * | 2003-09-30 | 2007-02-20 | Agere Systems Inc. | Method and apparatus for using cobalt silicided polycrystalline silicon for a one time programmable non-volatile semiconductor memory |
US7439168B2 (en) * | 2004-10-12 | 2008-10-21 | Dcg Systems, Inc | Apparatus and method of forming silicide in a localized manner |
-
2005
- 2005-12-19 TW TW094144994A patent/TW200629543A/zh unknown
- 2005-12-23 US US11/793,990 patent/US7989914B2/en active Active
- 2005-12-23 EP EP05825195A patent/EP1831927B1/en not_active Expired - Fee Related
- 2005-12-23 JP JP2007547544A patent/JP2008526007A/ja active Pending
- 2005-12-23 CN CNB2005800449382A patent/CN100472773C/zh not_active Expired - Fee Related
- 2005-12-23 DE DE602005020979T patent/DE602005020979D1/de active Active
- 2005-12-23 WO PCT/EP2005/057150 patent/WO2006069982A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02294067A (ja) * | 1989-03-31 | 1990-12-05 | Texas Instr Inc <Ti> | 電界効果トランジスタの選択的プログラミング方法 |
JPH04192459A (ja) * | 1990-11-27 | 1992-07-10 | Toshiba Corp | 半導体メモリセル |
JPH04294577A (ja) * | 1991-03-22 | 1992-10-19 | Ricoh Co Ltd | プログラム可能な半導体装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009004578A (ja) * | 2007-06-21 | 2009-01-08 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP4510057B2 (ja) * | 2007-06-21 | 2010-07-21 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US7796460B2 (en) | 2007-06-21 | 2010-09-14 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
EP1831927A1 (en) | 2007-09-12 |
EP1831927B1 (en) | 2010-04-28 |
CN100472773C (zh) | 2009-03-25 |
DE602005020979D1 (de) | 2010-06-10 |
WO2006069982A1 (en) | 2006-07-06 |
TW200629543A (en) | 2006-08-16 |
CN101091249A (zh) | 2007-12-19 |
US20090102014A1 (en) | 2009-04-23 |
US7989914B2 (en) | 2011-08-02 |
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