JP2008157770A - Signal selection circuit and semiconductor testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal selection circuit and a semiconductor testing device capable of speed heightening of signal switching, cost reduction and miniaturization, by shortening greatly a settling time of a low-pass filter, and by reducing the number of A/D conversion parts. <P>SOLUTION: A representative configuration of the signal selection circuit is characterized by including a plurality of analog signal input parts 152; a plurality of low-pass filters 154 connected respectively to the plurality of analog signal input parts 152; and a multiplexer 156 connected to the plurality of low-pass filters 154, for selecting a signal alternatively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus for conducting an electrical test of a device under test such as an IC or LSI, and particularly has a feature in a signal selection circuit.

  In recent years, integrated circuits (ICs) have been increased in capacity, speed, and size (high density). In a device having such an integrated circuit, a high-speed and complicated process is required for electrical function testing as the density of the integrated circuit increases. In a semiconductor test apparatus for performing such a test, a device under test (Device Under Test: hereinafter referred to as “DUT”) includes a memory, an LSI (Large Scale Integration), and an SOC (System On a Chip). Also called system LSI). Note that the SOC is an LSI in which a plurality of circuits that realize a specific function are combined and mounted on one chip.

  A semiconductor test apparatus for testing a DUT includes an apparatus main body, a test head, and a performance board as disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 6-324115: FIG. 4 in particular). The apparatus main body measures the output of a constant voltage, a constant current, etc., and the input from the DUT with respect to the DUT. The test head includes a driver, a comparator, a drive circuit that drives a relay, and the like. The performance board is equipped with a plurality of DUTs, and electrically connects the test head and the DUT. In the test head, when the signal output from the DUT is an analog signal, the signal is converted into a digital signal in a PE card (Pin Electronics Card) mounted on the test head.

  Since the DUT has a large number of pins, the signal paths output from the DUT inevitably increase. The analog signal needs to be subjected to A / D (Analog / Digital) conversion after removing high-frequency noise by a low-pass filter. Japanese Patent Application Laid-Open No. 9-97393 (particularly FIG. 1) proposes a multipoint measuring apparatus suitable for switching and measuring the outputs of a large number of sensors in a short time. Patent Document 2 discloses a plurality of sensor groups grouped into a predetermined number, a plurality of multiplexers constituting first-stage switching means for sequentially switching and outputting the output signals of the sensors for each sensor group, A configuration including a plurality of low-pass filters to which the output signals of the multiplexers are respectively input and a multiplexer constituting second-stage switching means for switching and extracting the output signals of these low-pass filters is described.

FIG. 5 is a diagram for explaining a conventional signal selection circuit, in which a part of the configuration of Patent Document 2 is simplified for the convenience of explanation. A plurality of switches 702 are connected to the plurality of sensors 701, respectively. The plurality of switches 702 can be configured by a multiplexer together. The plurality of switches 702 are connected to a low pass filter 703 (LPF: Low Pass Filter), and are input to the A / D conversion unit 704 after high frequency noise is removed. By switching the plurality of switches 702, analog signals input from the plurality of sensors 701 can be selectively selected and converted into digital signals. By switching the sensor 701 with the switch 702 in this manner, the number of low-pass filters 703 and A / D conversion units 704 can be reduced, and production cost and size can be reduced.
JP-A-6-324115 JP-A-9-97393

  In the configuration described in Patent Document 2, an RC filter is generally used as the low-pass filter 703. The A / D conversion needs to be executed after waiting for the settling time of the low-pass filter 703. Therefore, each time the plurality of switches 702 are switched for the plurality of sensors 701, the settling time must be waited.

  In recent years, the number of pins has been steadily increasing due to the complexity and sophistication of DUTs. For this reason, as the number of sensors 701 handled by one low-pass filter and A / D converter increases, the time required for A / D conversion for all the sensors 701 (that is, the time required for the test) becomes longer. Accordingly, the processing speed can be improved by grouping the sensors 701 into a predetermined number, and providing a low-pass filter 703 and an A / D conversion unit 704 for each group to perform parallel processing.

  Nevertheless, the settling time of the RC filter is very long compared to the time required for A / D conversion itself. For this reason, even if a high-speed A / D converter is used, it is difficult to dramatically reduce the time.

  For example, when the cutoff frequency of the low-pass filter 703 is 72 KHz, the settling time of the low-pass filter 703 is about 27 microseconds (12 times the time constant). On the other hand, the time required for A / D conversion is about 2 microseconds at 500 ksample / s. The number of pins handled for one PE card is 64, that is, the sensor 701 (for example, PMU: Parametric Measurement Unit) has 64 channels.

  Such shortening of the settling time of the low-pass filter is an important issue in order to increase the speed of the semiconductor test apparatus in the future. Although the time can be shortened to some extent by grouping the sensors 701 as described above, the difference between the time required for A / D conversion and the settling time is still large, and the number of A / D converters 704 increases. There is a problem. Further, if an active filter is configured using an operational amplifier, there is a possibility of speeding up, but there is a problem that the production cost increases.

  Therefore, the present invention greatly reduces the settling time of the low-pass filter and reduces the number of A / D converters, thereby enabling signal selection that can speed up the switching of signals, reduce costs, and reduce the size. An object is to provide a circuit and a semiconductor test apparatus.

  In order to solve the above problems, a typical configuration of a signal selection circuit according to the present invention is a circuit that selectively selects a plurality of analog signals, and includes a plurality of analog signal input units and a plurality of analog signals. It is characterized by comprising a plurality of low-pass filters respectively connected to the input section and a multiplexer connected to the plurality of low-pass filters and selectively selecting signals.

  According to the above configuration, since the low-pass filter is on the input unit side of the multiplexer and receives the signal from the input unit in advance, the low-pass filter is set in advance. Therefore, it is possible to switch signals very quickly without waiting for the settling time. Further, since the switching is fast, more pins (that is, more analog signal input units) can be handled for one A / D conversion unit, and the number of A / D conversion units can be reduced. Therefore, cost reduction and downsizing of the apparatus can be achieved.

  The low pass filter may be an RC filter. The RC filter can be configured inexpensively, but the settling time is long. However, according to the present invention, it is not necessary to wait for the settling time, so that the RC filter can be preferably used.

  Furthermore, an A / D converter that converts an analog signal output from the multiplexer into a digital signal may be provided. By converting an analog signal from which high-frequency noise has been removed by a low-pass filter into a digital signal, it can be suitably processed by a computer or the like.

  A typical configuration of a semiconductor test apparatus according to the present invention is a semiconductor test apparatus that performs an electrical test of a device under test, and includes a plurality of analog signal input sections to which signals output from the device under test are input. , A plurality of low-pass filters respectively connected to a plurality of analog signal input units, a multiplexer connected to the plurality of low-pass filters and alternatively selecting a signal, and an analog signal output from the multiplexer being converted into a digital signal And an A / D converter. As a result, the speed of the semiconductor test apparatus can be increased, and the cost can be reduced and the apparatus can be reduced in size.

  The analog signal input unit may be included in an input / output unit including an analog signal output unit that supplies a signal to the device under test. As a result, the PMU can be used as an input / output for the DUT, and the circuit configuration can be simplified.

  According to the present invention, a signal capable of speeding up signal switching, reducing cost, and downsizing by significantly reducing the settling time of the low-pass filter and reducing the number of A / D converters. A selection circuit and a semiconductor test apparatus can be provided.

  Embodiments of a signal selection circuit and a semiconductor test apparatus according to the present invention will be described. FIG. 1 is a schematic configuration diagram of a semiconductor test apparatus, FIG. 2 is a diagram illustrating a configuration of a main part of a PE card, and FIG. 3 is a diagram illustrating an analog signal input unit. Note that dimensions, materials, and other specific numerical values shown in the following examples are merely examples for facilitating the understanding of the invention, and do not limit the present invention unless otherwise specified.

  A semiconductor test apparatus 100 shown in FIG. 1 includes a main body 110 and a test head 120. A performance board 130 is placed on the test head 120, and a DUT 140 is placed on the performance board 130. In the present embodiment, the DUT 140 is a memory, an LSI (Large Scale Integration), an SOC (System On a Chip), or the like.

  The main body 110 is provided with a central control unit 114 that performs a test process set through a control computer 112. The test head 120 is provided with a test terminal connected to each device terminal of the DUT 140 and a PE card 122 provided with, for example, 32 pin modules connected to the test terminal and performing a test function. The PE card 122 reflects the command related to the function test from the main body 110 on the test terminal. The performance board 130 has a structure that can be fitted to the test head 120 and on which the DUT 140 can be mounted, and electrically connects a plurality of test terminals to the device terminals of the DUT 140.

  As shown in FIG. 2, the PE card 122 includes a plurality of analog signal input units 152 (152a to n), a plurality of low-pass filters 154 (154a to n), a multiplexer 156, an A / D conversion unit 158, and an FPGA 160. ing.

  The analog signal input unit 152 receives a signal output from the DUT. The analog signal input unit 152 is provided with, for example, 64 channels per PE card 122 (responsible for 64 pins of the DUT). As shown in FIG. 3, the analog signal input unit 152 may be included in the input / output unit 150 including an analog signal output unit 151 that gives a signal to the DUT. Such a circuit can be configured using a PMU (Parametric Measurement Unit), and the circuit configuration for input and output can be simplified.

  One low-pass filter 154 is connected to each of the plurality of analog signal input units 152. In the present embodiment, the low-pass filter 154 is configured by an RC filter (a filter including a resistor directly connected to a circuit and a grounded capacitor).

  Multiplexer 156 is connected to a plurality of low pass filters 154 and alternatively selects a signal. A signal that is not selected may theoretically have a very small amount of current flowing to the ground, but can be ignored in the configuration of this embodiment.

  The A / D converter 158 converts the analog signal output from the multiplexer 156 into a digital signal. The converted digital signal is sent to the control computer 112 through the FPGA 160. The FPGA 160 has a function of controlling operations of the analog signal input unit 152, the multiplexer 156, and the A / D conversion unit 158 in addition to data processing.

  According to the above configuration, the signal always reaches the multiplexer 156 in all the analog signal input units 152. Since the low-pass filter 154 is closer to the analog signal input unit 152 than the multiplexer 156 and receives a signal from the analog signal input unit 152 in advance, the low-pass filter 154 starts to receive a signal from the analog signal input unit 152. From (without waiting for switching), settling has started and completed in advance.

  In other words, settling is started simultaneously in all the low-pass filters 154. Therefore, the time required to wait for settling when performing the test is only the time for the first time (time for one time). After that, after switching the multiplexer 156, data acquisition is performed without waiting for the settling time. Good. As a result, it is possible to switch signals at a very high speed, and it is possible to drastically shorten the switching time as compared with the case of waiting for settling every time the switch is switched as in the prior art.

  Further, in order to make switching faster, analog signal input units 152 may be grouped in one PE card 122, and a multiplexer 156 and an A / D conversion unit 158 may be provided for each group to perform parallel processing. . Even in this case, since switching is performed at high speed, more pins (that is, more analog signal input units 152) can be handled for one A / D conversion unit 158. Therefore, even if grouping is performed, the number of groups can be reduced as compared with the prior art, and the number of A / D conversion units 158 can be reduced. Therefore, cost reduction and downsizing of the apparatus can be achieved.

  The RC filter has a relatively long settling time, but according to the present invention, it is not necessary to wait for the settling time, and therefore it can be suitably used without any trouble. Specifically, the resistor and the capacitor can be configured by, for example, a 1005 size (length 1 mm, width 0.5 mm) chip. Therefore, even if the same number of low-pass filters 154 as the number of analog signal input units 152 are configured, the substrate size does not increase. Further, since such chip parts are inexpensive, an increase in production cost can be minimized even though the number of low-pass filters 154 increases.

  In the present embodiment, the signal selection circuit is applied to a semiconductor test apparatus. However, the present invention is not limited to this and can be configured as a signal selection circuit provided in an arbitrary apparatus.

  That is, as shown in FIG. 4, a plurality of analog signal input units 152, a plurality of low-pass filters 154 connected to the plurality of analog signal input units 152, and a plurality of low-pass filters 154, respectively, are alternatively signaled. And a multiplexer 156 that selects the signal selection circuit according to the present invention can be configured. With this configuration, it is possible to speed up signal selection, reduce costs, and reduce the size of the apparatus.

  Although the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to such examples. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  The present invention can be used as, for example, a semiconductor test apparatus that performs an electrical test of a device under test such as an IC or LSI, and a signal selection circuit provided therein.

It is a schematic block diagram of a semiconductor test apparatus. It is a figure explaining the principal part structure of a PE card. It is a figure explaining an analog signal input part. It is a figure explaining the minimum structure of a signal selection circuit. It is a figure explaining the conventional signal selection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Semiconductor test apparatus 110 ... Main body 112 ... Control computer 114 ... Central control part 120 ... Test head 122 ... PE card 130 ... Performance board 140 ... DUT
150 ... I / O unit 151 ... Analog signal output unit 152 ... Analog signal input unit 154 ... Low-pass filter 156 ... Multiplexer 158 ... A / D conversion unit 160 ... FPGA
701 ... Sensor 702 ... Switch 703 ... Low-pass filter 704 ... A / D converter

Claims (5)

A circuit that selectively selects a plurality of analog signals,
A plurality of analog signal inputs;
A plurality of low-pass filters respectively connected to the plurality of analog signal input units;
A signal selection circuit, comprising: a multiplexer connected to the plurality of low-pass filters to selectively select a signal.   2. The signal selection circuit according to claim 1, wherein the low-pass filter is an RC filter.   2. The signal selection circuit according to claim 1, further comprising an A / D converter for converting an analog signal output from the multiplexer into a digital signal. A semiconductor test apparatus for conducting an electrical test of a device under test,
A plurality of analog signal input units to which signals output from the device under test are input;
A plurality of low-pass filters respectively connected to the plurality of analog signal input units;
A multiplexer connected to the plurality of low-pass filters to selectively select a signal;
A semiconductor test apparatus comprising: an A / D converter that converts an analog signal output from the multiplexer into a digital signal.   5. The semiconductor test apparatus according to claim 4, wherein the analog signal input unit is included in an input / output unit including an analog signal output unit that supplies a signal to the device under test.

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